From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 267DBCA0FF0 for ; Fri, 1 Sep 2023 08:10:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348639AbjIAIKS (ORCPT ); Fri, 1 Sep 2023 04:10:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343832AbjIAIKK (ORCPT ); Fri, 1 Sep 2023 04:10:10 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECB9210EC; Fri, 1 Sep 2023 01:09:59 -0700 (PDT) X-UUID: ee13d6dc489e11ee8051498923ad61e6-20230901 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CxV19o0KC50J6ousdCuLaiAFSegaAoRHAMQOW5YpiiM=; b=XHr71t8ZjwxzT2fdOMY2vTfZNtfx6bq1oit5aXzYVdsWeVt3/w56RROC1+vZF7J8q7wbZK7QAk9s+konLu/m69BGsZkF9PTzyTlKkhXPO5h3NlBbU4eTSo3DbjnV+QgA0auZJtK+o7qOvOLyOy2u6hscDTNecjfBpJl2iUPjpvU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:8c0ab339-f6b7-417f-b442-1563f4a6c546,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:6e2d7113-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ee13d6dc489e11ee8051498923ad61e6-20230901 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2132350699; Fri, 01 Sep 2023 16:09:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:51 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 01/14] dt-bindings: remoteproc: mediatek: Improve the rpmsg subnode definition Date: Fri, 1 Sep 2023 16:09:22 +0800 Message-ID: <20230901080935.14571-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Improve the definition of the rpmsg subnode by assigning a distinct node name and adding the definition source of node properties. Signed-off-by: Tinghan Shen Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- .../bindings/remoteproc/mtk,scp.yaml | 31 +++++++++---------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Do= cumentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 895415772d1d..271081df0e46 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -58,6 +58,18 @@ properties: memory-region: maxItems: 1 =20 + cros-ec-rpmsg: + $ref: /schemas/mfd/google,cros-ec.yaml + description: + This subnode represents the rpmsg device. The properties + of this node are defined by the individual bindings for + the rpmsg devices. + + required: + - mediatek,rpmsg-name + + unevaluatedProperties: false + required: - compatible - reg @@ -89,21 +101,7 @@ allOf: reg-names: maxItems: 2 =20 -additionalProperties: - type: object - description: - Subnodes of the SCP represent rpmsg devices. The names of the devices - are not important. The properties of these nodes are defined by the - individual bindings for the rpmsg devices. - properties: - mediatek,rpmsg-name: - $ref: /schemas/types.yaml#/definitions/string-array - description: - Contains the name for the rpmsg device. Used to match - the subnode to rpmsg device announced by SCP. - - required: - - mediatek,rpmsg-name +additionalProperties: false =20 examples: - | @@ -118,7 +116,8 @@ examples: clocks =3D <&infracfg CLK_INFRA_SCPSYS>; clock-names =3D "main"; =20 - cros_ec { + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; }; --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 998ECCA0FE6 for ; Fri, 1 Sep 2023 08:10:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348658AbjIAIK0 (ORCPT ); Fri, 1 Sep 2023 04:10:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348606AbjIAIKM (ORCPT ); Fri, 1 Sep 2023 04:10:12 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE94810FA; Fri, 1 Sep 2023 01:10:01 -0700 (PDT) X-UUID: ee167590489e11ee8051498923ad61e6-20230901 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0v1sHSdRL6Qx9RsSEfvIFRQuGdYV7Ul8S2vCf20EzFw=; b=shnGkAFfYpKU9pPDNDwSIAv89ojRSMSEqUpBsgvuLx4eRkmgCv4AFS71yitTgEX0APLbuboiUlAXjtJHwA0AuN3t2StSd9ErhbKgira6uBS7jqahJdlBBfZRyw4NwiCizQ+FH4e9oWLj/ZNq8YRBMNEx3P9Wup9DcN3LBtXp4iU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:d1ffec80-4cba-4435-b5cb-1bcb5fb0617e,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:6d2d7113-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ee167590489e11ee8051498923ad61e6-20230901 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 162738457; Fri, 01 Sep 2023 16:09:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:51 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 02/14] arm64: dts: mediatek: Update the node name of SCP rpmsg subnode Date: Fri, 1 Sep 2023 16:09:23 +0800 Message-ID: <20230901080935.14571-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Align the node name with the definition in SCP bindings. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Acked-by: Matthias Brugger Tested-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/bo= ot/dts/mediatek/mt8183-kukui.dtsi index 6ce16a265e05..34076ba28fd0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -831,7 +831,7 @@ pinctrl-names =3D "default"; pinctrl-0 =3D <&scp_pins>; =20 - cros_ec { + cros-ec-rpmsg { compatible =3D "google,cros-ec-rpmsg"; mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 0e8b34117090..1bbc994bc109 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1284,7 +1284,7 @@ pinctrl-names =3D "default"; pinctrl-0 =3D <&scp_pins>; =20 - cros-ec { + cros-ec-rpmsg { compatible =3D "google,cros-ec-rpmsg"; mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57373CA0FE6 for ; Fri, 1 Sep 2023 08:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348627AbjIAIKP (ORCPT ); Fri, 1 Sep 2023 04:10:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348587AbjIAIKK (ORCPT ); Fri, 1 Sep 2023 04:10:10 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5C6810DF; Fri, 1 Sep 2023 01:09:59 -0700 (PDT) X-UUID: ed9c7fe2489e11eea33bb35ae8d461a2-20230901 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mHZvfrM0o5UaIt01vL+X0Xi78aCQjddfdApBpcmPqT8=; b=Mhx+x8VAt74DxJEEfwUivpAbIDZYxaNJRgDvYqPFXVVKiggi6htPGtuYkcKJb3UWhS+/E8xE61PxnixsAktVCDZ20mzLJa4Ga4ZeGPsFHkHBWCcVjkEl23zjrMBlQUMAEgpZdx6vEmytVRBhddmXXMGHjLe5b3icIwo2YN1RRPI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:74df6244-9ed7-4718-9ae6-033446d507c6,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:f86333ef-9a6e-4c39-b73e-f2bc08ca3dc5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ed9c7fe2489e11eea33bb35ae8d461a2-20230901 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 109404480; Fri, 01 Sep 2023 16:09:52 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:52 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Tinghan Shen" CC: , , , , , Subject: [PATCH v17 03/14] dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP Date: Fri, 1 Sep 2023 16:09:24 +0800 Message-ID: <20230901080935.14571-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the SCP binding to describe the MT8195 dual-core SCP. Under different applications, the MT8195 SCP can be used as single-core or dual-core. This change keeps the single-core definitions and adds new definitions for the dual-core use case. Signed-off-by: Tinghan Shen Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- .../bindings/remoteproc/mtk,scp.yaml | 145 +++++++++++++++++- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Do= cumentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 271081df0e46..09102dda4942 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt8188-scp - mediatek,mt8192-scp - mediatek,mt8195-scp + - mediatek,mt8195-scp-dual =20 reg: description: @@ -31,10 +32,7 @@ properties: =20 reg-names: minItems: 2 - items: - - const: sram - - const: cfg - - const: l1tcm + maxItems: 3 =20 clocks: description: @@ -70,6 +68,81 @@ properties: =20 unevaluatedProperties: false =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: + description: + Standard ranges definition providing address translations for + local SCP SRAM address spaces to bus addresses. + +patternProperties: + "^scp@[a-f0-9]+$": + type: object + description: + The MediaTek SCP integrated to SoC might be a multi-core version. + The other cores are represented as child nodes of the boot core. + There are some integration differences for the IP like the usage of + address translator for translating SoC bus addresses into address sp= ace + for the processor. + + Each SCP core has own cache memory. The SRAM and L1TCM are shared by + cores. The power of cache, SRAM and L1TCM power should be enabled + before booting SCP cores. The size of cache, SRAM, and L1TCM are var= ied + on differnt SoCs. + + The SCP cores do not use an MMU, but has a set of registers to + control the translations between 32-bit CPU addresses into system bus + addresses. Cache and memory access settings are provided through a + Memory Protection Unit (MPU), programmable only from the SCP. + + properties: + compatible: + enum: + - mediatek,scp-core + + reg: + description: The base address and size of SRAM. + maxItems: 1 + + reg-names: + const: sram + + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + If present, name (or relative path) of the file within the + firmware search path containing the firmware image used when + initializing sub cores of multi-core SCP. + + memory-region: + maxItems: 1 + + cros-ec-rpmsg: + $ref: /schemas/mfd/google,cros-ec.yaml + description: + This subnode represents the rpmsg device. The properties + of this node are defined by the individual bindings for + the rpmsg devices. + + required: + - mediatek,rpmsg-name + + unevaluatedProperties: false + + required: + - compatible + - reg + - reg-names + + additionalProperties: false + required: - compatible - reg @@ -99,7 +172,37 @@ allOf: reg: maxItems: 2 reg-names: + items: + - const: sram + - const: cfg + - if: + properties: + compatible: + enum: + - mediatek,mt8192-scp + - mediatek,mt8195-scp + then: + properties: + reg: + maxItems: 3 + reg-names: + items: + - const: sram + - const: cfg + - const: l1tcm + - if: + properties: + compatible: + enum: + - mediatek,mt8195-scp-dual + then: + properties: + reg: maxItems: 2 + reg-names: + items: + - const: cfg + - const: l1tcm =20 additionalProperties: false =20 @@ -121,3 +224,37 @@ examples: mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; }; + + - | + scp@10500000 { + compatible =3D "mediatek,mt8195-scp-dual"; + reg =3D <0x10720000 0xe0000>, + <0x10700000 0x8000>; + reg-names =3D "cfg", "l1tcm"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x10500000 0x100000>; + + scp@0 { + compatible =3D "mediatek,scp-core"; + reg =3D <0x0 0xa0000>; + reg-names =3D "sram"; + + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; + }; + + scp@a0000 { + compatible =3D "mediatek,scp-core"; + reg =3D <0xa0000 0x20000>; + reg-names =3D "sram"; + + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; + }; + }; --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66A7DCA0FE6 for ; Fri, 1 Sep 2023 08:10:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348644AbjIAIKa (ORCPT ); Fri, 1 Sep 2023 04:10:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233301AbjIAIKN (ORCPT ); Fri, 1 Sep 2023 04:10:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32D531705; Fri, 1 Sep 2023 01:10:02 -0700 (PDT) X-UUID: ee4b66c4489e11ee8051498923ad61e6-20230901 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=j+QYraQbzb9ohLMzNn/JclhKPYuqSnCdv9f3/SYy3Jw=; b=G4eiqd1h5rJ6+U/FA87SdDv7nYCYIWHRSlkvx90uCIFUakcO2f/w/3AbuAyNp/NqHzC0ktL1LEuEPZGO0foO71Qa1zR39cCdVcrzYSkkniDa59cHfOuTwgNVpAcisTVf9dLpV6ABoCc1lEaC2lII2aQ2ChHaeGHLCwaQHfw2uOw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:151c1a0e-35b8-4246-b567-ddc05c5790bb,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:fe6333ef-9a6e-4c39-b73e-f2bc08ca3dc5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ee4b66c4489e11ee8051498923ad61e6-20230901 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1499766843; Fri, 01 Sep 2023 16:09:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:52 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Tinghan Shen" CC: , , , , , Subject: [PATCH v17 04/14] remoteproc: mediatek: Add MT8195 SCP core 1 operations Date: Fri, 1 Sep 2023 16:09:25 +0800 Message-ID: <20230901080935.14571-5-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SCP rproc driver has a set of chip dependent callbacks for boot sequence and IRQ handling. Implement these callbacks for MT8195 SCP core 1. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 9 ++++++ drivers/remoteproc/mtk_scp.c | 55 +++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index ea6fa1100a00..c0905aec3b4b 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_SCP2SPM_IPC_CLR 0x4094 #define MT8192_GIPC_IN_SET 0x4098 #define MT8192_HOST_IPC_INT_BIT BIT(0) +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) =20 #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 @@ -56,6 +57,14 @@ =20 #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) =20 +#define MT8195_CPU1_SRAM_PD 0x1084 +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 +#define MT8195_CORE1_SW_RSTN_SET 0x20004 +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_CFG 0x20034 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288 =20 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index dcc94ee2458d..48e759c2d486 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -176,6 +176,16 @@ static void mt8192_scp_reset_deassert(struct mtk_scp *= scp) writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); } =20 +static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); +} + +static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); +} + static void mt8183_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -212,6 +222,18 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } =20 +static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host =3D readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) + scp_ipi_handler(scp); + + writel(scp_to_host, scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp =3D priv; @@ -453,6 +475,18 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) return 0; } =20 +static int mt8195_scp_c1_before_load(struct mtk_scp *scp) +{ + scp->data->scp_reset_assert(scp); + + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* enable MPU for all memory regions */ + writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + + return 0; +} + static int scp_load(struct rproc *rproc, const struct firmware *fw) { struct mtk_scp *scp =3D rproc->priv; @@ -625,6 +659,15 @@ static void mt8195_scp_stop(struct mtk_scp *scp) writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); } =20 +static void mt8195_scp_c1_stop(struct mtk_scp *scp) +{ + /* Power off CPU SRAM */ + scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* Disable SCP watchdog */ + writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); +} + static int scp_stop(struct rproc *rproc) { struct mtk_scp *scp =3D rproc->priv; @@ -989,6 +1032,18 @@ static const struct mtk_scp_of_data mt8195_of_data = =3D { .host_to_scp_int_bit =3D MT8192_HOST_IPC_INT_BIT, }; =20 +static const struct mtk_scp_of_data mt8195_of_data_c1 =3D { + .scp_clk_get =3D mt8195_scp_clk_get, + .scp_before_load =3D mt8195_scp_c1_before_load, + .scp_irq_handler =3D mt8195_scp_c1_irq_handler, + .scp_reset_assert =3D mt8195_scp_c1_reset_assert, + .scp_reset_deassert =3D mt8195_scp_c1_reset_deassert, + .scp_stop =3D mt8195_scp_c1_stop, + .scp_da_to_va =3D mt8192_scp_da_to_va, + .host_to_scp_reg =3D MT8192_GIPC_IN_SET, + .host_to_scp_int_bit =3D MT8195_CORE1_HOST_IPC_INT_BIT, +}; + static const struct of_device_id mtk_scp_of_match[] =3D { { .compatible =3D "mediatek,mt8183-scp", .data =3D &mt8183_of_data }, { .compatible =3D "mediatek,mt8186-scp", .data =3D &mt8186_of_data }, --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37398CA0FFD for ; Fri, 1 Sep 2023 08:10:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238998AbjIAIKW (ORCPT ); Fri, 1 Sep 2023 04:10:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348595AbjIAIKL (ORCPT ); Fri, 1 Sep 2023 04:10:11 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBACC10F6; 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Fri, 01 Sep 2023 16:09:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:52 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 05/14] remoteproc: mediatek: Extract SCP common registers Date: Fri, 1 Sep 2023 16:09:26 +0800 Message-ID: <20230901080935.14571-6-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is the 1st preliminary steps for probing multi-core SCP. The registers of config and l1tcm are common on single-core SCP and multi-core SCP. Extract these registers out to reduce duplicated fields in mtk_scp when multiple SCP instances are created. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 13 ++- drivers/remoteproc/mtk_scp.c | 164 ++++++++++++++++--------------- drivers/remoteproc/mtk_scp_ipi.c | 4 +- 3 files changed, 96 insertions(+), 85 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index c0905aec3b4b..b04d71277c1f 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -100,17 +100,20 @@ struct mtk_scp_of_data { size_t ipi_buf_offset; }; =20 +struct mtk_scp_of_cluster { + void __iomem *reg_base; + void __iomem *l1tcm_base; + size_t l1tcm_size; + phys_addr_t l1tcm_phys; +}; + struct mtk_scp { struct device *dev; struct rproc *rproc; struct clk *clk; - void __iomem *reg_base; void __iomem *sram_base; size_t sram_size; phys_addr_t sram_phys; - void __iomem *l1tcm_base; - size_t l1tcm_size; - phys_addr_t l1tcm_phys; =20 const struct mtk_scp_of_data *data; =20 @@ -128,6 +131,8 @@ struct mtk_scp { size_t dram_size; =20 struct rproc_subdev *rpmsg_subdev; + + struct mtk_scp_of_cluster *cluster; }; =20 /** diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 48e759c2d486..f88e60e4bc21 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -152,45 +152,45 @@ static void mt8183_scp_reset_assert(struct mtk_scp *s= cp) { u32 val; =20 - val =3D readl(scp->reg_base + MT8183_SW_RSTN); + val =3D readl(scp->cluster->reg_base + MT8183_SW_RSTN); val &=3D ~MT8183_SW_RSTN_BIT; - writel(val, scp->reg_base + MT8183_SW_RSTN); + writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); } =20 static void mt8183_scp_reset_deassert(struct mtk_scp *scp) { u32 val; =20 - val =3D readl(scp->reg_base + MT8183_SW_RSTN); + val =3D readl(scp->cluster->reg_base + MT8183_SW_RSTN); val |=3D MT8183_SW_RSTN_BIT; - writel(val, scp->reg_base + MT8183_SW_RSTN); + writel(val, scp->cluster->reg_base + MT8183_SW_RSTN); } =20 static void mt8192_scp_reset_assert(struct mtk_scp *scp) { - writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); } =20 static void mt8192_scp_reset_deassert(struct mtk_scp *scp) { - writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_CLR); } =20 static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp) { - writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); + writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_SET); } =20 static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp) { - writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); + writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_CLR); } =20 static void mt8183_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; =20 - scp_to_host =3D readl(scp->reg_base + MT8183_SCP_TO_HOST); + scp_to_host =3D readl(scp->cluster->reg_base + MT8183_SCP_TO_HOST); if (scp_to_host & MT8183_SCP_IPC_INT_BIT) scp_ipi_handler(scp); else @@ -198,14 +198,14 @@ static void mt8183_scp_irq_handler(struct mtk_scp *sc= p) =20 /* SCP won't send another interrupt until we set SCP_TO_HOST to 0. */ writel(MT8183_SCP_IPC_INT_BIT | MT8183_SCP_WDT_INT_BIT, - scp->reg_base + MT8183_SCP_TO_HOST); + scp->cluster->reg_base + MT8183_SCP_TO_HOST); } =20 static void mt8192_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; =20 - scp_to_host =3D readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); + scp_to_host =3D readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET); =20 if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { scp_ipi_handler(scp); @@ -215,10 +215,10 @@ static void mt8192_scp_irq_handler(struct mtk_scp *sc= p) * MT8192_SCP2APMCU_IPC. */ writel(MT8192_SCP_IPC_INT_BIT, - scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); + scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR); } else { scp_wdt_handler(scp, scp_to_host); - writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); + writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ); } } =20 @@ -226,12 +226,12 @@ static void mt8195_scp_c1_irq_handler(struct mtk_scp = *scp) { u32 scp_to_host; =20 - scp_to_host =3D readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); + scp_to_host =3D readl(scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_SET= ); =20 if (scp_to_host & MT8192_SCP_IPC_INT_BIT) scp_ipi_handler(scp); =20 - writel(scp_to_host, scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); + writel(scp_to_host, scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); } =20 static irqreturn_t scp_irq_handler(int irq, void *priv) @@ -363,26 +363,26 @@ static int mt8195_scp_clk_get(struct mtk_scp *scp) static int mt8183_scp_before_load(struct mtk_scp *scp) { /* Clear SCP to host interrupt */ - writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST); + writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOS= T); =20 /* Reset clocks before loading FW */ - writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL); - writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL); =20 /* Initialize TCM before loading FW. */ - writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD); - writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); =20 /* Turn on the power of SCP's SRAM before using it. */ - writel(0x0, scp->reg_base + MT8183_SCP_SRAM_PDN); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_SRAM_PDN); =20 /* * Set I-cache and D-cache size before loading SCP FW. * SCP SRAM logical address may change when cache size setting differs. */ writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB, - scp->reg_base + MT8183_SCP_CACHE_CON); - writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON); + scp->cluster->reg_base + MT8183_SCP_CACHE_CON); + writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCAC= HE_CON); =20 return 0; } @@ -408,28 +408,28 @@ static void scp_sram_power_off(void __iomem *addr, u3= 2 reserved_mask) static int mt8186_scp_before_load(struct mtk_scp *scp) { /* Clear SCP to host interrupt */ - writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST); + writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOS= T); =20 /* Reset clocks before loading FW */ - writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL); - writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL); =20 /* Turn on the power of SCP's SRAM before using it. Enable 1 block per ti= me*/ - scp_sram_power_on(scp->reg_base + MT8183_SCP_SRAM_PDN, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8183_SCP_SRAM_PDN, 0); =20 /* Initialize TCM before loading FW. */ - writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD); - writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); - writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1); - writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD); + writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD); + writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_P1); + writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_p2); =20 /* * Set I-cache and D-cache size before loading SCP FW. * SCP SRAM logical address may change when cache size setting differs. */ writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB, - scp->reg_base + MT8183_SCP_CACHE_CON); - writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON); + scp->cluster->reg_base + MT8183_SCP_CACHE_CON); + writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCAC= HE_CON); =20 return 0; } @@ -437,19 +437,19 @@ static int mt8186_scp_before_load(struct mtk_scp *scp) static int mt8192_scp_before_load(struct mtk_scp *scp) { /* clear SPM interrupt, SCP2SPM_IPC_CLR */ - writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR); + writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); =20 - writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); =20 /* enable SRAM clock */ - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0); - scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); =20 /* enable MPU for all memory regions */ - writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); + writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); =20 return 0; } @@ -457,20 +457,20 @@ static int mt8192_scp_before_load(struct mtk_scp *scp) static int mt8195_scp_before_load(struct mtk_scp *scp) { /* clear SPM interrupt, SCP2SPM_IPC_CLR */ - writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR); + writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); =20 - writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); + writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); =20 /* enable SRAM clock */ - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); - scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); =20 /* enable MPU for all memory regions */ - writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); + writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF); =20 return 0; } @@ -479,10 +479,10 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *= scp) { scp->data->scp_reset_assert(scp); =20 - scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); =20 /* enable MPU for all memory regions */ - writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); =20 return 0; } @@ -601,11 +601,11 @@ static void *mt8192_scp_da_to_va(struct mtk_scp *scp,= u64 da, size_t len) } =20 /* optional memory region */ - if (scp->l1tcm_size && - da >=3D scp->l1tcm_phys && - (da + len) <=3D scp->l1tcm_phys + scp->l1tcm_size) { - offset =3D da - scp->l1tcm_phys; - return (void __force *)scp->l1tcm_base + offset; + if (scp->cluster->l1tcm_size && + da >=3D scp->cluster->l1tcm_phys && + (da + len) <=3D scp->cluster->l1tcm_phys + scp->cluster->l1tcm_size) { + offset =3D da - scp->cluster->l1tcm_phys; + return (void __force *)scp->cluster->l1tcm_base + offset; } =20 /* optional memory region */ @@ -629,43 +629,43 @@ static void *scp_da_to_va(struct rproc *rproc, u64 da= , size_t len, bool *is_iome static void mt8183_scp_stop(struct mtk_scp *scp) { /* Disable SCP watchdog */ - writel(0, scp->reg_base + MT8183_WDT_CFG); + writel(0, scp->cluster->reg_base + MT8183_WDT_CFG); } =20 static void mt8192_scp_stop(struct mtk_scp *scp) { /* Disable SRAM clock */ - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0); - scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); =20 /* Disable SCP watchdog */ - writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); + writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG); } =20 static void mt8195_scp_stop(struct mtk_scp *scp) { /* Disable SRAM clock */ - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); - scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); =20 /* Disable SCP watchdog */ - writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); + writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG); } =20 static void mt8195_scp_c1_stop(struct mtk_scp *scp) { /* Power off CPU SRAM */ - scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); =20 /* Disable SCP watchdog */ - writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); + writel(0, scp->cluster->reg_base + MT8195_CORE1_WDT_CFG); } =20 static int scp_stop(struct rproc *rproc) @@ -859,11 +859,16 @@ static int scp_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; struct mtk_scp *scp; + struct mtk_scp_of_cluster *scp_cluster; struct rproc *rproc; struct resource *res; const char *fw_name =3D "scp.img"; int ret, i; =20 + scp_cluster =3D devm_kzalloc(dev, sizeof(*scp_cluster), GFP_KERNEL); + if (!scp_cluster) + return -ENOMEM; + ret =3D rproc_of_parse_firmware(dev, 0, &fw_name); if (ret < 0 && ret !=3D -EINVAL) return ret; @@ -876,6 +881,7 @@ static int scp_probe(struct platform_device *pdev) scp->rproc =3D rproc; scp->dev =3D dev; scp->data =3D of_device_get_match_data(dev); + scp->cluster =3D scp_cluster; platform_set_drvdata(pdev, scp); =20 res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); @@ -889,20 +895,20 @@ static int scp_probe(struct platform_device *pdev) =20 /* l1tcm is an optional memory region */ res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm"); - scp->l1tcm_base =3D devm_ioremap_resource(dev, res); - if (IS_ERR(scp->l1tcm_base)) { - ret =3D PTR_ERR(scp->l1tcm_base); + scp->cluster->l1tcm_base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(scp->cluster->l1tcm_base)) { + ret =3D PTR_ERR(scp->cluster->l1tcm_base); if (ret !=3D -EINVAL) { return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n"); } } else { - scp->l1tcm_size =3D resource_size(res); - scp->l1tcm_phys =3D res->start; + scp->cluster->l1tcm_size =3D resource_size(res); + scp->cluster->l1tcm_phys =3D res->start; } =20 - scp->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "cfg"); - if (IS_ERR(scp->reg_base)) - return dev_err_probe(dev, PTR_ERR(scp->reg_base), + scp->cluster->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "c= fg"); + if (IS_ERR(scp->cluster->reg_base)) + return dev_err_probe(dev, PTR_ERR(scp->cluster->reg_base), "Failed to parse and map cfg memory\n"); =20 ret =3D scp->data->scp_clk_get(scp); diff --git a/drivers/remoteproc/mtk_scp_ipi.c b/drivers/remoteproc/mtk_scp_= ipi.c index 9c7c17b9d181..cd0b60106ec2 100644 --- a/drivers/remoteproc/mtk_scp_ipi.c +++ b/drivers/remoteproc/mtk_scp_ipi.c @@ -177,7 +177,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf= , unsigned int len, mutex_lock(&scp->send_lock); =20 /* Wait until SCP receives the last command */ - ret =3D readl_poll_timeout_atomic(scp->reg_base + scp->data->host_to_scp_= reg, + ret =3D readl_poll_timeout_atomic(scp->cluster->reg_base + scp->data->hos= t_to_scp_reg, val, !val, 0, SCP_TIMEOUT_US); if (ret) { dev_err(scp->dev, "%s: IPI timeout!\n", __func__); @@ -192,7 +192,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf= , unsigned int len, scp->ipi_id_ack[id] =3D false; /* send the command to SCP */ writel(scp->data->host_to_scp_int_bit, - scp->reg_base + scp->data->host_to_scp_reg); + scp->cluster->reg_base + scp->data->host_to_scp_reg); =20 if (wait) { /* wait for SCP's ACK */ --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2BA6CA0FF4 for ; Fri, 1 Sep 2023 08:10:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348670AbjIAIKX (ORCPT ); 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Fri, 01 Sep 2023 16:09:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:52 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 06/14] remoteproc: mediatek: Revise SCP rproc initialization flow for multi-core SCP Date: Fri, 1 Sep 2023 16:09:27 +0800 Message-ID: <20230901080935.14571-7-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is the 2nd preliminary step for probing multi-core SCP. Initialization of configuration and L1TCM registers is extracted to only performed once on multi-core SCP. The rest of remoteproc initialization procedure is similar for both single and multi-core SCP and is applied to each core. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 63 ++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 24 deletions(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index f88e60e4bc21..7a2ba1e1e95a 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -854,21 +854,17 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *s= cp) } } =20 -static int scp_probe(struct platform_device *pdev) +static int scp_rproc_init(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; struct mtk_scp *scp; - struct mtk_scp_of_cluster *scp_cluster; struct rproc *rproc; struct resource *res; const char *fw_name =3D "scp.img"; int ret, i; =20 - scp_cluster =3D devm_kzalloc(dev, sizeof(*scp_cluster), GFP_KERNEL); - if (!scp_cluster) - return -ENOMEM; - ret =3D rproc_of_parse_firmware(dev, 0, &fw_name); if (ret < 0 && ret !=3D -EINVAL) return ret; @@ -893,24 +889,6 @@ static int scp_probe(struct platform_device *pdev) scp->sram_size =3D resource_size(res); scp->sram_phys =3D res->start; =20 - /* l1tcm is an optional memory region */ - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm"); - scp->cluster->l1tcm_base =3D devm_ioremap_resource(dev, res); - if (IS_ERR(scp->cluster->l1tcm_base)) { - ret =3D PTR_ERR(scp->cluster->l1tcm_base); - if (ret !=3D -EINVAL) { - return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n"); - } - } else { - scp->cluster->l1tcm_size =3D resource_size(res); - scp->cluster->l1tcm_phys =3D res->start; - } - - scp->cluster->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "c= fg"); - if (IS_ERR(scp->cluster->reg_base)) - return dev_err_probe(dev, PTR_ERR(scp->cluster->reg_base), - "Failed to parse and map cfg memory\n"); - ret =3D scp->data->scp_clk_get(scp); if (ret) return ret; @@ -962,6 +940,43 @@ static int scp_probe(struct platform_device *pdev) return ret; } =20 +static int scp_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_scp_of_cluster *scp_cluster; + struct resource *res; + int ret; + + scp_cluster =3D devm_kzalloc(dev, sizeof(*scp_cluster), GFP_KERNEL); + if (!scp_cluster) + return -ENOMEM; + + scp_cluster->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "cf= g"); + if (IS_ERR(scp_cluster->reg_base)) + return dev_err_probe(dev, PTR_ERR(scp_cluster->reg_base), + "Failed to parse and map cfg memory\n"); + + /* l1tcm is an optional memory region */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm"); + scp_cluster->l1tcm_base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(scp_cluster->l1tcm_base)) { + ret =3D PTR_ERR(scp_cluster->l1tcm_base); + if (ret !=3D -EINVAL) + return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n"); + + scp_cluster->l1tcm_base =3D NULL; + } else { + scp_cluster->l1tcm_size =3D resource_size(res); + scp_cluster->l1tcm_phys =3D res->start; + } + + ret =3D scp_rproc_init(pdev, scp_cluster); + if (ret) + return ret; + + return 0; +} + static void scp_remove(struct platform_device *pdev) { struct mtk_scp *scp =3D platform_get_drvdata(pdev); --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F189BCA0FE9 for ; Fri, 1 Sep 2023 08:10:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348650AbjIAIKZ (ORCPT ); Fri, 1 Sep 2023 04:10:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348613AbjIAIKN (ORCPT ); Fri, 1 Sep 2023 04:10:13 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED2931703; 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Fri, 01 Sep 2023 16:09:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:52 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 07/14] remoteproc: mediatek: Probe SCP cluster on single-core SCP Date: Fri, 1 Sep 2023 16:09:28 +0800 Message-ID: <20230901080935.14571-8-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is the 3rd preliminary step for probing multi-core SCP. Rewrite the probing flow of single-core SCP to adapt with the 'cluster' concept needed by the multi-core SCP. The SCP core object(s) is maintained at the cluster list. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 2 + drivers/remoteproc/mtk_scp.c | 86 +++++++++++++++++++++++---------- 2 files changed, 63 insertions(+), 25 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index b04d71277c1f..1438159ae736 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -105,6 +105,7 @@ struct mtk_scp_of_cluster { void __iomem *l1tcm_base; size_t l1tcm_size; phys_addr_t l1tcm_phys; + struct list_head mtk_scp_list; }; =20 struct mtk_scp { @@ -132,6 +133,7 @@ struct mtk_scp { =20 struct rproc_subdev *rpmsg_subdev; =20 + struct list_head elem; struct mtk_scp_of_cluster *cluster; }; =20 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 7a2ba1e1e95a..d67dcabdab9e 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -854,8 +854,8 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } } =20 -static int scp_rproc_init(struct platform_device *pdev, - struct mtk_scp_of_cluster *scp_cluster) +static struct mtk_scp *scp_rproc_init(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; @@ -867,11 +867,13 @@ static int scp_rproc_init(struct platform_device *pde= v, =20 ret =3D rproc_of_parse_firmware(dev, 0, &fw_name); if (ret < 0 && ret !=3D -EINVAL) - return ret; + return ERR_PTR(ret); =20 rproc =3D devm_rproc_alloc(dev, np->name, &scp_ops, fw_name, sizeof(*scp)= ); - if (!rproc) - return dev_err_probe(dev, -ENOMEM, "unable to allocate remoteproc\n"); + if (!rproc) { + dev_err(dev, "unable to allocate remoteproc\n"); + return ERR_PTR(-ENOMEM); + } =20 scp =3D rproc->priv; scp->rproc =3D rproc; @@ -882,20 +884,21 @@ static int scp_rproc_init(struct platform_device *pde= v, =20 res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); scp->sram_base =3D devm_ioremap_resource(dev, res); - if (IS_ERR(scp->sram_base)) - return dev_err_probe(dev, PTR_ERR(scp->sram_base), - "Failed to parse and map sram memory\n"); + if (IS_ERR(scp->sram_base)) { + dev_err(dev, "Failed to parse and map sram memory\n"); + return ERR_CAST(scp->sram_base); + } =20 scp->sram_size =3D resource_size(res); scp->sram_phys =3D res->start; =20 ret =3D scp->data->scp_clk_get(scp); if (ret) - return ret; + return ERR_PTR(ret); =20 ret =3D scp_map_memory_region(scp); if (ret) - return ret; + return ERR_PTR(ret); =20 mutex_init(&scp->send_lock); for (i =3D 0; i < SCP_IPI_MAX; i++) @@ -922,11 +925,7 @@ static int scp_rproc_init(struct platform_device *pdev, goto remove_subdev; } =20 - ret =3D rproc_add(rproc); - if (ret) - goto remove_subdev; - - return 0; + return scp; =20 remove_subdev: scp_remove_rpmsg_subdev(scp); @@ -937,7 +936,43 @@ static int scp_rproc_init(struct platform_device *pdev, mutex_destroy(&scp->ipi_desc[i].lock); mutex_destroy(&scp->send_lock); =20 - return ret; + return ERR_PTR(ret); +} + +static void scp_free(struct mtk_scp *scp) +{ + int i; + + scp_remove_rpmsg_subdev(scp); + scp_ipi_unregister(scp, SCP_IPI_INIT); + scp_unmap_memory_region(scp); + for (i =3D 0; i < SCP_IPI_MAX; i++) + mutex_destroy(&scp->ipi_desc[i].lock); + mutex_destroy(&scp->send_lock); +} + +static int scp_cluster_init(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) +{ + struct device *dev =3D &pdev->dev; + struct list_head *scp_list =3D &scp_cluster->mtk_scp_list; + struct mtk_scp *scp; + int ret; + + scp =3D scp_rproc_init(pdev, scp_cluster); + if (IS_ERR(scp)) + return PTR_ERR(scp); + + ret =3D rproc_add(scp->rproc); + if (ret) { + dev_err(dev, "Failed to add rproc\n"); + scp_free(scp); + return ret; + } + + list_add_tail(&scp->elem, scp_list); + + return 0; } =20 static int scp_probe(struct platform_device *pdev) @@ -970,7 +1005,9 @@ static int scp_probe(struct platform_device *pdev) scp_cluster->l1tcm_phys =3D res->start; } =20 - ret =3D scp_rproc_init(pdev, scp_cluster); + INIT_LIST_HEAD(&scp_cluster->mtk_scp_list); + + ret =3D scp_cluster_init(pdev, scp_cluster); if (ret) return ret; =20 @@ -980,15 +1017,14 @@ static int scp_probe(struct platform_device *pdev) static void scp_remove(struct platform_device *pdev) { struct mtk_scp *scp =3D platform_get_drvdata(pdev); - int i; + struct mtk_scp_of_cluster *scp_cluster =3D scp->cluster; + struct mtk_scp *temp; =20 - rproc_del(scp->rproc); - scp_remove_rpmsg_subdev(scp); - scp_ipi_unregister(scp, SCP_IPI_INIT); - scp_unmap_memory_region(scp); - for (i =3D 0; i < SCP_IPI_MAX; i++) - mutex_destroy(&scp->ipi_desc[i].lock); - mutex_destroy(&scp->send_lock); + list_for_each_entry_safe_reverse(scp, temp, &scp_cluster->mtk_scp_list, e= lem) { + list_del(&scp->elem); + rproc_del(scp->rproc); + scp_free(scp); + } } =20 static const struct mtk_scp_of_data mt8183_of_data =3D { --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B08CA0FE6 for ; Fri, 1 Sep 2023 08:10:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242348AbjIAIKg (ORCPT ); Fri, 1 Sep 2023 04:10:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348626AbjIAIKP (ORCPT ); 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Fri, 01 Sep 2023 16:09:54 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:52 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 08/14] remoteproc: mediatek: Probe SCP cluster on multi-core SCP Date: Fri, 1 Sep 2023 16:09:29 +0800 Message-ID: <20230901080935.14571-9-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The difference of single-core SCP and multi-core SCP device tree is the presence of child device nodes described SCP cores. The SCP driver populates the platform device and checks the child nodes to identify whether it's a single-core SCP or a multi-core SCP. Add the remoteproc instances of multi-core SCP to the SCP cluster list. When the SCP driver is removed, it cleanup resources by walking through the cluster list. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 123 +++++++++++++++++++++++++++++++++-- 1 file changed, 118 insertions(+), 5 deletions(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d67dcabdab9e..685e2c2bb6ee 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -855,7 +855,8 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } =20 static struct mtk_scp *scp_rproc_init(struct platform_device *pdev, - struct mtk_scp_of_cluster *scp_cluster) + struct mtk_scp_of_cluster *scp_cluster, + const struct mtk_scp_of_data *of_data) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; @@ -878,7 +879,7 @@ static struct mtk_scp *scp_rproc_init(struct platform_d= evice *pdev, scp =3D rproc->priv; scp->rproc =3D rproc; scp->dev =3D dev; - scp->data =3D of_device_get_match_data(dev); + scp->data =3D of_data; scp->cluster =3D scp_cluster; platform_set_drvdata(pdev, scp); =20 @@ -951,15 +952,15 @@ static void scp_free(struct mtk_scp *scp) mutex_destroy(&scp->send_lock); } =20 -static int scp_cluster_init(struct platform_device *pdev, - struct mtk_scp_of_cluster *scp_cluster) +static int scp_add_single_core(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) { struct device *dev =3D &pdev->dev; struct list_head *scp_list =3D &scp_cluster->mtk_scp_list; struct mtk_scp *scp; int ret; =20 - scp =3D scp_rproc_init(pdev, scp_cluster); + scp =3D scp_rproc_init(pdev, scp_cluster, of_device_get_match_data(dev)); if (IS_ERR(scp)) return PTR_ERR(scp); =20 @@ -975,6 +976,107 @@ static int scp_cluster_init(struct platform_device *p= dev, return 0; } =20 +static int scp_add_multi_core(struct platform_device *pdev, + struct mtk_scp_of_cluster *scp_cluster) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev_of_node(dev); + struct platform_device *cpdev; + struct device_node *child; + struct list_head *scp_list =3D &scp_cluster->mtk_scp_list; + const struct mtk_scp_of_data **cluster_of_data; + struct mtk_scp *scp, *temp; + int core_id =3D 0; + int ret; + + cluster_of_data =3D (const struct mtk_scp_of_data **)of_device_get_match_= data(dev); + + for_each_available_child_of_node(np, child) { + if (!cluster_of_data[core_id]) { + ret =3D -EINVAL; + dev_err(dev, "Not support core %d\n", core_id); + of_node_put(child); + goto init_fail; + } + + cpdev =3D of_find_device_by_node(child); + if (!cpdev) { + ret =3D -ENODEV; + dev_err(dev, "Not found platform device for core %d\n", core_id); + of_node_put(child); + goto init_fail; + } + + scp =3D scp_rproc_init(cpdev, scp_cluster, cluster_of_data[core_id]); + put_device(&cpdev->dev); + if (IS_ERR(scp)) { + ret =3D PTR_ERR(scp); + dev_err(dev, "Failed to initialize core %d rproc\n", core_id); + of_node_put(child); + goto init_fail; + } + + ret =3D rproc_add(scp->rproc); + if (ret) { + dev_err(dev, "Failed to add rproc of core %d\n", core_id); + of_node_put(child); + scp_free(scp); + goto init_fail; + } + + list_add_tail(&scp->elem, scp_list); + core_id++; + } + + /* Here we are setting the platform device for @pdev to the last @scp tha= t was + * created, which is needed because (1) scp_rproc_init() is calling + * platform_set_drvdata() on the child platform devices and (2) we need a= handle to + * the cluster list in scp_remove(). + */ + platform_set_drvdata(pdev, scp); + + return 0; + +init_fail: + list_for_each_entry_safe_reverse(scp, temp, scp_list, elem) { + list_del(&scp->elem); + rproc_del(scp->rproc); + scp_free(scp); + } + + return ret; +} + +static int scp_is_single_core(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev_of_node(dev); + struct device_node *child; + + child =3D of_get_next_available_child(np, NULL); + if (!child) + return dev_err_probe(dev, -ENODEV, "No child node\n"); + + of_node_put(child); + return of_node_name_eq(child, "cros-ec-rpmsg"); +} + +static int scp_cluster_init(struct platform_device *pdev, struct mtk_scp_o= f_cluster *scp_cluster) +{ + int ret; + + ret =3D scp_is_single_core(pdev); + if (ret < 0) + return ret; + + if (ret) + ret =3D scp_add_single_core(pdev, scp_cluster); + else + ret =3D scp_add_multi_core(pdev, scp_cluster); + + return ret; +} + static int scp_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1007,6 +1109,10 @@ static int scp_probe(struct platform_device *pdev) =20 INIT_LIST_HEAD(&scp_cluster->mtk_scp_list); =20 + ret =3D devm_of_platform_populate(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to populate platform devices\n"); + ret =3D scp_cluster_init(pdev, scp_cluster); if (ret) return ret; @@ -1101,12 +1207,19 @@ static const struct mtk_scp_of_data mt8195_of_data_= c1 =3D { .host_to_scp_int_bit =3D MT8195_CORE1_HOST_IPC_INT_BIT, }; =20 +static const struct mtk_scp_of_data *mt8195_of_data_cores[] =3D { + &mt8195_of_data, + &mt8195_of_data_c1, + NULL +}; + static const struct of_device_id mtk_scp_of_match[] =3D { { .compatible =3D "mediatek,mt8183-scp", .data =3D &mt8183_of_data }, { .compatible =3D "mediatek,mt8186-scp", .data =3D &mt8186_of_data }, { .compatible =3D "mediatek,mt8188-scp", .data =3D &mt8188_of_data }, { .compatible =3D "mediatek,mt8192-scp", .data =3D &mt8192_of_data }, { .compatible =3D "mediatek,mt8195-scp", .data =3D &mt8195_of_data }, + { .compatible =3D "mediatek,mt8195-scp-dual", .data =3D &mt8195_of_data_c= ores }, {}, }; MODULE_DEVICE_TABLE(of, mtk_scp_of_match); --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98C2ECA0FE6 for ; Fri, 1 Sep 2023 08:10:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242900AbjIAIKc (ORCPT ); Fri, 1 Sep 2023 04:10:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348615AbjIAIKO (ORCPT ); Fri, 1 Sep 2023 04:10:14 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3C0E1708; Fri, 1 Sep 2023 01:10:03 -0700 (PDT) X-UUID: eeb03428489e11eea33bb35ae8d461a2-20230901 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Fri, 01 Sep 2023 16:09:54 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:52 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 09/14] remoteproc: mediatek: Remove dependency of MT8195 SCP L2TCM power control on dual-core SCP Date: Fri, 1 Sep 2023 16:09:30 +0800 Message-ID: <20230901080935.14571-10-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previously, SCP core 0 controlled the power of L2TCM and dictated that SCP core 1 could only boot after SCP core 0. To address this constraint, extracted the power control flow of L2TCM and made it shared between both cores, enabling support for arbitrary boot order. The flow for controlling L2TCM power has been incorporated into the mt8195_scp_before_load() and mt8195_scp_stop() APIs, which are respectively invoked during the rproc->ops->start() and rproc->ops->stop() operations. These APIs effectively serve the same purpose as the rproc prepare()/unprepare() APIs." Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 3 ++ drivers/remoteproc/mtk_scp.c | 71 ++++++++++++++++++++++++++------- 2 files changed, 59 insertions(+), 15 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index 1438159ae736..fea05bbba9aa 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -106,6 +106,9 @@ struct mtk_scp_of_cluster { size_t l1tcm_size; phys_addr_t l1tcm_phys; struct list_head mtk_scp_list; + /* Prevent concurrent operations of this structure and L2TCM power contro= l. */ + struct mutex cluster_lock; + u32 l2tcm_refcnt; }; =20 struct mtk_scp { diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 685e2c2bb6ee..59d9182a8d1e 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -454,19 +454,37 @@ static int mt8192_scp_before_load(struct mtk_scp *scp) return 0; } =20 -static int mt8195_scp_before_load(struct mtk_scp *scp) +static int mt8195_scp_l2tcm_on(struct mtk_scp *scp) { - /* clear SPM interrupt, SCP2SPM_IPC_CLR */ - writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); + struct mtk_scp_of_cluster *scp_cluster =3D scp->cluster; + + mutex_lock(&scp_cluster->cluster_lock); + + if (scp_cluster->l2tcm_refcnt =3D=3D 0) { + /* clear SPM interrupt, SCP2SPM_IPC_CLR */ + writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR); + + /* Power on L2TCM */ + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, + MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + } + + scp_cluster->l2tcm_refcnt +=3D 1; =20 + mutex_unlock(&scp_cluster->cluster_lock); + + return 0; +} + +static int mt8195_scp_before_load(struct mtk_scp *scp) +{ writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET); =20 - /* enable SRAM clock */ - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, - MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + mt8195_scp_l2tcm_on(scp); + scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); =20 /* enable MPU for all memory regions */ @@ -479,6 +497,8 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *sc= p) { scp->data->scp_reset_assert(scp); =20 + mt8195_scp_l2tcm_on(scp); + scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); =20 /* enable MPU for all memory regions */ @@ -645,14 +665,31 @@ static void mt8192_scp_stop(struct mtk_scp *scp) writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG); } =20 +static void mt8195_scp_l2tcm_off(struct mtk_scp *scp) +{ + struct mtk_scp_of_cluster *scp_cluster =3D scp->cluster; + + mutex_lock(&scp_cluster->cluster_lock); + + if (scp_cluster->l2tcm_refcnt > 0) + scp_cluster->l2tcm_refcnt -=3D 1; + + if (scp_cluster->l2tcm_refcnt =3D=3D 0) { + /* Power off L2TCM */ + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); + scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, + MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + } + + mutex_unlock(&scp_cluster->cluster_lock); +} + static void mt8195_scp_stop(struct mtk_scp *scp) { - /* Disable SRAM clock */ - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0); - scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, - MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS); + mt8195_scp_l2tcm_off(scp); + scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0); =20 /* Disable SCP watchdog */ @@ -661,6 +698,8 @@ static void mt8195_scp_stop(struct mtk_scp *scp) =20 static void mt8195_scp_c1_stop(struct mtk_scp *scp) { + mt8195_scp_l2tcm_off(scp); + /* Power off CPU SRAM */ scp_sram_power_off(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0); =20 @@ -1108,6 +1147,7 @@ static int scp_probe(struct platform_device *pdev) } =20 INIT_LIST_HEAD(&scp_cluster->mtk_scp_list); + mutex_init(&scp_cluster->cluster_lock); =20 ret =3D devm_of_platform_populate(dev); if (ret) @@ -1131,6 +1171,7 @@ static void scp_remove(struct platform_device *pdev) rproc_del(scp->rproc); scp_free(scp); } + mutex_destroy(&scp_cluster->cluster_lock); } =20 static const struct mtk_scp_of_data mt8183_of_data =3D { --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 170F0CA0FE1 for ; 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charset="utf-8" Because MT8195 SCP core 0 and core 1 both boot from head of SRAM and have the same viewpoint of SRAM, SCP has a "core 1 SRAM offset" configuration to control the access destination of SCP core 1 to boot core 1 from different SRAM location. The "core 1 SRAM offset" configuration is composed by a range and an offset. It works like a simple memory mapped mechanism. When SCP core 1 accesses a SRAM address located in the range, the SCP bus adds the configured offset to the address to shift the physical destination address on SCP SRAM. This shifting is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 7 +++++++ drivers/remoteproc/mtk_scp.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index fea05bbba9aa..3d6b53b9f374 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -65,6 +65,13 @@ #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 #define MT8195_CORE1_WDT_CFG 0x20034 =20 +#define MT8195_SEC_CTRL 0x85000 +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 +#define MT8195_L2TCM_OFFSET 0x850d0 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288 =20 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 59d9182a8d1e..db5b15f5f8c1 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -495,6 +495,10 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) =20 static int mt8195_scp_c1_before_load(struct mtk_scp *scp) { + u32 sec_ctrl; + struct mtk_scp *scp_c0; + struct mtk_scp_of_cluster *scp_cluster =3D scp->cluster; + scp->data->scp_reset_assert(scp); =20 mt8195_scp_l2tcm_on(scp); @@ -504,6 +508,30 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *s= cp) /* enable MPU for all memory regions */ writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); =20 + /* + * The L2TCM_OFFSET_RANGE and L2TCM_OFFSET shift the destination address + * on SRAM when SCP core 1 accesses SRAM. + * + * This configuration solves booting the SCP core 0 and core 1 from + * different SRAM address because core 0 and core 1 both boot from + * the head of SRAM by default. this must be configured before boot SCP c= ore 1. + * + * The value of L2TCM_OFFSET_RANGE is from the viewpoint of SCP core 1. + * When SCP core 1 issues address within the range (L2TCM_OFFSET_RANGE), + * the address will be added with a fixed offset (L2TCM_OFFSET) on the bu= s. + * The shift action is tranparent to software. + */ + writel(0, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW); + writel(scp->sram_size, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE= _0_HIGH); + + scp_c0 =3D list_first_entry(&scp_cluster->mtk_scp_list, struct mtk_scp, e= lem); + writel(scp->sram_phys - scp_c0->sram_phys, scp->cluster->reg_base + MT819= 5_L2TCM_OFFSET); + + /* enable SRAM offset when fetching instruction and data */ + sec_ctrl =3D readl(scp->cluster->reg_base + MT8195_SEC_CTRL); + sec_ctrl |=3D MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D; + writel(sec_ctrl, scp->cluster->reg_base + MT8195_SEC_CTRL); + return 0; } =20 --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AFCACA0FE8 for ; Fri, 1 Sep 2023 08:10:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348676AbjIAIKb (ORCPT ); Fri, 1 Sep 2023 04:10:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348619AbjIAIKP (ORCPT ); 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Fri, 01 Sep 2023 16:09:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:53 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Tinghan Shen" CC: , , , , , Subject: [PATCH v17 11/14] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout Date: Fri, 1 Sep 2023 16:09:32 +0800 Message-ID: <20230901080935.14571-12-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 5 +++++ drivers/remoteproc/mtk_scp.c | 25 ++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index 3d6b53b9f374..6d7736a031f7 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -55,6 +55,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 =20 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) =20 #define MT8195_CPU1_SRAM_PD 0x1084 @@ -63,6 +67,7 @@ #define MT8195_CORE1_SW_RSTN_CLR 0x20000 #define MT8195_CORE1_SW_RSTN_SET 0x20004 #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 #define MT8195_CORE1_WDT_CFG 0x20034 =20 #define MT8195_SEC_CTRL 0x85000 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index db5b15f5f8c1..49b2ca2b30b3 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -222,6 +222,29 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } =20 +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host =3D readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + } else { + u32 reason =3D readl(scp->cluster->reg_base + MT8195_SYS_STATUS); + + if (reason & MT8195_CORE0_WDT) + writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ); + + if (reason & MT8195_CORE1_WDT) + writel(1, scp->cluster->reg_base + MT8195_CORE1_WDT_IRQ); + + scp_wdt_handler(scp, reason); + } + + writel(scp_to_host, scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR); +} + static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -1255,7 +1278,7 @@ static const struct mtk_scp_of_data mt8192_of_data = =3D { static const struct mtk_scp_of_data mt8195_of_data =3D { .scp_clk_get =3D mt8195_scp_clk_get, .scp_before_load =3D mt8195_scp_before_load, - .scp_irq_handler =3D mt8192_scp_irq_handler, + .scp_irq_handler =3D mt8195_scp_irq_handler, .scp_reset_assert =3D mt8192_scp_reset_assert, .scp_reset_deassert =3D mt8192_scp_reset_deassert, .scp_stop =3D mt8195_scp_stop, --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B13ECA0FEB for ; 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Fri, 01 Sep 2023 16:09:53 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:53 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 12/14] remoteproc: mediatek: Report watchdog crash to all cores Date: Fri, 1 Sep 2023 16:09:33 +0800 Message-ID: <20230901080935.14571-13-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To ensure consistent behavior, the watchdog timeout handling of the multi-core SCP should reset the whole SCP sub-system when watchdog timeout. Triggering the rproc recovery flow on all instances will ensure proper recovery of the SCP sub-system. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 49b2ca2b30b3..37ee5e6286ee 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -68,8 +68,14 @@ EXPORT_SYMBOL_GPL(scp_put); =20 static void scp_wdt_handler(struct mtk_scp *scp, u32 scp_to_host) { + struct mtk_scp_of_cluster *scp_cluster =3D scp->cluster; + struct mtk_scp *scp_node; + dev_err(scp->dev, "SCP watchdog timeout! 0x%x", scp_to_host); - rproc_report_crash(scp->rproc, RPROC_WATCHDOG); + + /* report watchdog timeout to all cores */ + list_for_each_entry(scp_node, &scp_cluster->mtk_scp_list, elem) + rproc_report_crash(scp_node->rproc, RPROC_WATCHDOG); } =20 static void scp_init_ipi_handler(void *data, unsigned int len, void *priv) --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F091CCA0FEA for ; Fri, 1 Sep 2023 08:10:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348679AbjIAIK2 (ORCPT ); Fri, 1 Sep 2023 04:10:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348598AbjIAIKM (ORCPT ); Fri, 1 Sep 2023 04:10:12 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A87710FF; Fri, 1 Sep 2023 01:10:01 -0700 (PDT) X-UUID: ef0b2f22489e11eea33bb35ae8d461a2-20230901 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BIjIqffxT1gXbrhCK796RooRo5ORoQHBzqsXFq8mm8Y=; b=EynN6e0F6q/lO5uiu4EWd532qj7+rX0WB7oVhdS59FZXdqSVBySD7Fdw0YSynMMWIKt6sgozdSAU9KpXPWDUeQRKPaoEn6PfQGvMOmRDGOr0c2Uz8JKpxQPiL6NdJosDqp0lW+Z0T1VJ1+L3zaMT87h26yWykwaV80FLGkRVUxk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:fe8c77d8-5852-421e-90cb-9cb51d3a1079,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:236433ef-9a6e-4c39-b73e-f2bc08ca3dc5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ef0b2f22489e11eea33bb35ae8d461a2-20230901 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1313777529; Fri, 01 Sep 2023 16:09:54 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:53 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 13/14] remoteproc: mediatek: Refine ipi handler error message Date: Fri, 1 Sep 2023 16:09:34 +0800 Message-ID: <20230901080935.14571-14-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The error message doesn't accurately reflect the cause of the error. The error is due to a handler not being found, not an invalid IPI ID. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 37ee5e6286ee..e10cc2d5ae7c 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -112,7 +112,7 @@ static void scp_ipi_handler(struct mtk_scp *scp) scp_ipi_lock(scp, id); handler =3D ipi_desc[id].handler; if (!handler) { - dev_err(scp->dev, "No such ipi id =3D %d\n", id); + dev_err(scp->dev, "No handler for ipi id =3D %d\n", id); scp_ipi_unlock(scp, id); return; } --=20 2.18.0 From nobody Thu Nov 14 06:31:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF04CCA0FEA for ; Fri, 1 Sep 2023 08:10:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348680AbjIAIKj (ORCPT ); Fri, 1 Sep 2023 04:10:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348624AbjIAIKP (ORCPT ); Fri, 1 Sep 2023 04:10:15 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F74510E6; Fri, 1 Sep 2023 01:10:04 -0700 (PDT) X-UUID: ef33699c489e11ee8051498923ad61e6-20230901 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EgTVB8/wFgscxLDYs3qg9WMPyo6Fp8L2xH8FV1ZxS8Y=; b=BFa6IlKmqPaBcUvbnbfeCdEHyZ0wmr0hedY/ZQhBdH555Lyj79Ao5LDdBu3oQykErRhy+Iag+LuzJOTB/fdlvyWlhUvBVFOH6cEPf160Num7uF5kcyizPAOoATwrko+A5JrezY+1rEg1zyIX8RsnxIvTm3CeJaFbSCuWBnezarA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:40e979a9-2786-4c55-8d18-e48d1452e02a,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:d69787c2-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ef33699c489e11ee8051498923ad61e6-20230901 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1777927356; Fri, 01 Sep 2023 16:09:55 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 1 Sep 2023 16:09:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 1 Sep 2023 16:09:53 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v17 14/14] arm64: dts: mediatek: mt8195: Add SCP 2nd core Date: Fri, 1 Sep 2023 16:09:35 +0800 Message-ID: <20230901080935.14571-15-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230901080935.14571-1-tinghan.shen@mediatek.com> References: <20230901080935.14571-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rewrite the MT8195 SCP device node as a cluster and add the SCP 2nd core in it. Since the SCP device node is changed to multi-core structure, enable SCP cluster to enable probing SCP core 0. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 6 +++- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 34 ++++++++++++++----- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 37a3e9de90ff..4584077d3a4c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -991,7 +991,11 @@ interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; =20 -&scp { +&scp_cluster { + status =3D "okay"; +}; + +&scp_c0 { status =3D "okay"; =20 firmware-name =3D "mediatek/mt8195/scp.img"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 48b72b3645e1..7809118f74fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -922,14 +922,30 @@ clocks =3D <&infracfg_ao CLK_INFRA_AO_GCE2>; }; =20 - scp: scp@10500000 { - compatible =3D "mediatek,mt8195-scp"; - reg =3D <0 0x10500000 0 0x100000>, - <0 0x10720000 0 0xe0000>, - <0 0x10700000 0 0x8000>; - reg-names =3D "sram", "cfg", "l1tcm"; - interrupts =3D ; + scp_cluster: scp@10500000 { + compatible =3D "mediatek,mt8195-scp-dual"; + reg =3D <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>; + reg-names =3D "cfg", "l1tcm"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0x10500000 0x100000>; status =3D "disabled"; + + scp_c0: scp@0 { + compatible =3D "mediatek,scp-core"; + reg =3D <0x0 0xa0000>; + reg-names =3D "sram"; + interrupts =3D ; + status =3D "disabled"; + }; + + scp_c1: scp@a0000 { + compatible =3D "mediatek,scp-core"; + reg =3D <0xa0000 0x20000>; + reg-names =3D "sram"; + interrupts =3D ; + status =3D "disabled"; + }; }; =20 scp_adsp: clock-controller@10720000 { @@ -2374,7 +2390,7 @@ =20 video-codec@18000000 { compatible =3D "mediatek,mt8195-vcodec-dec"; - mediatek,scp =3D <&scp>; + mediatek,scp =3D <&scp_c0>; iommus =3D <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; #address-cells =3D <2>; #size-cells =3D <2>; @@ -2540,7 +2556,7 @@ <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; interrupts =3D ; - mediatek,scp =3D <&scp>; + mediatek,scp =3D <&scp_c0>; clocks =3D <&vencsys CLK_VENC_VENC>; clock-names =3D "venc_sel"; assigned-clocks =3D <&topckgen CLK_TOP_VENC>; --=20 2.18.0