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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000989E5.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6745.16 via Frontend Transport; Thu, 31 Aug 2023 15:21:52 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 31 Aug 2023 10:21:51 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v10 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state Date: Thu, 31 Aug 2023 10:20:21 -0500 Message-ID: <20230831152031.184295-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230831152031.184295-1-terry.bowman@amd.com> References: <20230831152031.184295-1-terry.bowman@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E5:EE_|DM4PR12MB6109:EE_ X-MS-Office365-Filtering-Correlation-Id: 6b0fbafb-4fd8-422b-705a-08dbaa36011b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2023 15:21:52.5026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b0fbafb-4fd8-422b-705a-08dbaa36011b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6109 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Robert Richter The Component Register base address @component_reg_phys is no longer used after the rework of the Component Register setup which now uses struct member @comp_map instead. Remove the base address. Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang --- drivers/cxl/cxlmem.h | 2 -- drivers/cxl/mem.c | 4 ++-- drivers/cxl/pci.c | 3 --- tools/testing/cxl/test/mem.c | 1 - 4 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 607ee34b0ce7..fdfa6e5dd739 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -390,7 +390,6 @@ enum cxl_devtype { * @dpa_res: Overall DPA resource tree for the device * @pmem_res: Active Persistent memory capacity configuration * @ram_res: Active Volatile memory capacity configuration - * @component_reg_phys: register base of component registers * @serial: PCIe Device Serial Number * @type: Generic Memory Class device or Vendor Specific Memory device */ @@ -405,7 +404,6 @@ struct cxl_dev_state { struct resource dpa_res; struct resource pmem_res; struct resource ram_res; - resource_size_t component_reg_phys; u64 serial; enum cxl_devtype type; }; diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 317c7548e4e9..3af3218ebe0e 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, str= uct cxl_memdev *cxlmd, struct cxl_dport *parent_dport) { struct cxl_port *parent_port =3D parent_dport->port; - struct cxl_dev_state *cxlds =3D cxlmd->cxlds; struct cxl_port *endpoint, *iter, *down; int rc; =20 @@ -65,8 +64,9 @@ static int devm_cxl_add_endpoint(struct device *host, str= uct cxl_memdev *cxlmd, ep->next =3D down; } =20 + /* The Endpoint's component regs are located in cxlds. */ endpoint =3D devm_cxl_add_port(host, &cxlmd->dev, - cxlds->component_reg_phys, + CXL_RESOURCE_NONE, parent_dport); if (IS_ERR(endpoint)) return PTR_ERR(endpoint); diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index f8ad601b314e..b71f1c7d16ce 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -835,7 +835,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) * If the component registers can't be found, the cxl_pci driver may * still be useful for management functions so don't return an error. */ - cxlds->component_reg_phys =3D CXL_RESOURCE_NONE; rc =3D cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &cxlds->comp_map); if (rc) @@ -843,8 +842,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) else if (!cxlds->comp_map.component_map.ras.valid) dev_dbg(&pdev->dev, "RAS registers not found\n"); =20 - cxlds->component_reg_phys =3D cxlds->comp_map.resource; - rc =3D cxl_map_component_regs(&cxlds->comp_map, cxlds->dev, &cxlds->regs.component, BIT(CXL_CM_CAP_CAP_ID_RAS)); diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index 464fc39ed277..aa44d111fd28 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -1423,7 +1423,6 @@ static int cxl_mock_mem_probe(struct platform_device = *pdev) cxlds->serial =3D pdev->id; if (is_rcd(pdev)) { cxlds->rcd =3D true; - cxlds->component_reg_phys =3D CXL_RESOURCE_NONE; } =20 rc =3D cxl_enumerate_cmds(mds); --=20 2.34.1