From nobody Fri Dec 19 02:49:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23E2FC83F15 for ; Wed, 30 Aug 2023 19:54:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232824AbjH3Tyt (ORCPT ); Wed, 30 Aug 2023 15:54:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241094AbjH3Ty1 (ORCPT ); Wed, 30 Aug 2023 15:54:27 -0400 Received: from mail-qt1-x82d.google.com (mail-qt1-x82d.google.com [IPv6:2607:f8b0:4864:20::82d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 279876A4C for ; Wed, 30 Aug 2023 12:23:13 -0700 (PDT) Received: by mail-qt1-x82d.google.com with SMTP id d75a77b69052e-4107e6fb0e8so281451cf.3 for ; Wed, 30 Aug 2023 12:23:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1693423297; x=1694028097; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yfL7hyBseirw2ULKrzVmWf2hUa/6+UsGULqRK6gzzdQ=; b=Zm+uAGzPvbJsEEp700xFergIXBX4V6oBP94hDbrVJma8sHqtVujJRdmr7eujAmlV8d zeu4sOHErQXpdNNCizii1TboCHnTcesPNP6jFxeFvykF3ynHOwoBWd/1N9ShnWC0m5IZ gsC+fzfRjz4TYhWgbniPQ32tgngiel/xVZ5HQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693423297; x=1694028097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yfL7hyBseirw2ULKrzVmWf2hUa/6+UsGULqRK6gzzdQ=; b=f7Q9CxnKjKzTHmbAVPh2qodEDgqJAl4YMZKX8+skeGBrfwNAogU8C+sAe7msM2BJHy U53VQbcOtQ2oK4FP3mhS425L3w22NExd7NEa5GlUh8UDzdnwsXya6dlAm9QRMscllzra XHXo7qx8c+OARTipNqBhR1BBBRz1v90y7HAX0q9fU1cMLq5xI60Rrwjb1nNdA/ZPbJ8g TDjkvZvqSOMY4/3ieYYzIwGyewjLIuib+p6A72Rj5mafRcv7iXDA7vCdYUnfsQyBiJx9 s1v+p0eu1x1m3NHqEp1eiiPnkVbXF6xenl0mBGh0UxfAoXS0xcWrxPyK18z/3oxDdo3a llGA== X-Gm-Message-State: AOJu0YwY/UrouDWvUNcFpJ/4sZtxIgBCP27YXfxusNlo9EWJutpYnVv/ u4XrJVvvHblkgCY/MVX3a9zXphG5iPzGdowv8uG39+pI X-Google-Smtp-Source: AGHT+IGsRVBhxDwcrTroEG3U48LgMw7Y7iXGf6tvH99XoYoezCk7L0nZpJx4PQuaXGFWu2v93kvrxQ== X-Received: by 2002:a05:6a21:35c8:b0:14d:8dbe:1960 with SMTP id ba8-20020a056a2135c800b0014d8dbe1960mr2942041pzc.55.1693422817689; Wed, 30 Aug 2023 12:13:37 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:e315:dec6:467c:83c5]) by smtp.gmail.com with ESMTPSA id c15-20020a170902d48f00b001bbdf32f011sm11338928plg.269.2023.08.30.12.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 12:13:37 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, Masayoshi Mizuma , "Rafael J . Wysocki" , Chen-Yu Tsai , Lecopzer Chen , Tomohiro Misono , Stephane Eranian , kgdb-bugreport@lists.sourceforge.net, Peter Zijlstra , Thomas Gleixner , Stephen Boyd , ito-yuichi@fujitsu.com, linux-perf-users@vger.kernel.org, Ard Biesheuvel , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v12 1/7] irqchip/gic-v3: Enable support for SGIs to act as NMIs Date: Wed, 30 Aug 2023 12:11:22 -0700 Message-ID: <20230830121115.v12.1.I1223c11c88937bd0cbd9b086d4ef216985797302@changeid> X-Mailer: git-send-email 2.42.0.283.g2d96d420d3-goog In-Reply-To: <20230830191314.1618136-1-dianders@chromium.org> References: <20230830191314.1618136-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As of commit 6abbd6988971 ("irqchip/gic, gic-v3: Make SGIs use handle_percpu_devid_irq()") SGIs are treated the same as PPIs/EPPIs and use handle_percpu_devid_irq() by default. Unfortunately, handle_percpu_devid_irq() isn't NMI safe, and so to run in an NMI context those should use handle_percpu_devid_fasteoi_nmi(). In order to accomplish this, we just have to make room for SGIs in the array of refcounts that keeps track of which interrupts are set as NMI. We also rename the array and create a new indexing scheme that accounts for SGIs. Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as IRQs/NMIs happen as part of this routine. Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Signed-off-by: Douglas Anderson Acked-by: Mark Rutland Tested-by: Chen-Yu Tsai --- I'll note that this change is a little more black magic to me than others in this series. I don't have a massive amounts of familiarity with all the moving parts of gic-v3, so I mostly just followed Mark Rutland's advice [1]. Please pay extra attention to make sure I didn't do anything too terrible. Mark's advice wasn't a full patch and I ended up doing a bit of work to translate it to reality, so I did not add him as "Co-developed-by" here. Mark: if you would like this tag then please provide it and your Signed-off-by. I certainly won't object. [1] https://lore.kernel.org/r/ZNC-YRQopO0PaIIo@FVFF77S0Q05N.cambridge.arm.c= om Changes in v12: - Added a comment about why we account for 16 SGIs when Linux uses 8. Changes in v10: - Rewrite as needed for 5.11+ as per Mark Rutland and Sumit. drivers/irqchip/irq-gic-v3.c | 59 +++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index eedfa8e9f077..8d20122ba0a8 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -78,6 +78,13 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) =20 +/* + * There are 16 SGIs, though we only actually use 8 in Linux. The other 8 = SGIs + * are potentially stolen by the secure side. Some code, especially code d= ealing + * with hwirq IDs, is simplified by accounting for all 16. + */ +#define SGI_NR 16 + /* * The behaviours of RPR and PMR registers differ depending on the value of * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the @@ -125,8 +132,8 @@ EXPORT_SYMBOL(gic_nonsecure_priorities); __priority; \ }) =20 -/* ppi_nmi_refs[n] =3D=3D number of cpus having ppi[n + 16] set as NMI */ -static refcount_t *ppi_nmi_refs; +/* rdist_nmi_refs[n] =3D=3D number of cpus having the rdist interrupt n se= t as NMI */ +static refcount_t *rdist_nmi_refs; =20 static struct gic_kvm_info gic_v3_kvm_info __initdata; static DEFINE_PER_CPU(bool, has_rss); @@ -519,9 +526,22 @@ static u32 __gic_get_ppi_index(irq_hw_number_t hwirq) } } =20 -static u32 gic_get_ppi_index(struct irq_data *d) +static u32 __gic_get_rdist_idx(irq_hw_number_t hwirq) +{ + switch (__get_intid_range(hwirq)) { + case SGI_RANGE: + case PPI_RANGE: + return hwirq; + case EPPI_RANGE: + return hwirq - EPPI_BASE_INTID + 32; + default: + unreachable(); + } +} + +static u32 gic_get_rdist_idx(struct irq_data *d) { - return __gic_get_ppi_index(d->hwirq); + return __gic_get_rdist_idx(d->hwirq); } =20 static int gic_irq_nmi_setup(struct irq_data *d) @@ -545,11 +565,14 @@ static int gic_irq_nmi_setup(struct irq_data *d) =20 /* desc lock should already be held */ if (gic_irq_in_rdist(d)) { - u32 idx =3D gic_get_ppi_index(d); + u32 idx =3D gic_get_rdist_idx(d); =20 - /* Setting up PPI as NMI, only switch handler for first NMI */ - if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { - refcount_set(&ppi_nmi_refs[idx], 1); + /* + * Setting up a percpu interrupt as NMI, only switch handler + * for first NMI + */ + if (!refcount_inc_not_zero(&rdist_nmi_refs[idx])) { + refcount_set(&rdist_nmi_refs[idx], 1); desc->handle_irq =3D handle_percpu_devid_fasteoi_nmi; } } else { @@ -582,10 +605,10 @@ static void gic_irq_nmi_teardown(struct irq_data *d) =20 /* desc lock should already be held */ if (gic_irq_in_rdist(d)) { - u32 idx =3D gic_get_ppi_index(d); + u32 idx =3D gic_get_rdist_idx(d); =20 /* Tearing down NMI, only switch handler for last NMI */ - if (refcount_dec_and_test(&ppi_nmi_refs[idx])) + if (refcount_dec_and_test(&rdist_nmi_refs[idx])) desc->handle_irq =3D handle_percpu_devid_irq; } else { desc->handle_irq =3D handle_fasteoi_irq; @@ -1279,10 +1302,10 @@ static void gic_cpu_init(void) rbase =3D gic_data_rdist_sgi_base(); =20 /* Configure SGIs/PPIs as non-secure Group-1 */ - for (i =3D 0; i < gic_data.ppi_nr + 16; i +=3D 32) + for (i =3D 0; i < gic_data.ppi_nr + SGI_NR; i +=3D 32) writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); =20 - gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); + gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR, gic_redist_wait_for_rwp); =20 /* initialise system registers */ gic_cpu_sys_reg_init(); @@ -1939,12 +1962,13 @@ static void gic_enable_nmi_support(void) return; } =20 - ppi_nmi_refs =3D kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERN= EL); - if (!ppi_nmi_refs) + rdist_nmi_refs =3D kcalloc(gic_data.ppi_nr + SGI_NR, + sizeof(*rdist_nmi_refs), GFP_KERNEL); + if (!rdist_nmi_refs) return; =20 - for (i =3D 0; i < gic_data.ppi_nr; i++) - refcount_set(&ppi_nmi_refs[i], 0); + for (i =3D 0; i < gic_data.ppi_nr + SGI_NR; i++) + refcount_set(&rdist_nmi_refs[i], 0); =20 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", gic_has_relaxed_pmr_sync() ? "relaxed" : "forced"); @@ -2061,6 +2085,7 @@ static int __init gic_init_bases(phys_addr_t dist_phy= s_base, =20 gic_dist_init(); gic_cpu_init(); + gic_enable_nmi_support(); gic_smp_init(); gic_cpu_pm_init(); =20 @@ -2073,8 +2098,6 @@ static int __init gic_init_bases(phys_addr_t dist_phy= s_base, gicv2m_init(handle, gic_data.domain); } =20 - gic_enable_nmi_support(); - return 0; =20 out_free: --=20 2.42.0.283.g2d96d420d3-goog From nobody Fri Dec 19 02:49:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB7C7C83F01 for ; Wed, 30 Aug 2023 19:50:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239049AbjH3TuE (ORCPT ); Wed, 30 Aug 2023 15:50:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240686AbjH3Ttf (ORCPT ); Wed, 30 Aug 2023 15:49:35 -0400 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4042910D8 for ; Wed, 30 Aug 2023 12:16:01 -0700 (PDT) Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-1bf57366ccdso8535025ad.1 for ; Wed, 30 Aug 2023 12:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1693422821; x=1694027621; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZcYgzJmdMLPe2IlWA1yPnnbUqn3VnbnF5Y/j/01p/cw=; b=EdyVQZDR0e/8asToAwLlLI7455Cq8Q6v4RyYLDFO2ccfRtGPERkU5VnsBPBDX/y5+u pkEkG5t1Pe4jwmPg1bDls7b9uqrvUfAaHoOsPG+AOAvxWJfLSI0gnK4CFrOdYuMXwoR0 KVlsJ+erP9GkBg0vMTXTQ3lPtNoRLM2h+OB0Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693422821; x=1694027621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZcYgzJmdMLPe2IlWA1yPnnbUqn3VnbnF5Y/j/01p/cw=; b=jphD98Xgx6Ispna4OhJuRvun1t8sjF4SfR2OKaV9qh5UFRvJciKvy27OxNyEWVyEoN Jl8BPWPDbflOwgDPeE4zE9s5jDsLRoZdtBCDVzg755NUYc3HPTVRPGIb4LPFZubFcvob er+BFMQ5hxhyRtTdan3k41DijKs5I8c7GyEjap3lZ0P9N1va4iR0SwH+bztV0dRvKMbZ JZfgRqf/yx9soJR8jlufQ24bJ9W71ecsQUmsmh6iP0AH7Rv+pLdd3zj2O8vdzKV6P9p+ xufJH/As9IlYJCTnnVyb42oyfQSBC4/nbwowTeB1S8bKXrnUXht8LYXBHR6mG+z8sqho WZLA== X-Gm-Message-State: AOJu0YyMLntqhPwDdMFzd84mZ5OCx5yY8ueGbL3xINu/nf1F3ve5Cai+ 5y4GahvKxciUpTyQeG0zaVMh/g== X-Google-Smtp-Source: AGHT+IG6twoQxbusQyqNYajt9MUxkEGt9m+q9o/FOJcMdRNJj/VNJrOH6rag6dueRkF1UgSa1G+MZQ== X-Received: by 2002:a17:903:2448:b0:1bc:7312:78e2 with SMTP id l8-20020a170903244800b001bc731278e2mr835918pls.5.1693422820749; Wed, 30 Aug 2023 12:13:40 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:e315:dec6:467c:83c5]) by smtp.gmail.com with ESMTPSA id c15-20020a170902d48f00b001bbdf32f011sm11338928plg.269.2023.08.30.12.13.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 12:13:39 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, Masayoshi Mizuma , "Rafael J . Wysocki" , Chen-Yu Tsai , Lecopzer Chen , Tomohiro Misono , Stephane Eranian , kgdb-bugreport@lists.sourceforge.net, Peter Zijlstra , Thomas Gleixner , Stephen Boyd , ito-yuichi@fujitsu.com, linux-perf-users@vger.kernel.org, Ard Biesheuvel , Douglas Anderson , Frederic Weisbecker , Ingo Molnar , linux-kernel@vger.kernel.org Subject: [PATCH v12 2/7] arm64: idle: Tag the arm64 idle functions as __cpuidle Date: Wed, 30 Aug 2023 12:11:23 -0700 Message-ID: <20230830121115.v12.2.I4baba13e220bdd24d11400c67f137c35f07f82c7@changeid> X-Mailer: git-send-email 2.42.0.283.g2d96d420d3-goog In-Reply-To: <20230830191314.1618136-1-dianders@chromium.org> References: <20230830191314.1618136-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As per the (somewhat recent) comment before the definition of `__cpuidle`, the tag is like `noinstr` but also marks a function so it can be identified by cpu_in_idle(). Let's add these markings to arm64 cpuidle functions With this change we get useful backtraces like: NMI backtrace for cpu N skipped: idling at cpu_do_idle+0x94/0x98 instead of useless backtraces when dumping all processors using nmi_cpu_backtrace(). NOTE: this patch won't make cpu_in_idle() work perfectly for arm64, but it doesn't hurt and does catch some cases. Specifically an example that wasn't caught in my testing looked like this: gic_cpu_sys_reg_init+0x1f8/0x314 gic_cpu_pm_notifier+0x40/0x78 raw_notifier_call_chain+0x5c/0x134 cpu_pm_notify+0x38/0x64 cpu_pm_exit+0x20/0x2c psci_enter_idle_state+0x48/0x70 cpuidle_enter_state+0xb8/0x260 cpuidle_enter+0x44/0x5c do_idle+0x188/0x30c Acked-by: Mark Rutland Reviewed-by: Stephen Boyd Acked-by: Sumit Garg Signed-off-by: Douglas Anderson Tested-by: Chen-Yu Tsai --- (no changes since v11) Changes in v11: - Updated commit message as per Stephen. Changes in v9: - Added to commit message that this doesn't catch all cases. Changes in v8: - "Tag the arm64 idle functions as __cpuidle" new for v8 arch/arm64/kernel/idle.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/idle.c b/arch/arm64/kernel/idle.c index c1125753fe9b..05cfb347ec26 100644 --- a/arch/arm64/kernel/idle.c +++ b/arch/arm64/kernel/idle.c @@ -20,7 +20,7 @@ * ensure that interrupts are not masked at the PMR (because the core will * not wake up if we block the wake up signal in the interrupt controller). */ -void noinstr cpu_do_idle(void) +void __cpuidle cpu_do_idle(void) { struct arm_cpuidle_irq_context context; =20 @@ -35,7 +35,7 @@ void noinstr cpu_do_idle(void) /* * This is our default idle handler. */ -void noinstr arch_cpu_idle(void) +void __cpuidle arch_cpu_idle(void) { /* * This should do all the clock switching and wait for interrupt --=20 2.42.0.283.g2d96d420d3-goog From nobody Fri Dec 19 02:49:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 638E3C83F01 for ; Wed, 30 Aug 2023 19:49:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231548AbjH3Ttr (ORCPT ); Wed, 30 Aug 2023 15:49:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239762AbjH3TtW (ORCPT ); Wed, 30 Aug 2023 15:49:22 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E296B10CF for ; Wed, 30 Aug 2023 12:15:18 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1bf6ea270b2so106335ad.0 for ; Wed, 30 Aug 2023 12:15:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1693422823; x=1694027623; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QGHKcN7Ka8B60Cc8NAsYNSueTLmOdg2PizihYDqFSZs=; b=Hc7b5t69epHVtlqmNyCmjgk9wup/pX46JkVLnJEoGxyyAE7YWGuP/BFiLWikYBNdnV Dds/Trg/IKCnj5vKfm2DCvcGLRYpMLCEQzUxzC+yibQ9mdY3YeIME1pYpTHF6tVi2BgS jjb41DKLzHBcM6mUBqWYC95uAXZtWxWRkv9Zg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693422823; x=1694027623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QGHKcN7Ka8B60Cc8NAsYNSueTLmOdg2PizihYDqFSZs=; b=hV2AbXb+O34m9z16q46MFQUuIQCDPGDU74WbXrbn/b489pt2g/Utg3bxpMr4/TMj4R luh/EH/C9rrA7k9zKxrbC/6Q3s3SUWT8Mk3b3hKaN9aGRHmC/YSmK03yjiT5fccutnIm GUAHteH3nzF0nJ9CbOhQLr3UQVJ9ySIVPsuGfhRrTChLtp/wOg2v0wjN6HVM3mUoLxtH 0iaDnhxO4UZqgCafFP4+AK9yRzW+6Ztrw7ZMkwtZp17iFZTZxQMKdDjZckOJP2i/L586 s52Q076ecsLWTX3ScQMix+jZ6Ykbm4+Qm7JgYRir4uUn5RdZEAHC+ZRjL7VrRbMsPweq Ofdw== X-Gm-Message-State: AOJu0YwYHPYzumL14WAIkgQevUIMZEZwW1odBQZ20958rpR+5nZYsDLn fUrAA6zO8KXwfGFlcsQtKwZLqQ== X-Google-Smtp-Source: AGHT+IGHLoraFTbGB/BxEaiA4QfM3FoXZ9A5Wt6qDnQMmcmH/dI+mTNuF8xBJCW6mk1vkdMY6M7zoA== X-Received: by 2002:a17:902:d48e:b0:1b9:f7f4:5687 with SMTP id c14-20020a170902d48e00b001b9f7f45687mr3502248plg.24.1693422823023; Wed, 30 Aug 2023 12:13:43 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:e315:dec6:467c:83c5]) by smtp.gmail.com with ESMTPSA id c15-20020a170902d48f00b001bbdf32f011sm11338928plg.269.2023.08.30.12.13.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 12:13:42 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, Masayoshi Mizuma , "Rafael J . Wysocki" , Chen-Yu Tsai , Lecopzer Chen , Tomohiro Misono , Stephane Eranian , kgdb-bugreport@lists.sourceforge.net, Peter Zijlstra , Thomas Gleixner , Stephen Boyd , ito-yuichi@fujitsu.com, linux-perf-users@vger.kernel.org, Ard Biesheuvel , Douglas Anderson , D Scott Phillips , Josh Poimboeuf , Kees Cook , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Tolvanen , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v12 3/7] arm64: smp: Remove dedicated wakeup IPI Date: Wed, 30 Aug 2023 12:11:24 -0700 Message-ID: <20230830121115.v12.3.I7209db47ef8ec151d3de61f59005bbc59fe8f113@changeid> X-Mailer: git-send-email 2.42.0.283.g2d96d420d3-goog In-Reply-To: <20230830191314.1618136-1-dianders@chromium.org> References: <20230830191314.1618136-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Mark Rutland To enable NMI backtrace and KGDB's NMI cpu roundup, we need to free up at least one dedicated IPI. On arm64 the IPI_WAKEUP IPI is only used for the ACPI parking protocol, which itself is only used on some very early ARMv8 systems which couldn't implement PSCI. Remove the IPI_WAKEUP IPI, and rely on the IPI_RESCHEDULE IPI to wake CPUs from the parked state. This will cause a tiny amonut of redundant work to check the thread flags, but this is miniscule in relation to the cost of taking and handling the IPI in the first place. We can safely handle redundant IPI_RESCHEDULE IPIs, so there should be no functional impact as a result of this change. Signed-off-by: Mark Rutland Reviewed-by: Stephen Boyd Reviewed-by: Sumit Garg Signed-off-by: Douglas Anderson Cc: Catalin Marinas Cc: Marc Zyngier Cc: Will Deacon Tested-by: Chen-Yu Tsai --- I have no idea how to test this. I just took Mark's patch and jammed it into my series. Logicially the patch seems reasonable to me. (no changes since v11) Changes in v11: - arch_send_wakeup_ipi() now takes an unsigned int. Changes in v10: - ("arm64: smp: Remove dedicated wakeup IPI") new for v10. arch/arm64/include/asm/smp.h | 4 ++-- arch/arm64/kernel/acpi_parking_protocol.c | 2 +- arch/arm64/kernel/smp.c | 28 +++++++++-------------- 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 9b31e6d0da17..efb13112b408 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -89,9 +89,9 @@ extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); =20 #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL -extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); +extern void arch_send_wakeup_ipi(unsigned int cpu); #else -static inline void arch_send_wakeup_ipi_mask(const struct cpumask *mask) +static inline void arch_send_wakeup_ipi(unsigned int cpu) { BUILD_BUG(); } diff --git a/arch/arm64/kernel/acpi_parking_protocol.c b/arch/arm64/kernel/= acpi_parking_protocol.c index b1990e38aed0..e1be29e608b7 100644 --- a/arch/arm64/kernel/acpi_parking_protocol.c +++ b/arch/arm64/kernel/acpi_parking_protocol.c @@ -103,7 +103,7 @@ static int acpi_parking_protocol_cpu_boot(unsigned int = cpu) &mailbox->entry_point); writel_relaxed(cpu_entry->gic_cpu_id, &mailbox->cpu_id); =20 - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + arch_send_wakeup_ipi(cpu); =20 return 0; } diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 960b98b43506..a5848f1ef817 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -72,7 +72,6 @@ enum ipi_msg_type { IPI_CPU_CRASH_STOP, IPI_TIMER, IPI_IRQ_WORK, - IPI_WAKEUP, NR_IPI }; =20 @@ -764,7 +763,6 @@ static const char *ipi_types[NR_IPI] __tracepoint_strin= g =3D { [IPI_CPU_CRASH_STOP] =3D "CPU stop (for crash dump) interrupts", [IPI_TIMER] =3D "Timer broadcast interrupts", [IPI_IRQ_WORK] =3D "IRQ work interrupts", - [IPI_WAKEUP] =3D "CPU wake-up interrupts", }; =20 static void smp_cross_call(const struct cpumask *target, unsigned int ipin= r); @@ -797,13 +795,6 @@ void arch_send_call_function_single_ipi(int cpu) smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); } =20 -#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL -void arch_send_wakeup_ipi_mask(const struct cpumask *mask) -{ - smp_cross_call(mask, IPI_WAKEUP); -} -#endif - #ifdef CONFIG_IRQ_WORK void arch_irq_work_raise(void) { @@ -897,14 +888,6 @@ static void do_handle_IPI(int ipinr) break; #endif =20 -#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL - case IPI_WAKEUP: - WARN_ONCE(!acpi_parking_protocol_valid(cpu), - "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", - cpu); - break; -#endif - default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; @@ -979,6 +962,17 @@ void arch_smp_send_reschedule(int cpu) smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); } =20 +#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL +void arch_send_wakeup_ipi(unsigned int cpu) +{ + /* + * We use a scheduler IPI to wake the CPU as this avoids the need for a + * dedicated IPI and we can safely handle spurious scheduler IPIs. + */ + arch_smp_send_reschedule(cpu); +} +#endif + #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST void tick_broadcast(const struct cpumask *mask) { --=20 2.42.0.283.g2d96d420d3-goog From nobody Fri Dec 19 02:49:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C247FC6FA8F for ; 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Wed, 30 Aug 2023 12:13:45 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:e315:dec6:467c:83c5]) by smtp.gmail.com with ESMTPSA id c15-20020a170902d48f00b001bbdf32f011sm11338928plg.269.2023.08.30.12.13.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 12:13:44 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, Masayoshi Mizuma , "Rafael J . Wysocki" , Chen-Yu Tsai , Lecopzer Chen , Tomohiro Misono , Stephane Eranian , kgdb-bugreport@lists.sourceforge.net, Peter Zijlstra , Thomas Gleixner , Stephen Boyd , ito-yuichi@fujitsu.com, linux-perf-users@vger.kernel.org, Ard Biesheuvel , Douglas Anderson , D Scott Phillips , Josh Poimboeuf , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v12 4/7] arm64: smp: Add arch support for backtrace using pseudo-NMI Date: Wed, 30 Aug 2023 12:11:25 -0700 Message-ID: <20230830121115.v12.4.Ie6c132b96ebbbcddbf6954b9469ed40a6960343c@changeid> X-Mailer: git-send-email 2.42.0.283.g2d96d420d3-goog In-Reply-To: <20230830191314.1618136-1-dianders@chromium.org> References: <20230830191314.1618136-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable arch_trigger_cpumask_backtrace() support on arm64. This enables things much like they are enabled on arm32 (including some of the funky logic around NR_IPI, nr_ipi, and MAX_IPI) but with the difference that, unlike arm32, we'll try to enable the backtrace to use pseudo-NMI. NOTE: this patch is a squash of the little bit of code adding the ability to mark an IPI to try to use pseudo-NMI plus the little bit of code to hook things up for kgdb. This approach was decided upon in the discussion of v9 [1]. This patch depends on commit 8d539b84f1e3 ("nmi_backtrace: allow excluding an arbitrary CPU") since that commit changed the prototype of arch_trigger_cpumask_backtrace(), which this patch implements. [1] https://lore.kernel.org/r/ZORY51mF4alI41G1@FVFF77S0Q05N Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Co-developed-by: Mark Rutland Signed-off-by: Mark Rutland Reviewed-by: Stephen Boyd Reviewed-by: Misono Tomohiro Signed-off-by: Douglas Anderson Tested-by: Chen-Yu Tsai --- Changes in v12: - Minor comment change to add "()" after nmi_trigger_cpumask_backtrace. - Updated the commit hash of the commit this depends on. Changes in v11: - Adjust comment about NR_IPI/MAX_IPI. - Don't use confusing "backed by" idiom in comment. - Made arm64_backtrace_ipi() static. Changes in v10: - Backtrace now directly supported in smp.c - Squash backtrace into patch adding support for pseudo-NMI IPIs. Changes in v9: - Added comments that we might not be using NMI always. - Fold in v8 patch #10 ("Fallback to a regular IPI if NMI isn't enabled") - Moved header file out of "include" since it didn't need to be there. - Remove arm64_supports_nmi() - Renamed "NMI IPI" to "debug IPI" since it might not be backed by NMI. - arch_trigger_cpumask_backtrace() no longer returns bool Changes in v8: - Removed "#ifdef CONFIG_SMP" since arm64 is always SMP - debug_ipi_setup() and debug_ipi_teardown() no longer take cpu param arch/arm64/include/asm/irq.h | 3 ++ arch/arm64/kernel/smp.c | 86 +++++++++++++++++++++++++++++++----- 2 files changed, 78 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index fac08e18bcd5..50ce8b697ff3 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -6,6 +6,9 @@ =20 #include =20 +void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu= ); +#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace + struct pt_regs; =20 int set_handle_irq(void (*handle_irq)(struct pt_regs *)); diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index a5848f1ef817..28c904ca499a 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -33,6 +33,7 @@ #include #include #include +#include =20 #include #include @@ -72,12 +73,18 @@ enum ipi_msg_type { IPI_CPU_CRASH_STOP, IPI_TIMER, IPI_IRQ_WORK, - NR_IPI + NR_IPI, + /* + * Any enum >=3D NR_IPI and < MAX_IPI is special and not tracable + * with trace_ipi_* + */ + IPI_CPU_BACKTRACE =3D NR_IPI, + MAX_IPI }; =20 static int ipi_irq_base __read_mostly; static int nr_ipi __read_mostly =3D NR_IPI; -static struct irq_desc *ipi_desc[NR_IPI] __read_mostly; +static struct irq_desc *ipi_desc[MAX_IPI] __read_mostly; =20 static void ipi_setup(int cpu); =20 @@ -845,6 +852,22 @@ static void __noreturn ipi_cpu_crash_stop(unsigned int= cpu, struct pt_regs *regs #endif } =20 +static void arm64_backtrace_ipi(cpumask_t *mask) +{ + __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask); +} + +void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) +{ + /* + * NOTE: though nmi_trigger_cpumask_backtrace() has "nmi_" in the name, + * nothing about it truly needs to be implemented using an NMI, it's + * just that it's _allowed_ to work with NMIs. If ipi_should_be_nmi() + * returned false our backtrace attempt will just use a regular IPI. + */ + nmi_trigger_cpumask_backtrace(mask, exclude_cpu, arm64_backtrace_ipi); +} + /* * Main handler for inter-processor interrupts */ @@ -888,6 +911,14 @@ static void do_handle_IPI(int ipinr) break; #endif =20 + case IPI_CPU_BACKTRACE: + /* + * NOTE: in some cases this _won't_ be NMI context. See the + * comment in arch_trigger_cpumask_backtrace(). + */ + nmi_cpu_backtrace(get_irq_regs()); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; @@ -909,6 +940,19 @@ static void smp_cross_call(const struct cpumask *targe= t, unsigned int ipinr) __ipi_send_mask(ipi_desc[ipinr], target); } =20 +static bool ipi_should_be_nmi(enum ipi_msg_type ipi) +{ + if (!system_uses_irq_prio_masking()) + return false; + + switch (ipi) { + case IPI_CPU_BACKTRACE: + return true; + default: + return false; + } +} + static void ipi_setup(int cpu) { int i; @@ -916,8 +960,14 @@ static void ipi_setup(int cpu) if (WARN_ON_ONCE(!ipi_irq_base)) return; =20 - for (i =3D 0; i < nr_ipi; i++) - enable_percpu_irq(ipi_irq_base + i, 0); + for (i =3D 0; i < nr_ipi; i++) { + if (ipi_should_be_nmi(i)) { + prepare_percpu_nmi(ipi_irq_base + i); + enable_percpu_nmi(ipi_irq_base + i, 0); + } else { + enable_percpu_irq(ipi_irq_base + i, 0); + } + } } =20 #ifdef CONFIG_HOTPLUG_CPU @@ -928,8 +978,14 @@ static void ipi_teardown(int cpu) if (WARN_ON_ONCE(!ipi_irq_base)) return; =20 - for (i =3D 0; i < nr_ipi; i++) - disable_percpu_irq(ipi_irq_base + i); + for (i =3D 0; i < nr_ipi; i++) { + if (ipi_should_be_nmi(i)) { + disable_percpu_nmi(ipi_irq_base + i); + teardown_percpu_nmi(ipi_irq_base + i); + } else { + disable_percpu_irq(ipi_irq_base + i); + } + } } #endif =20 @@ -937,15 +993,23 @@ void __init set_smp_ipi_range(int ipi_base, int n) { int i; =20 - WARN_ON(n < NR_IPI); - nr_ipi =3D min(n, NR_IPI); + WARN_ON(n < MAX_IPI); + nr_ipi =3D min(n, MAX_IPI); =20 for (i =3D 0; i < nr_ipi; i++) { int err; =20 - err =3D request_percpu_irq(ipi_base + i, ipi_handler, - "IPI", &cpu_number); - WARN_ON(err); + if (ipi_should_be_nmi(i)) { + err =3D request_percpu_nmi(ipi_base + i, ipi_handler, + "IPI", &cpu_number); + WARN(err, "Could not request IPI %d as NMI, err=3D%d\n", + i, err); + } else { + err =3D request_percpu_irq(ipi_base + i, ipi_handler, + "IPI", &cpu_number); + WARN(err, "Could not request IPI %d as IRQ, err=3D%d\n", + i, err); + } =20 ipi_desc[i] =3D irq_to_desc(ipi_base + i); irq_set_status_flags(ipi_base + i, IRQ_HIDDEN); --=20 2.42.0.283.g2d96d420d3-goog From nobody Fri Dec 19 02:49:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3297C6FA8F for ; Wed, 30 Aug 2023 20:32:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239756AbjH3Uc3 (ORCPT ); Wed, 30 Aug 2023 16:32:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239750AbjH3UcR (ORCPT ); Wed, 30 Aug 2023 16:32:17 -0400 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B99931244E for ; Wed, 30 Aug 2023 12:29:20 -0700 (PDT) Received: by mail-qk1-x734.google.com with SMTP id af79cd13be357-76f08e302a1so2714985a.1 for ; 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Wed, 30 Aug 2023 12:13:47 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:e315:dec6:467c:83c5]) by smtp.gmail.com with ESMTPSA id c15-20020a170902d48f00b001bbdf32f011sm11338928plg.269.2023.08.30.12.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 12:13:46 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, Masayoshi Mizuma , "Rafael J . Wysocki" , Chen-Yu Tsai , Lecopzer Chen , Tomohiro Misono , Stephane Eranian , kgdb-bugreport@lists.sourceforge.net, Peter Zijlstra , Thomas Gleixner , Stephen Boyd , ito-yuichi@fujitsu.com, linux-perf-users@vger.kernel.org, Ard Biesheuvel , Douglas Anderson , D Scott Phillips , Josh Poimboeuf , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v12 5/7] arm64: smp: IPI_CPU_STOP and IPI_CPU_CRASH_STOP should try for NMI Date: Wed, 30 Aug 2023 12:11:26 -0700 Message-ID: <20230830121115.v12.5.Ifadbfd45b22c52edcb499034dd4783d096343260@changeid> X-Mailer: git-send-email 2.42.0.283.g2d96d420d3-goog In-Reply-To: <20230830191314.1618136-1-dianders@chromium.org> References: <20230830191314.1618136-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There's no reason why IPI_CPU_STOP and IPI_CPU_CRASH_STOP can't be handled as NMI. They are very simple and everything in them is NMI-safe. Mark them as things to use NMI for if NMI is available. Suggested-by: Mark Rutland Reviewed-by: Stephen Boyd Reviewed-by: Misono Tomohiro Reviewed-by: Sumit Garg Signed-off-by: Douglas Anderson Acked-by: Mark Rutland Tested-by: Chen-Yu Tsai Tested-by: Mark Rutland --- I don't actually have any good way to test/validate this patch. It's added to the series at Mark's request. (no changes since v10) Changes in v10: - ("IPI_CPU_STOP and IPI_CPU_CRASH_STOP should try for NMI") new for v10. arch/arm64/kernel/smp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 28c904ca499a..800c59cf9b64 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -946,6 +946,8 @@ static bool ipi_should_be_nmi(enum ipi_msg_type ipi) return false; =20 switch (ipi) { + case IPI_CPU_STOP: + case IPI_CPU_CRASH_STOP: case IPI_CPU_BACKTRACE: return true; default: --=20 2.42.0.283.g2d96d420d3-goog From nobody Fri Dec 19 02:49:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E39D4C83F01 for ; Wed, 30 Aug 2023 20:30:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239992AbjH3Uae (ORCPT ); Wed, 30 Aug 2023 16:30:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239867AbjH3UaQ (ORCPT ); Wed, 30 Aug 2023 16:30:16 -0400 Received: from mail-qv1-xf2e.google.com (mail-qv1-xf2e.google.com [IPv6:2607:f8b0:4864:20::f2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B7A7322FD for ; Wed, 30 Aug 2023 12:24:55 -0700 (PDT) Received: by mail-qv1-xf2e.google.com with SMTP id 6a1803df08f44-64f387094ddso544236d6.3 for ; Wed, 30 Aug 2023 12:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1693423443; x=1694028243; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=noX4yZdaLohQeeiEyvyLjmGW8lnsNXNGq5GJE9PggTY=; b=mvzmUEnk65x4gEjEyF3rhbv6Atmm/zyrhIJFS0fgmlFGJ89Q4acjwNlYqjKm3+BMWy phQEj29lNzfiQF02/b49CEwWL8R1J+HG+dA3bIqHgArRMul6ymn/0LvW/LsizgwkBbPI BpJOShbxKcN6IDeV4/Rt/KQMTDzyUUM63us7s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693423443; x=1694028243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=noX4yZdaLohQeeiEyvyLjmGW8lnsNXNGq5GJE9PggTY=; b=MuTCMx0mR1cKCHiLzR8jasOwpAWdZfffQdRejTUa72OYoVyb0vv232wjgJUk2JA7GX XUJ9dNn1N0izQUGOUvXp3yKtlyORAekAxtnI0M3Rvgc2bqw9WfYsxCiRzQLSyxcgYqcA Vk8GSQEcIwdj7/fZSuNCmh3knVGK6MihIaqNbuJ4rI7C8TYb+WahB3a1ySqYd9m/WysE SFD8D88V5ESrrkY8Cd3dGASKYtiQW7uDHLNNhPxP6bSFDAtmHogOAto8syweaobg5G87 hzqlCZVatgO2lAiQgC/XgHZeG3qwesgPvzO5MNAemA9WRz4kVCmP7Jwu6dFIVUGjZh/n JPpw== X-Gm-Message-State: AOJu0YwGhHv2NAk5VejJ0g2w9SRJFa9qtygxnJS+imqkzJqRA8XAhMlb C2UwZEdv0qfcHo9aPEf9rNCuMoObcmmQeannMLRt3okL X-Google-Smtp-Source: AGHT+IGdb5Mb2GxsmI1BOhJNHIBP+oW3B+qOgeklBIYfkq+/l/caGuTOikwQNy7fuKfgn5kIZmdgGA== X-Received: by 2002:a17:902:ef93:b0:1b7:e49f:1d with SMTP id iz19-20020a170902ef9300b001b7e49f001dmr3090765plb.62.1693422829677; Wed, 30 Aug 2023 12:13:49 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:e315:dec6:467c:83c5]) by smtp.gmail.com with ESMTPSA id c15-20020a170902d48f00b001bbdf32f011sm11338928plg.269.2023.08.30.12.13.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 12:13:49 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, Masayoshi Mizuma , "Rafael J . Wysocki" , Chen-Yu Tsai , Lecopzer Chen , Tomohiro Misono , Stephane Eranian , kgdb-bugreport@lists.sourceforge.net, Peter Zijlstra , Thomas Gleixner , Stephen Boyd , ito-yuichi@fujitsu.com, linux-perf-users@vger.kernel.org, Ard Biesheuvel , Douglas Anderson , D Scott Phillips , Josh Poimboeuf , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v12 6/7] arm64: kgdb: Implement kgdb_roundup_cpus() to enable pseudo-NMI roundup Date: Wed, 30 Aug 2023 12:11:27 -0700 Message-ID: <20230830121115.v12.6.I2ef26d1b3bfbed2d10a281942b0da7d9854de05e@changeid> X-Mailer: git-send-email 2.42.0.283.g2d96d420d3-goog In-Reply-To: <20230830191314.1618136-1-dianders@chromium.org> References: <20230830191314.1618136-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Up until now we've been using the generic (weak) implementation for kgdb_roundup_cpus() when using kgdb on arm64. Let's move to a custom one. The advantage here is that, when pseudo-NMI is enabled on a device, we'll be able to round up CPUs using pseudo-NMI. This allows us to debug CPUs that are stuck with interrupts disabled. If pseudo-NMIs are not enabled then we'll fallback to just using an IPI, which is still slightly better than the generic implementation since it avoids the potential situation described in the generic kgdb_call_nmi_hook(). Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Reviewed-by: Daniel Thompson Reviewed-by: Stephen Boyd Signed-off-by: Douglas Anderson Acked-by: Mark Rutland Tested-by: Chen-Yu Tsai --- I debated whether this should be in "arch/arm64/kernel/smp.c" or if I should try to find a way for it to go into "arch/arm64/kernel/kgdb.c". In the end this is so little code that it didn't seem worth it to find a way to export the IPI defines or to otherwise come up with some API between kgdb.c and smp.c. If someone has strong feelings and wants this to change, please shout and give details of your preferred solution. FWIW, it seems like ~half the other platforms put this in "smp.c" with an ifdef for KGDB and the other half put it in "kgdb.c" with an ifdef for SMP. :-P (no changes since v10) Changes in v10: - Don't allocate the cpumask on the stack; just iterate. - Moved kgdb calls to smp.c to avoid needing to export IPI info. - kgdb now has its own IPI. Changes in v9: - Remove fallback for when debug IPI isn't available. - Renamed "NMI IPI" to "debug IPI" since it might not be backed by NMI. arch/arm64/kernel/smp.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 800c59cf9b64..1a53e57c81d0 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include =20 @@ -79,6 +80,7 @@ enum ipi_msg_type { * with trace_ipi_* */ IPI_CPU_BACKTRACE =3D NR_IPI, + IPI_KGDB_ROUNDUP, MAX_IPI }; =20 @@ -868,6 +870,22 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *m= ask, int exclude_cpu) nmi_trigger_cpumask_backtrace(mask, exclude_cpu, arm64_backtrace_ipi); } =20 +#ifdef CONFIG_KGDB +void kgdb_roundup_cpus(void) +{ + int this_cpu =3D raw_smp_processor_id(); + int cpu; + + for_each_online_cpu(cpu) { + /* No need to roundup ourselves */ + if (cpu =3D=3D this_cpu) + continue; + + __ipi_send_single(ipi_desc[IPI_KGDB_ROUNDUP], cpu); + } +} +#endif + /* * Main handler for inter-processor interrupts */ @@ -919,6 +937,10 @@ static void do_handle_IPI(int ipinr) nmi_cpu_backtrace(get_irq_regs()); break; =20 + case IPI_KGDB_ROUNDUP: + kgdb_nmicallback(cpu, get_irq_regs()); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; @@ -949,6 +971,7 @@ static bool ipi_should_be_nmi(enum ipi_msg_type ipi) case IPI_CPU_STOP: case IPI_CPU_CRASH_STOP: case IPI_CPU_BACKTRACE: + case IPI_KGDB_ROUNDUP: return true; default: return false; --=20 2.42.0.283.g2d96d420d3-goog From nobody Fri Dec 19 02:49:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1578DC83F15 for ; Wed, 30 Aug 2023 19:55:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231920AbjH3Tzi (ORCPT ); Wed, 30 Aug 2023 15:55:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238701AbjH3Tz0 (ORCPT ); Wed, 30 Aug 2023 15:55:26 -0400 Received: from mail-oi1-x235.google.com (mail-oi1-x235.google.com [IPv6:2607:f8b0:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D70C732B5C for ; Wed, 30 Aug 2023 12:25:12 -0700 (PDT) Received: by mail-oi1-x235.google.com with SMTP id 5614622812f47-3a85b9deeb3so4033952b6e.1 for ; Wed, 30 Aug 2023 12:25:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1693423450; x=1694028250; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lm34Kk+maPdNp9rFuwAAy5O1fZmlUwsB3d8wqfk31DQ=; b=Cc7bzK3foUHBf/0juo6aLEYQziud+YCqD9zbpiHgcs9WHajtePd+NiVSmlR7O7HLX4 7p0mRwKGDgY6PSAV1gVEr1uL81NYmJqH5w7uDywwEn0S9Ji+2Sl/ZI6QDReUQCxPmoIz go+Xia+Ts4nqpfuisedsBsi1VWzoowtS0MhbY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693423450; x=1694028250; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lm34Kk+maPdNp9rFuwAAy5O1fZmlUwsB3d8wqfk31DQ=; b=bmI59HJyTEWXO1hayuAM2NhahyxellGGaCXARh5jNfUjniUJq/PMmF8mxccirA3oev Y643ChxV3lEWMn2lZxmlM7LFTQLEueP83yiGkk/58MlXkhjuGaBlYlAf2iaH1KllHzDf h7hKROo2UKyZZftsB1/QXMNJOv54ruc3UvD36vYQ+XGVTPinAljFVDsNPblw6WFZJ8Ps nVhUZniIzeqJNkzLoSuknGKt18dwqHzMa4MTdYqU9V8u3LYIWqI2h77d2AnTpOEqGvjD wfyoQphilwrkEImf/op1EZap11loXRsVrCCSHuCNoJ5BNqXR8jfubrI6chH3bzmC5Pbs fa2g== X-Gm-Message-State: AOJu0Yy0r6FC9kO5I197wEfA63j102E/NOpjtwhskb1oTxsvHkGV7Wis UAjVKTXqD4mFOfef/aFG1xLo1LPOnMA/EEjWrvZPWoSe X-Google-Smtp-Source: AGHT+IEt4V9Q3kKv3ps387mUFelpzuS3AhZ1ooWe7nWHiUV3yMAAUWymDyit8Cg7nWN79LlkVQ4iHQ== X-Received: by 2002:a17:902:b18d:b0:1b5:1467:c4e8 with SMTP id s13-20020a170902b18d00b001b51467c4e8mr2658054plr.15.1693422833430; Wed, 30 Aug 2023 12:13:53 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:e315:dec6:467c:83c5]) by smtp.gmail.com with ESMTPSA id c15-20020a170902d48f00b001bbdf32f011sm11338928plg.269.2023.08.30.12.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Aug 2023 12:13:52 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, Masayoshi Mizuma , "Rafael J . Wysocki" , Chen-Yu Tsai , Lecopzer Chen , Tomohiro Misono , Stephane Eranian , kgdb-bugreport@lists.sourceforge.net, Peter Zijlstra , Thomas Gleixner , Stephen Boyd , ito-yuichi@fujitsu.com, linux-perf-users@vger.kernel.org, Ard Biesheuvel , Douglas Anderson , D Scott Phillips , Josh Poimboeuf , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v12 7/7] arm64: smp: Mark IPI globals as __ro_after_init Date: Wed, 30 Aug 2023 12:11:28 -0700 Message-ID: <20230830121115.v12.7.I625d393afd71e1766ef73d3bfaac0b347a4afd19@changeid> X-Mailer: git-send-email 2.42.0.283.g2d96d420d3-goog In-Reply-To: <20230830191314.1618136-1-dianders@chromium.org> References: <20230830191314.1618136-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mark the three IPI-related globals in smp.c as "__ro_after_init" since they are only ever set in set_smp_ipi_range(), which is marked "__init". This is a better and more secure marking than the old "__read_mostly". Suggested-by: Stephen Boyd Signed-off-by: Douglas Anderson Acked-by: Mark Rutland Tested-by: Chen-Yu Tsai --- This patch is almost completely unrelated to the rest of the series other than the fact that it would cause a merge conflict with the series if sent separately. I tacked it on to this series in response to Stephen's feedback on v11 of this series [1]. If someone hates it (not sure why they would), it could be dropped. If someone loves it, it could be promoted to the start of the series and/or land on its own (resolving merge conflicts). [1] https://lore.kernel.org/r/CAE-0n52iVDgZa8XT8KTMj12c_ESSJt7f7A0fuZ_oAMMq= pGcSzA@mail.gmail.com Changes in v12: - ("arm64: smp: Mark IPI globals as __ro_after_init") new for v12. arch/arm64/kernel/smp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 1a53e57c81d0..814d9aa93b21 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -84,9 +84,9 @@ enum ipi_msg_type { MAX_IPI }; =20 -static int ipi_irq_base __read_mostly; -static int nr_ipi __read_mostly =3D NR_IPI; -static struct irq_desc *ipi_desc[MAX_IPI] __read_mostly; +static int ipi_irq_base __ro_after_init; +static int nr_ipi __ro_after_init =3D NR_IPI; +static struct irq_desc *ipi_desc[MAX_IPI] __ro_after_init; =20 static void ipi_setup(int cpu); =20 --=20 2.42.0.283.g2d96d420d3-goog