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Wed, 30 Aug 2023 04:58:31 -0700 From: Sumit Gupta To: , , , CC: , , , Subject: [Patch] firmware: tegra: reset BPMP IPC channels early during resume Date: Wed, 30 Aug 2023 17:28:29 +0530 Message-ID: <20230830115829.23977-1-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E3:EE_|PH7PR12MB9104:EE_ X-MS-Office365-Filtering-Correlation-Id: da6e6d57-b820-4e89-41f0-08dba950748f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hYxUmMJHlSsVtwTzRkvnpAW7kTDkJQHGS6IuQ1qubzi5KZnVhwDy6xonadqgBe0ebMwrzuq1gwkk1pJrIwlv2xbocXKKZqUbTmlBIq5MIlDG3WhEaXMKvUdtryuQcgrT2tXQx5T5YF8yFhoe4bltYA4tMrG6KhIwC4objs5pHNEyZD8VBGB4s7jVBcN8YnF43r12vAWxeu9f/6B+qu+ht1ZxE4w+PVpKQ9e2CrsK5cBDCyH87VTpAEG8D0S4IGruNhUCVEC1Vmt7nYXqwxqjawuPxYvsC+JV/HOdSFbLp/eKWctVV8YhdnGuGnbLa2uW40ECTzdgMZgjiCzwk+TxqW8LnfNC4cEVZTaPdtvCQoeMBjx11HnXrt5TzdVxjc2u4Q0WY0O3JM0EiZj/7Pq2pQtlhDUcsPc7iib0l6hWdJBWQ6cfuUnKJtOzfcrTKi+P9GvVrfW/tyt9DNk3riaMted89DchEkPVqFM1cbcHIDXFEjqVjBUHBmELpjA2pMw+d227sCtUI0Qb1QZbXErvrhFlZFbP3IBlZLDx7Twk/QGtTYR3W6GUJsD90slS/r/te8bO+9SxUIWWGKxGEWlqBnZivBmbH+i1F4CvXrBNHgX0vXd2FSGJoLPx6u9tOaAoCECSvFIxsJ9mt8tuN+RLRLLc+lYkvDdgS/YFxfLTq5cvKCZeubEnuO8E+JTFrisc3QmKoMQByKxNXsWu2DohLt9IQoJau+o4clSNKSIGrYtydQ1s6Pt0LfiWFabTgDhd X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(376002)(396003)(346002)(186009)(82310400011)(1800799009)(451199024)(46966006)(40470700004)(36840700001)(40480700001)(40460700003)(7636003)(316002)(54906003)(70206006)(70586007)(356005)(478600001)(110136005)(82740400003)(2906002)(86362001)(8936002)(8676002)(450100002)(7696005)(41300700001)(5660300002)(4326008)(83380400001)(107886003)(36860700001)(47076005)(1076003)(26005)(426003)(2616005)(336012)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Aug 2023 11:58:42.0143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da6e6d57-b820-4e89-41f0-08dba950748f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9104 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add 'tegra_bpmp_reset()' function to reset the IPC channels for BPMP on first call to tegra_bpmp_transfer() API after system resumes. This allows us to handle any requests that might be sent too soon as they can cause hang during system resume. One case where we see BPMP requests being sent before the BPMP driver has resumed is the memory bandwidth requests which are triggered by onlining the CPUs during system resume. The CPUs are onlined before the BPMP has resumed and we need to reset the BPMP IPC channels to handle these requests. Fixes: f41e1442ac5b ("cpufreq: tegra194: add OPP support and set bandwidth") Signed-off-by: Jonathan Hunter Signed-off-by: Sumit Gupta --- drivers/firmware/tegra/bpmp-private.h | 2 +- drivers/firmware/tegra/bpmp-tegra186.c | 4 +-- drivers/firmware/tegra/bpmp.c | 45 ++++++++++++++++++++++---- include/soc/tegra/bpmp.h | 2 ++ 4 files changed, 44 insertions(+), 9 deletions(-) diff --git a/drivers/firmware/tegra/bpmp-private.h b/drivers/firmware/tegra= /bpmp-private.h index 182bfe396516..8f59bbe990dc 100644 --- a/drivers/firmware/tegra/bpmp-private.h +++ b/drivers/firmware/tegra/bpmp-private.h @@ -20,7 +20,7 @@ struct tegra_bpmp_ops { int (*post_response)(struct tegra_bpmp_channel *channel); int (*post_request)(struct tegra_bpmp_channel *channel); int (*ring_doorbell)(struct tegra_bpmp *bpmp); - int (*resume)(struct tegra_bpmp *bpmp); + int (*reset)(struct tegra_bpmp *bpmp); }; =20 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \ diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmware/tegr= a/bpmp-tegra186.c index 6f0d0511b486..122d0c630863 100644 --- a/drivers/firmware/tegra/bpmp-tegra186.c +++ b/drivers/firmware/tegra/bpmp-tegra186.c @@ -366,7 +366,7 @@ static void tegra186_bpmp_deinit(struct tegra_bpmp *bpm= p) tegra186_bpmp_teardown_channels(bpmp); } =20 -static int tegra186_bpmp_resume(struct tegra_bpmp *bpmp) +static int tegra186_bpmp_reset(struct tegra_bpmp *bpmp) { tegra186_bpmp_reset_channels(bpmp); =20 @@ -385,5 +385,5 @@ const struct tegra_bpmp_ops tegra186_bpmp_ops =3D { .post_response =3D tegra186_bpmp_post_message, .post_request =3D tegra186_bpmp_post_message, .ring_doorbell =3D tegra186_bpmp_ring_doorbell, - .resume =3D tegra186_bpmp_resume, + .reset =3D tegra186_bpmp_reset, }; diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index 51d062e0c3f1..6a269a66175e 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -313,6 +313,14 @@ static ssize_t tegra_bpmp_channel_write(struct tegra_b= pmp_channel *channel, return __tegra_bpmp_channel_write(channel, mrq, flags, data, size); } =20 +static int tegra_bpmp_reset(struct tegra_bpmp *bpmp) +{ + if (bpmp->soc->ops->reset) + return bpmp->soc->ops->reset(bpmp); + + return 0; +} + int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp, struct tegra_bpmp_message *msg) { @@ -325,6 +333,15 @@ int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp, if (!tegra_bpmp_message_valid(msg)) return -EINVAL; =20 + if (bpmp->needs_reset) { + err =3D tegra_bpmp_reset(bpmp); + if (err < 0) { + dev_err(bpmp->dev, "Failed to reset the BPMP!\n"); + return err; + } + bpmp->needs_reset =3D false; + } + channel =3D bpmp->tx_channel; =20 spin_lock(&bpmp->atomic_tx_lock); @@ -364,6 +381,15 @@ int tegra_bpmp_transfer(struct tegra_bpmp *bpmp, if (!tegra_bpmp_message_valid(msg)) return -EINVAL; =20 + if (bpmp->needs_reset) { + err =3D tegra_bpmp_reset(bpmp); + if (err < 0) { + dev_err(bpmp->dev, "Failed to reset the BPMP!\n"); + return err; + } + bpmp->needs_reset =3D false; + } + channel =3D tegra_bpmp_write_threaded(bpmp, msg->mrq, msg->tx.data, msg->tx.size); if (IS_ERR(channel)) @@ -740,6 +766,8 @@ static int tegra_bpmp_probe(struct platform_device *pde= v) if (err < 0) return err; =20 + bpmp->needs_reset =3D false; + err =3D tegra_bpmp_request_mrq(bpmp, MRQ_PING, tegra_bpmp_mrq_handle_ping, bpmp); if (err < 0) @@ -796,18 +824,23 @@ static int tegra_bpmp_probe(struct platform_device *p= dev) return err; } =20 -static int __maybe_unused tegra_bpmp_resume(struct device *dev) +static int __maybe_unused tegra_bpmp_suspend(struct device *dev) { struct tegra_bpmp *bpmp =3D dev_get_drvdata(dev); =20 - if (bpmp->soc->ops->resume) - return bpmp->soc->ops->resume(bpmp); - else - return 0; + /* + * If the BPMP has a reset handler then mark as + * not ready until on entry to suspend. This flag + * is used to trigger the reset after resume. + */ + if (bpmp->soc->ops->reset) + bpmp->needs_reset =3D true; + + return 0; } =20 static const struct dev_pm_ops tegra_bpmp_pm_ops =3D { - .resume_noirq =3D tegra_bpmp_resume, + .suspend_noirq =3D tegra_bpmp_suspend, }; =20 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \ diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h index 5842e38bb288..932f7fd1edfb 100644 --- a/include/soc/tegra/bpmp.h +++ b/include/soc/tegra/bpmp.h @@ -102,6 +102,8 @@ struct tegra_bpmp { #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_mirror; #endif + + bool needs_reset; }; =20 struct tegra_bpmp_message { --=20 2.17.1