From nobody Fri Dec 19 17:33:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F795C83F17 for ; Wed, 30 Aug 2023 18:31:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235467AbjH3SbQ (ORCPT ); Wed, 30 Aug 2023 14:31:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243395AbjH3Kxx (ORCPT ); Wed, 30 Aug 2023 06:53:53 -0400 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AB8A198 for ; Wed, 30 Aug 2023 03:53:51 -0700 (PDT) Received: from pps.filterd (m0356516.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37UAlxh0004676; Wed, 30 Aug 2023 10:53:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=WZbNLZ6BUq5IR8IIqhAv0z7Wo4CfMYZ+rFojnZ7/+os=; b=hdAvZ3SqAic6r2Bub/SbndoCT+0TIrJo+crHG7Dc6qQPHA9VOta9M0lvzcuyFNF8eaVe x4VMkuRpETUsexKFSNqSBWxCC0jfCnQdYe/OS8/XAcYSxbqDphBd/IDtWHwHbf+1etiU JTFkPMuCLUep6p4lIylACFeuQ+jJLS0E5aSub2VhfAeoxE/X3gL4/a9cwRVijv0N1Rxi 3P+/vZ3Mc+b8d2eudpbu0J4wsjY7BNghQo+9DstdFuMoxOD9e30p+5rX2Nt+3Iicw33N b5NJGNbKrFoS04zNAnCB8D4eMcJbgxvw10AkEhbcMqniMemaMC8HmoSCsleOt7e7pIoe Qw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3st4aw0317-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Aug 2023 10:53:30 +0000 Received: from m0356516.ppops.net (m0356516.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37UAmBJv005329; Wed, 30 Aug 2023 10:53:30 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3st4aw030s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Aug 2023 10:53:30 +0000 Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 37UA6Ebp019258; Wed, 30 Aug 2023 10:53:29 GMT Received: from smtprelay07.fra02v.mail.ibm.com ([9.218.2.229]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 3sqxe1tnk2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Aug 2023 10:53:29 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay07.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 37UArR8e61407494 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 30 Aug 2023 10:53:27 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B75912004B; Wed, 30 Aug 2023 10:53:27 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B7CDE20043; Wed, 30 Aug 2023 10:53:23 +0000 (GMT) Received: from saptarishi.in.ibm.com (unknown [9.43.8.96]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 30 Aug 2023 10:53:23 +0000 (GMT) From: Srikar Dronamraju To: Michael Ellerman Cc: linuxppc-dev , Srikar Dronamraju , Juergen Gross , Nicholas Piggin , Christophe Leroy , Josh Poimboeuf , Peter Zijlstra , Paul E McKenney , Valentin Schneider , Nathan Lynch , virtualization@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] powerpc/smp: Cache CPU has Asymmetric SMP Date: Wed, 30 Aug 2023 16:22:41 +0530 Message-ID: <20230830105244.62477-2-srikar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230830105244.62477-1-srikar@linux.vnet.ibm.com> References: <20230830105244.62477-1-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: v-Ta_8zjOXq3bB_YeeXSJfwiY_AKl7H1 X-Proofpoint-ORIG-GUID: DSKCAnDHWcUMyqqvUffQ3ptz5Sb-bMzW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_16,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308300098 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently cpu feature flag is checked whenever powerpc_smt_flags gets called. This is an unnecessary overhead. CPU_FTR_ASYM_SMT is set based on the processor and all processors will either have this set or will have it unset. Hence only check for the feature flag once and cache it to be used subsequently. This commit will help avoid a branch in powerpc_smt_flags Signed-off-by: Srikar Dronamraju --- arch/powerpc/kernel/smp.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index fbbb695bae3d..c7d1484ed230 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -987,18 +987,13 @@ static int __init init_thread_group_cache_map(int cpu= , int cache_property) } =20 static bool shared_caches; +static int asym_pack_flag; =20 #ifdef CONFIG_SCHED_SMT /* cpumask of CPUs with asymmetric SMT dependency */ static int powerpc_smt_flags(void) { - int flags =3D SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; - - if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { - printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); - flags |=3D SD_ASYM_PACKING; - } - return flags; + return SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES | asym_pack_flag; } #endif =20 @@ -1676,6 +1671,11 @@ static void __init fixup_topology(void) { int i; =20 + if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { + printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); + asym_pack_flag =3D SD_ASYM_PACKING; + } + #ifdef CONFIG_SCHED_SMT if (has_big_cores) { pr_info("Big cores detected but using small core scheduling\n"); --=20 2.41.0