From nobody Fri Dec 19 15:59:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81962C83F19 for ; Tue, 29 Aug 2023 12:59:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235797AbjH2M6o (ORCPT ); Tue, 29 Aug 2023 08:58:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235687AbjH2M6G (ORCPT ); Tue, 29 Aug 2023 08:58:06 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1289BF for ; Tue, 29 Aug 2023 05:58:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693313883; x=1724849883; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QldM16VWt9sIxeALCKvfIhayNh8wAJ4+hob5Nr/kC4A=; b=HjFR5bc+UF6rzaSOPWwrgzWlzlvwSaZAx6gnP4SlCOZXN3F4u+KS2MGb fwb5FRkNoNlokwMOvEXBwaUzf1/f5nJSzEj1sQ1Wjkq2IhOAk42bZi1Qu +T2hzbRXKVOrgmTYUiajHIMAF9YBt+hmKyELpIfjugQmWlzoEtqWkrcdU zZg1twmyH+zsFcBzuYF+7Ff1xo6h1NClw2nATA+rtK/9dl5zaotv7NE3Z T3s8WD9WFsdtIfPjfGqrDu4eyKJn5WcwpVQLkDgmZINAbI8lD3/lW2PfH IryPHlD+/YjDo/rNQvU0uhsrrWwmkLy6R1z6tYdQ4YJ1ZXOB3wqPDIM8q g==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="406354912" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="406354912" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 05:58:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="853272014" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="853272014" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga002.fm.intel.com with ESMTP; 29 Aug 2023 05:58:03 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org Cc: dapeng1.mi@linux.intel.com, zhenyuw@linux.intel.com, Kan Liang Subject: [PATCH 2/6] perf/x86/intel: Factor out the initialization code for SPR Date: Tue, 29 Aug 2023 05:58:02 -0700 Message-Id: <20230829125806.3016082-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230829125806.3016082-1-kan.liang@linux.intel.com> References: <20230829125806.3016082-1-kan.liang@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kan Liang The SPR and ADL p-core have a similar uarch. Most of the initialization code can be shared. Factor out intel_pmu_init_glc() for the common initialization code. The common part of the ADL p-core will be replaced by the later patch. Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 49 +++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 6c98c272d4f8..e9e69401524a 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5909,6 +5909,30 @@ static __always_inline bool is_mtl(u8 x86_model) (x86_model =3D=3D INTEL_FAM6_METEORLAKE_L); } =20 +static __always_inline void intel_pmu_init_glc(struct pmu *pmu) +{ + x86_pmu.late_ack =3D true; + x86_pmu.limit_period =3D glc_limit_period; + x86_pmu.pebs_aliases =3D NULL; + x86_pmu.pebs_prec_dist =3D true; + x86_pmu.pebs_block =3D true; + x86_pmu.flags |=3D PMU_FL_HAS_RSP_1; + x86_pmu.flags |=3D PMU_FL_NO_HT_SHARING; + x86_pmu.flags |=3D PMU_FL_INSTR_LATENCY; + x86_pmu.rtm_abort_event =3D X86_CONFIG(.event=3D0xc9, .umask=3D0x04); + x86_pmu.lbr_pt_coexist =3D true; + x86_pmu.num_topdown_events =3D 8; + static_call_update(intel_pmu_update_topdown_event, + &icl_update_topdown_event); + static_call_update(intel_pmu_set_topdown_event_period, + &icl_set_topdown_event_period); + + memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeo= f(hw_cache_event_ids)); + memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, siz= eof(hw_cache_extra_regs)); + hybrid(pmu, event_constraints) =3D intel_glc_event_constraints; + hybrid(pmu, pebs_constraints) =3D intel_glc_pebs_event_constraints; +} + __init int intel_pmu_init(void) { struct attribute **extra_skl_attr =3D &empty_attrs; @@ -6560,24 +6584,10 @@ __init int intel_pmu_init(void) fallthrough; case INTEL_FAM6_GRANITERAPIDS_X: case INTEL_FAM6_GRANITERAPIDS_D: - pmem =3D true; - x86_pmu.late_ack =3D true; - memcpy(hw_cache_event_ids, glc_hw_cache_event_ids, sizeof(hw_cache_event= _ids)); - memcpy(hw_cache_extra_regs, glc_hw_cache_extra_regs, sizeof(hw_cache_ext= ra_regs)); - - x86_pmu.event_constraints =3D intel_glc_event_constraints; - x86_pmu.pebs_constraints =3D intel_glc_pebs_event_constraints; + intel_pmu_init_glc(NULL); if (!x86_pmu.extra_regs) x86_pmu.extra_regs =3D intel_rwc_extra_regs; - x86_pmu.limit_period =3D glc_limit_period; x86_pmu.pebs_ept =3D 1; - x86_pmu.pebs_aliases =3D NULL; - x86_pmu.pebs_prec_dist =3D true; - x86_pmu.pebs_block =3D true; - x86_pmu.flags |=3D PMU_FL_HAS_RSP_1; - x86_pmu.flags |=3D PMU_FL_NO_HT_SHARING; - x86_pmu.flags |=3D PMU_FL_INSTR_LATENCY; - x86_pmu.hw_config =3D hsw_hw_config; x86_pmu.get_event_constraints =3D glc_get_event_constraints; extra_attr =3D boot_cpu_has(X86_FEATURE_RTM) ? @@ -6586,14 +6596,7 @@ __init int intel_pmu_init(void) mem_attr =3D glc_events_attrs; td_attr =3D glc_td_events_attrs; tsx_attr =3D glc_tsx_events_attrs; - x86_pmu.rtm_abort_event =3D X86_CONFIG(.event=3D0xc9, .umask=3D0x04); - x86_pmu.lbr_pt_coexist =3D true; - intel_pmu_pebs_data_source_skl(pmem); - x86_pmu.num_topdown_events =3D 8; - static_call_update(intel_pmu_update_topdown_event, - &icl_update_topdown_event); - static_call_update(intel_pmu_set_topdown_event_period, - &icl_set_topdown_event_period); + intel_pmu_pebs_data_source_skl(true); pr_cont("Sapphire Rapids events, "); name =3D "sapphire_rapids"; break; --=20 2.35.1