From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7604FC83F2B for ; Mon, 28 Aug 2023 19:28:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233428AbjH1T2E (ORCPT ); Mon, 28 Aug 2023 15:28:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232262AbjH1T12 (ORCPT ); Mon, 28 Aug 2023 15:27:28 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26541CF2 for ; Mon, 28 Aug 2023 12:27:05 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-31ad779e6b3so2945313f8f.2 for ; Mon, 28 Aug 2023 12:27:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693250823; x=1693855623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wD/cr04vsZ/9/IOH8u0P4R4N+JejbyXPUXltlkLTn0E=; b=M1YCfAkjhG7d0Ax1dScy8AVLJXABarbwhC5Mlo0zc9Ew3M2VGhafoaNLCteOa/m3yD a51pY+t6Juattc/dWgCcW5nI0pvqguxlPp5FJ5vGaAgvMjH1KJoO9MGqXY1f0LbEVuI7 dJKjPfwyZAUduK1/So0X8teePZ51EJP1GYGb9KQA055/SgoaFN3Z3Q8eDsSODuQVesfi g0wRYh8KooCB5ZAbAUhIOIXfrHkPDuslgoYMfLAr3MefJGv3an8ZasW5fR8A78XVetVA euyZ0Es9Hjfyda8lIn2WMO4xWS1bmAZlTwxN+rxdnLC+ZZe9RX5vQ8mxd9qJ/kOV5sCJ rijw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693250823; x=1693855623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wD/cr04vsZ/9/IOH8u0P4R4N+JejbyXPUXltlkLTn0E=; b=lyNNHoG70JGkWQfBahuYnoEwyw6yql7EQG+x9J4lXo8F1QImjUgJekKbDqgHRpU6Ts +HiVn+CGjF/p3HnWVYD27p+j0/vP0stoXAfAJIH2LFW8KjOq44dIegnOZ7jR2HsQhUTh YF1fIwqhhXjH/UQrawOCaHFfLuopXKtGWu0S4jpjAQoKBQpOeTITqTDriaLR0ZPR+MVW HoS4U+LjqHtbG0ZyfnVVrhynQnj9Uq13MqFB8s8oMmPr+VYJYKmbX0i4AyUPMKFlFgoP Ctxl+RdDkuau3nDQyPGJL4vjMvWgWj+/7crjGwzz3jB36iutXPOjZrRYGO5uJd8+XXnN 9JLA== X-Gm-Message-State: AOJu0Ywa2hjPSArZz0HOSTyTpr71sHLRcJgTEmZeftvFssry4j8rhCVq e9uD0bqMQPrDyz71VzOUZC6bEQ== X-Google-Smtp-Source: AGHT+IG2DjUhqTBQfx117neGDoGHgAk3CElFSNDlYxMkA8BW06/aoRj0xIELzMxoR+5xz/rb1iL0LQ== X-Received: by 2002:adf:e4c9:0:b0:31a:dbd8:95d4 with SMTP id v9-20020adfe4c9000000b0031adbd895d4mr19219586wrm.12.1693250823568; Mon, 28 Aug 2023 12:27:03 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:8bd:7f16:d368:115f]) by smtp.gmail.com with ESMTPSA id i20-20020a5d5234000000b003141f96ed36sm11435319wra.0.2023.08.28.12.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 12:27:03 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 01/11] firmware: qcom-scm: drop unneeded 'extern' specifiers Date: Mon, 28 Aug 2023 21:24:57 +0200 Message-Id: <20230828192507.117334-2-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 'extern' specifier in front of a function declaration has no effect. Remove all of them from the qcom-scm header. Signed-off-by: Bartosz Golaszewski Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- include/linux/firmware/qcom/qcom_scm.h | 101 ++++++++++++------------- 1 file changed, 48 insertions(+), 53 deletions(-) diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index 250ea4efb7cb..0187fc54249e 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -59,12 +59,12 @@ enum qcom_scm_ice_cipher { #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE) #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC) =20 -extern bool qcom_scm_is_available(void); +bool qcom_scm_is_available(void); =20 -extern int qcom_scm_set_cold_boot_addr(void *entry); -extern int qcom_scm_set_warm_boot_addr(void *entry); -extern void qcom_scm_cpu_power_down(u32 flags); -extern int qcom_scm_set_remote_state(u32 state, u32 id); +int qcom_scm_set_cold_boot_addr(void *entry); +int qcom_scm_set_warm_boot_addr(void *entry); +void qcom_scm_cpu_power_down(u32 flags); +int qcom_scm_set_remote_state(u32 state, u32 id); =20 struct qcom_scm_pas_metadata { void *ptr; @@ -72,54 +72,49 @@ struct qcom_scm_pas_metadata { ssize_t size; }; =20 -extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, - size_t size, - struct qcom_scm_pas_metadata *ctx); +int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t s= ize, + struct qcom_scm_pas_metadata *ctx); void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); -extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, - phys_addr_t size); -extern int qcom_scm_pas_auth_and_reset(u32 peripheral); -extern int qcom_scm_pas_shutdown(u32 peripheral); -extern bool qcom_scm_pas_supported(u32 peripheral); - -extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); -extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); - -extern bool qcom_scm_restore_sec_cfg_available(void); -extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); -extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); -extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); -extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size); -extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, - u32 cp_nonpixel_start, - u32 cp_nonpixel_size); -extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, - u64 *src, - const struct qcom_scm_vmperm *newvm, - unsigned int dest_cnt); - -extern bool qcom_scm_ocmem_lock_available(void); -extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, - u32 size, u32 mode); -extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, - u32 size); - -extern bool qcom_scm_ice_available(void); -extern int qcom_scm_ice_invalidate_key(u32 index); -extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, - enum qcom_scm_ice_cipher cipher, - u32 data_unit_size); - -extern bool qcom_scm_hdcp_available(void); -extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, - u32 *resp); - -extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fm= t); -extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); - -extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload= _val, - u64 limit_node, u32 node_id, u64 version); -extern int qcom_scm_lmh_profile_change(u32 profile_id); -extern bool qcom_scm_lmh_dcvsh_available(void); +int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t s= ize); +int qcom_scm_pas_auth_and_reset(u32 peripheral); +int qcom_scm_pas_shutdown(u32 peripheral); +bool qcom_scm_pas_supported(u32 peripheral); + +int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); +int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); + +bool qcom_scm_restore_sec_cfg_available(void); +int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); +int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); +int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); +int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size); +int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, + u32 cp_nonpixel_start, + u32 cp_nonpixel_size); +int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, u64 *src, + const struct qcom_scm_vmperm *newvm, + unsigned int dest_cnt); + +bool qcom_scm_ocmem_lock_available(void); +int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, + u32 size, u32 mode); +int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 s= ize); + +bool qcom_scm_ice_available(void); +int qcom_scm_ice_invalidate_key(u32 index); +int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, + enum qcom_scm_ice_cipher cipher, + u32 data_unit_size); + +bool qcom_scm_hdcp_available(void); +int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *res= p); + +int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt); +int qcom_scm_qsmmu500_wait_safe_toggle(bool en); + +int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, + u64 limit_node, u32 node_id, u64 version); +int qcom_scm_lmh_profile_change(u32 profile_id); +bool qcom_scm_lmh_dcvsh_available(void); =20 #endif --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F9A0C83F18 for ; Mon, 28 Aug 2023 19:28:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233158AbjH1T15 (ORCPT ); Mon, 28 Aug 2023 15:27:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233219AbjH1T13 (ORCPT ); Mon, 28 Aug 2023 15:27:29 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A844CF9 for ; Mon, 28 Aug 2023 12:27:06 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-31c5a2e8501so3035324f8f.0 for ; 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charset="utf-8" For easier maintenance order the included headers in qcom_scm.c alphabetically. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski --- drivers/firmware/qcom_scm.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index fde33acd46b7..980fcfa20b9f 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -2,24 +2,25 @@ /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved. * Copyright (C) 2015 Linaro Ltd. */ -#include -#include -#include + +#include +#include #include #include -#include #include +#include +#include +#include #include +#include #include -#include -#include #include #include #include #include -#include +#include #include -#include +#include =20 #include "qcom_scm.h" =20 --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9B95C83F17 for ; Mon, 28 Aug 2023 19:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233480AbjH1T2M (ORCPT ); Mon, 28 Aug 2023 15:28:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233269AbjH1T1b (ORCPT ); Mon, 28 Aug 2023 15:27:31 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60D9ACD8 for ; Mon, 28 Aug 2023 12:27:07 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-401d2e11dacso1808535e9.0 for ; Mon, 28 Aug 2023 12:27:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693250826; x=1693855626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=713tM2MtTN06BKtmpTKPtHYKAypTeU06f4AnOlNhYD4=; b=CSqa+pEoDUW2H0ZlraiWwUc3xrWOrJ1YaHmkjhFa1p/azSB734HWr7cU7e+myIPnxY qDsDy9RJtc6PWOZi806K/E6XsRbqhVy78B/oFwKTyW+g05lo+dhP4G62hGqrlQ641ZRU P8VP6sbAPFh7XXebDCKtOJ70udNb6SwiNfDapAw4WM4QHiBs1L6MYTO4T/+WXxLsQzk0 zIDoQGuZovksV9kVbawJ4xMgU2RlWI4uFaqB0yceUpKqZgcbSbYm5R1v8e88gGNG0KjH a5g9KaWoA3XNQ1D9zdItbOL4waj9PwpuPKgLNZQMhF8maGHr7j0ai4dCzdIUHby5GJf2 Rccg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693250826; x=1693855626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=713tM2MtTN06BKtmpTKPtHYKAypTeU06f4AnOlNhYD4=; b=gTf1wAF/4WGenaCzv/ptfQgVaC2Tji+LUE5kE9D8rft0U4yh7gA+JbfpNarwZrGE1a jMCzZQ/kmkqpk1oR6w+SwE3Ih5rog6b+E/VrXIgCF6A0i4yvuFhjML1hvVD9sGY92jkP z9fwWYJQLoymrLsUf8r9y7TGiENscW9G92TLxy95awG9ylGZv8zxMJgKev2OgqfBtL1J Cskr+g4cmaAy0G1KE+GSVWtE0j9G9b+dzex3BYwUlimjF4rRQBlVht4MNvIvu9P8mXfL 8MHbKPs1r/YWVvH6DD7e7e2TxTlATr4MIVSosG5r7vOdRghDuTlc/+SBxKXc3t3dJO92 np2w== X-Gm-Message-State: AOJu0YzHIuWsXMFUsuIVfCiBwsoh+KaMTqoA6xL58yDYVpdTw94S2Zr7 kCs9ILsN/fQF55lVOS+lGQz9oQ== X-Google-Smtp-Source: AGHT+IFP03AKHAfr/hAQD0gGF3wtYUFTciEZ8PKvTMJRFIBUMmxXBs7iwRUVJNseZQVqoKpOwBLzaw== X-Received: by 2002:adf:e682:0:b0:319:8c99:989a with SMTP id r2-20020adfe682000000b003198c99989amr369735wrm.8.1693250825898; Mon, 28 Aug 2023 12:27:05 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:8bd:7f16:d368:115f]) by smtp.gmail.com with ESMTPSA id i20-20020a5d5234000000b003141f96ed36sm11435319wra.0.2023.08.28.12.27.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 12:27:05 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 03/11] firmware: qcom-scm: atomically assign and read the global __scm pointer Date: Mon, 28 Aug 2023 21:24:59 +0200 Message-Id: <20230828192507.117334-4-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Checking for the availability of SCM bridge can happen from any context. It's only by chance that we haven't run into concurrency issues but with the upcoming SHM Bridge driver that will be initiated at the same initcall level, we need to assure the assignment and readback of the __scm pointer is atomic. Signed-off-by: Bartosz Golaszewski --- drivers/firmware/qcom_scm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 980fcfa20b9f..422de70faff8 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1331,7 +1331,7 @@ static int qcom_scm_find_dload_address(struct device = *dev, u64 *addr) */ bool qcom_scm_is_available(void) { - return !!__scm; + return !!READ_ONCE(__scm); } EXPORT_SYMBOL(qcom_scm_is_available); =20 @@ -1477,8 +1477,8 @@ static int qcom_scm_probe(struct platform_device *pde= v) if (ret) return ret; =20 - __scm =3D scm; - __scm->dev =3D &pdev->dev; + scm->dev =3D &pdev->dev; + WRITE_ONCE(__scm, scm); =20 init_completion(&__scm->waitq_comp); =20 --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E949FC83F2C for ; Mon, 28 Aug 2023 19:28:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233448AbjH1T2H (ORCPT ); Mon, 28 Aug 2023 15:28:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233327AbjH1T1b (ORCPT ); Mon, 28 Aug 2023 15:27:31 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4E7FCDD for ; Mon, 28 Aug 2023 12:27:08 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-31adc5c899fso3201556f8f.2 for ; Mon, 28 Aug 2023 12:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693250827; x=1693855627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q9IIbmqeXUEZrQQd9nJYDsQR20cl+CEuhTdfBNfLqNk=; b=U2c+D7W/DluCXF1TF7FZqcriMIZUK3c7RhavvfomxvpcFpDf8yDsO+W/TNBct8qfUV gAJqZGyE7rdbDYxbl+y3xmAYAP1l257zDnWa04rZZMlTwQzTGJeeHwfTeAXpSFVA+AoO +7vOphBP2vq2jqyVzTaaKWpF7XaUvqQ1RG5GY3jK5npXW2NnI31oKQ6YbZoo2gpbUgE0 d+GkWEDpPGi15djFRVH1GJCygrAE9ylq89zKIvKuq3sEDbMUIHE7SvcIS94/xP15JIzb PTB1TS6WF8wDllBXS0UfrL0VF7d1YHoMz6RGHU+H7XThrSmFLeITvkAen7ZEQ2ERJtFI YmNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693250827; x=1693855627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q9IIbmqeXUEZrQQd9nJYDsQR20cl+CEuhTdfBNfLqNk=; b=b1X8BnFyx3VfIhLNQo1tUXk6esIQi5zuJt9c09GTvxovrBoqzj9bHO5Hq0lif5SEh7 BAXqFhf4LNWpkG5gXN25N8BzUV3GC8OzyAUsI2bS50fZdhqO6hDJfgtHtvzoP4BSreEc WVvVwpg4cD+0sVqpveoymaD/0ESZ0/7zby/5I6/f8TlwbHx0iBpUnTs9UhLhWKazbT+Z bziXZNMbHVnVyQHVFpOn8bIwcBLmxXB0Xw1JFOqFHa+NXVD5uJVNqw0A7VdaAETmESsn rD0u6DTrh2zz+InOWtxsdaYWZRZM+SDhxMexUyghiUcLoqE1flc6zw2IDjMcf1pl7rQ+ 2ilA== X-Gm-Message-State: AOJu0YwT4pS68mtmr83RQwlBXZCU/i+ukDn+9ASKKvcjYSQXIroBH2Yt /nKRKNXOrncoU+jWoibM/fPSgA== X-Google-Smtp-Source: AGHT+IGELnRw3OVm+F5lO+SlIxnQc7iifWQmxaW6b93Q/z2oVixC1dvmEOehQrkSCMkjDmlRE7oFiA== X-Received: by 2002:adf:ea10:0:b0:31a:ed75:75e9 with SMTP id q16-20020adfea10000000b0031aed7575e9mr20375035wrm.13.1693250827195; Mon, 28 Aug 2023 12:27:07 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:8bd:7f16:d368:115f]) by smtp.gmail.com with ESMTPSA id i20-20020a5d5234000000b003141f96ed36sm11435319wra.0.2023.08.28.12.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 12:27:06 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 04/11] firmware: qcom-scm: add support for SHM bridge operations Date: Mon, 28 Aug 2023 21:25:00 +0200 Message-Id: <20230828192507.117334-5-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add low-level primitives for enabling SHM bridge support, creating SHM bridge pools and testing the availability of SHM bridges to qcom-scm. We don't yet provide a way to destroy the bridges as the first user will not require it. Signed-off-by: Bartosz Golaszewski --- drivers/firmware/qcom_scm.c | 83 ++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 3 + include/linux/firmware/qcom/qcom_scm.h | 8 +++ 3 files changed, 94 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 422de70faff8..f45d5a424424 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -31,6 +31,8 @@ module_param(download_mode, bool, 0); #define SCM_HAS_IFACE_CLK BIT(1) #define SCM_HAS_BUS_CLK BIT(2) =20 +#define SCM_SHM_BRIDGE_NOTSUPP 4 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -45,6 +47,8 @@ struct qcom_scm { int scm_vote_count; =20 u64 dload_mode_addr; + + bool shm_bridge_enabled; }; =20 struct qcom_scm_current_perm_info { @@ -1248,6 +1252,85 @@ bool qcom_scm_lmh_dcvsh_available(void) } EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); =20 +bool qcom_scm_shm_bridge_available(void) +{ + if (!qcom_scm_is_available()) + return false; + + return READ_ONCE(__scm->shm_bridge_enabled); +} +EXPORT_SYMBOL_GPL(qcom_scm_shm_bridge_available); + +/* + * Must not be called unless qcom_scm_shm_bridge_available() returned true + * first. + */ +int qcom_scm_enable_shm_bridge(void) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_MP, + .cmd =3D QCOM_SCM_MP_SHM_BRIDGE_ENABLE, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + + struct qcom_scm_res res; + int ret; + + ret =3D qcom_scm_call(__scm->dev, &desc, &res); + if (!ret && !res.result[0]) + WRITE_ONCE(__scm->shm_bridge_enabled, true); + + if (res.result[0] =3D=3D SCM_SHM_BRIDGE_NOTSUPP) + ret =3D -EOPNOTSUPP; + + return ret ?: res.result[0]; +} +EXPORT_SYMBOL_GPL(qcom_scm_enable_shm_bridge); + +int qcom_scm_create_shm_bridge(struct device *dev, u64 pfn_and_ns_perm_fla= gs, + u64 ipfn_and_s_perm_flags, u64 size_and_flags, + u64 ns_vmids, u64 *handle) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_MP, + .cmd =3D QCOM_SCM_MP_SHM_BRDIGE_CREATE, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + + struct qcom_scm_res res; + int ret; + + desc.args[0] =3D pfn_and_ns_perm_flags; + desc.args[1] =3D ipfn_and_s_perm_flags; + desc.args[2] =3D size_and_flags; + desc.args[3] =3D ns_vmids; + + desc.arginfo =3D QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL, + QCOM_SCM_VAL, QCOM_SCM_VAL); + + ret =3D qcom_scm_call(dev ?: __scm->dev, &desc, &res); + + if (handle && !ret) + *handle =3D res.result[1]; + + return ret ?: res.result[0]; +} +EXPORT_SYMBOL_GPL(qcom_scm_create_shm_bridge); + +int qcom_scm_delete_shm_bridge(struct device *dev, u64 handle) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_MP, + .cmd =3D QCOM_SCM_MP_SHM_BRIDGE_DELETE, + .owner =3D ARM_SMCCC_OWNER_SIP, + .args[0] =3D handle, + .arginfo =3D QCOM_SCM_ARGS(1, QCOM_SCM_VAL), + }; + + return qcom_scm_call(dev ?: __scm->dev, &desc, NULL); +} +EXPORT_SYMBOL_GPL(qcom_scm_delete_shm_bridge); + int qcom_scm_lmh_profile_change(u32 profile_id) { struct qcom_scm_desc desc =3D { diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index e6e512bd57d1..44d60d06344b 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -111,6 +111,9 @@ extern int scm_legacy_call(struct device *dev, const st= ruct qcom_scm_desc *desc, #define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05 #define QCOM_SCM_MP_VIDEO_VAR 0x08 #define QCOM_SCM_MP_ASSIGN 0x16 +#define QCOM_SCM_MP_SHM_BRIDGE_ENABLE 0x1c +#define QCOM_SCM_MP_SHM_BRIDGE_DELETE 0x1d +#define QCOM_SCM_MP_SHM_BRDIGE_CREATE 0x1e =20 #define QCOM_SCM_SVC_OCMEM 0x0f #define QCOM_SCM_OCMEM_LOCK_CMD 0x01 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index 0187fc54249e..100770380d97 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -5,6 +5,7 @@ #ifndef __QCOM_SCM_H #define __QCOM_SCM_H =20 +#include #include #include #include @@ -117,4 +118,11 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg= , u32 payload_val, int qcom_scm_lmh_profile_change(u32 profile_id); bool qcom_scm_lmh_dcvsh_available(void); =20 +bool qcom_scm_shm_bridge_available(void); +int qcom_scm_enable_shm_bridge(void); +int qcom_scm_create_shm_bridge(struct device *dev, u64 pfn_and_ns_perm_fla= gs, + u64 ipfn_and_s_perm_flags, u64 size_and_flags, + u64 ns_vmids, u64 *handle); +int qcom_scm_delete_shm_bridge(struct device *dev, u64 handle); + #endif --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9FE5C83F18 for ; Mon, 28 Aug 2023 19:28:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233360AbjH1T2B (ORCPT ); Mon, 28 Aug 2023 15:28:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233344AbjH1T1b (ORCPT ); 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Mon, 28 Aug 2023 12:27:07 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 05/11] dt-bindings: document the Qualcomm TEE Shared Memory Bridge Date: Mon, 28 Aug 2023 21:25:01 +0200 Message-Id: <20230828192507.117334-6-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Device Tree bindings for Qualcomm TEE Shared Memory Brige - a mechanism that allows sharing memory buffers between trustzone and the kernel. Signed-off-by: Bartosz Golaszewski --- .../bindings/firmware/qcom,shm-bridge.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/qcom,shm-bri= dge.yaml diff --git a/Documentation/devicetree/bindings/firmware/qcom,shm-bridge.yam= l b/Documentation/devicetree/bindings/firmware/qcom,shm-bridge.yaml new file mode 100644 index 000000000000..f660962b7b86 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/qcom,shm-bridge.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/qcom,shm-bridge.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM Shared Memory Bridge + +description: | + Qualcomm TEE Shared Memory Bridge allows sharing limited areas of kernel= 's + virtual memory with the trustzone in order to avoid mapping the entire R= AM. + +maintainers: + - Bjorn Andersson + - Konrad Dybcio + - Bartosz Golaszewski + +properties: + compatible: + items: + - enum: + - qcom,shm-bridge-sa8775p + - qcom,shm-bridge-sm8150 + - qcom,shm-bridge-sm8450 + - const: qcom,shm-bridge + +required: + - compatible + +additionalProperties: false + +examples: + - | + firmware { + compatible =3D "qcom,shm-bridge-sa8775p", "qcom,shm-bridge"; + }; --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEA9AC83F2D for ; Mon, 28 Aug 2023 19:28:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233454AbjH1T2J (ORCPT ); Mon, 28 Aug 2023 15:28:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233372AbjH1T1d (ORCPT ); Mon, 28 Aug 2023 15:27:33 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B950131 for ; Mon, 28 Aug 2023 12:27:11 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3fee87dd251so33584415e9.2 for ; Mon, 28 Aug 2023 12:27:11 -0700 (PDT) DKIM-Signature: v=1; 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Mon, 28 Aug 2023 12:27:09 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:8bd:7f16:d368:115f]) by smtp.gmail.com with ESMTPSA id i20-20020a5d5234000000b003141f96ed36sm11435319wra.0.2023.08.28.12.27.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 12:27:09 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 06/11] firmware: qcom-shm-bridge: new driver Date: Mon, 28 Aug 2023 21:25:02 +0200 Message-Id: <20230828192507.117334-7-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This module is a platform driver that also exposes an interface for kernel users to allocate blocks of memory shared with the trustzone. Signed-off-by: Bartosz Golaszewski --- drivers/firmware/Kconfig | 8 + drivers/firmware/Makefile | 1 + drivers/firmware/qcom-shm-bridge.c | 452 +++++++++++++++++++++++ include/linux/firmware/qcom/shm-bridge.h | 32 ++ 4 files changed, 493 insertions(+) create mode 100644 drivers/firmware/qcom-shm-bridge.c create mode 100644 include/linux/firmware/qcom/shm-bridge.h diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index b59e3041fd62..39f35ba18779 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -226,6 +226,14 @@ config QCOM_SCM_DOWNLOAD_MODE_DEFAULT =20 Say Y here to enable "download mode" by default. =20 +config QCOM_SHM_BRIDGE + bool "Qualcomm SHM bridge driver" + depends on QCOM_SCM + help + Say yes here to enable support for Qualcomm TEE Shared Memory Bridge. + This module exposes interfaces that allow kernel users to allocate + blocks of memory shared with the trustzone. + config SYSFB bool select BOOT_VESA_SUPPORT diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 28fcddcd688f..ba1590cf959c 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_RASPBERRYPI_FIRMWARE) +=3D raspberrypi.o obj-$(CONFIG_FW_CFG_SYSFS) +=3D qemu_fw_cfg.o obj-$(CONFIG_QCOM_SCM) +=3D qcom-scm.o qcom-scm-objs +=3D qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o +obj-$(CONFIG_QCOM_SHM_BRIDGE) +=3D qcom-shm-bridge.o obj-$(CONFIG_SYSFB) +=3D sysfb.o obj-$(CONFIG_SYSFB_SIMPLEFB) +=3D sysfb_simplefb.o obj-$(CONFIG_TI_SCI_PROTOCOL) +=3D ti_sci.o diff --git a/drivers/firmware/qcom-shm-bridge.c b/drivers/firmware/qcom-shm= -bridge.c new file mode 100644 index 000000000000..db76c5c5061d --- /dev/null +++ b/drivers/firmware/qcom-shm-bridge.c @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define QCOM_SHM_BRIDGE_NUM_VM_SHIFT 9 + +DEFINE_FREE(qcom_shm_bridge_pool, struct qcom_shm_bridge_pool *, + if (_T) qcom_shm_bridge_pool_unref(_T)) + +/* + * Size of the global fall-back pool can be adjusted using this param. Use= 4M + * as a sane default. + */ +static unsigned int qcom_shm_bridge_default_pool_size =3D SZ_4M; +module_param_named(default_pool_size, qcom_shm_bridge_default_pool_size, + uint, 0644); + +struct qcom_shm_bridge_pool { + struct device *dev; + void *vaddr; + phys_addr_t paddr; + size_t size; + uint64_t handle; + struct gen_pool *genpool; + struct list_head chunks; + spinlock_t lock; + struct kref refcount; +}; + +struct qcom_shm_bridge_chunk { + void *vaddr; + size_t size; + struct qcom_shm_bridge_pool *parent; + struct list_head siblings; +}; + +/* This is the global fall-back pool, used if user doesn't supply their ow= n. */ +static struct qcom_shm_bridge_pool *qcom_shm_bridge_default_pool; + +static RADIX_TREE(qcom_shm_bridge_chunks, GFP_ATOMIC); +static DEFINE_SPINLOCK(qcom_shm_bridge_chunks_lock); + +static void qcom_shm_bridge_pool_release(struct kref *kref) +{ + struct qcom_shm_bridge_pool *pool =3D + container_of(kref, struct qcom_shm_bridge_pool, refcount); + + if (pool->handle) + qcom_scm_delete_shm_bridge(pool->dev, pool->handle); + + if (pool->genpool) + gen_pool_destroy(pool->genpool); + + if (pool->paddr) + dma_unmap_single(pool->dev, pool->paddr, pool->size, + DMA_TO_DEVICE); + + if (pool->vaddr) + free_pages((unsigned long)pool->vaddr, get_order(pool->size)); + + put_device(pool->dev); + kfree(pool); +} + +static int qcom_shm_bridge_create(struct qcom_shm_bridge_pool *pool) +{ + uint64_t pfn_and_ns_perm, ipfn_and_s_perm, size_and_flags, ns_vmids, + ns_perms, handle; + int ret; + + ns_perms =3D (QCOM_SCM_PERM_WRITE | QCOM_SCM_PERM_READ); + ns_vmids =3D QCOM_SCM_VMID_HLOS; + pfn_and_ns_perm =3D (u64)pool->paddr | ns_perms; + ipfn_and_s_perm =3D (u64)pool->paddr | ns_perms; + size_and_flags =3D pool->size | (1 << QCOM_SHM_BRIDGE_NUM_VM_SHIFT); + + ret =3D qcom_scm_create_shm_bridge(pool->dev, pfn_and_ns_perm, + ipfn_and_s_perm, size_and_flags, + ns_vmids, &handle); + if (!ret) + pool->handle =3D handle; + + return ret; +} + +static struct qcom_shm_bridge_pool * +qcom_shm_bridge_pool_new_for_dev(struct device *dev, size_t size) +{ + struct qcom_shm_bridge_pool *pool __free(qcom_shm_bridge_pool) =3D NULL; + int ret; + + if (!qcom_scm_shm_bridge_available()) + return ERR_PTR(-ENODEV); + + if (!size) + return ERR_PTR(-EINVAL); + + pool =3D kzalloc(sizeof(*pool), GFP_KERNEL); + if (!pool) + return ERR_PTR(-ENOMEM); + + pool->dev =3D get_device(dev); + pool->size =3D size; + INIT_LIST_HEAD(&pool->chunks); + spin_lock_init(&pool->lock); + kref_init(&pool->refcount); + + pool->vaddr =3D (void *)__get_free_pages(GFP_KERNEL | GFP_DMA, + get_order(pool->size)); + if (!pool->vaddr) + return ERR_PTR(-ENOMEM); + + pool->paddr =3D dma_map_single(pool->dev, pool->vaddr, pool->size, + DMA_TO_DEVICE); + if (dma_mapping_error(dev, pool->paddr)) + return ERR_PTR(-ENOMEM); + + pool->genpool =3D gen_pool_create(PAGE_SHIFT, -1); + if (!pool->genpool) + return ERR_PTR(-ENOMEM); + + gen_pool_set_algo(pool->genpool, gen_pool_best_fit, NULL); + + ret =3D gen_pool_add_virt(pool->genpool, (unsigned long)pool->vaddr, + pool->paddr, pool->size, -1); + if (ret) + return ERR_PTR(ret); + + ret =3D qcom_shm_bridge_create(pool); + if (ret) + return ERR_PTR(ret); + + return no_free_ptr(pool); +} + +/** + * qcom_shm_bridge_pool_new - Create a new SHM Bridge memory pool. + * + * @size: Size of the pool. + * + * Creates a new Shared Memory Bridge pool from which users can allocate m= emory + * chunks. Must be called from process context. + * + * Return: + * Pointer to the newly created SHM Bridge pool with reference count set t= o 1 + * or ERR_PTR(). + */ +struct qcom_shm_bridge_pool *qcom_shm_bridge_pool_new(size_t size) +{ + struct device *dev; + + dev =3D bus_find_device_by_name(&platform_bus_type, NULL, + "qcom-shm-bridge"); + if (!dev) + return ERR_PTR(-ENODEV); + + return qcom_shm_bridge_pool_new_for_dev(dev, size); +} +EXPORT_SYMBOL_GPL(qcom_shm_bridge_pool_new); + +/** + * qcom_shm_bridge_pool_ref - Increate the refcount of an SHM Bridge pool. + * + * @pool: SHM Bridge pool of which the reference count to increase. + * + * Return: + * Pointer to the same pool object. + */ +struct qcom_shm_bridge_pool * +qcom_shm_bridge_pool_ref(struct qcom_shm_bridge_pool *pool) +{ + kref_get(&pool->refcount); + + return pool; +} +EXPORT_SYMBOL_GPL(qcom_shm_bridge_pool_ref); + +/** + * qcom_shm_bridge_pool_unref - Decrease the refcount of an SHM Bridge poo= l. + * + * @pool: SHM Bridge pool of which the reference count to decrease. + * + * Once the reference count reaches 0, the pool is released. + */ +void qcom_shm_bridge_pool_unref(struct qcom_shm_bridge_pool *pool) +{ + kref_put(&pool->refcount, qcom_shm_bridge_pool_release); +} +EXPORT_SYMBOL_GPL(qcom_shm_bridge_pool_unref); + +static void devm_qcom_shm_bridge_pool_unref(void *data) +{ + struct qcom_shm_bridge_pool *pool =3D data; + + qcom_shm_bridge_pool_unref(pool); +} + +/** + * devm_qcom_shm_bridge_pool_new - Managed variant of qcom_shm_bridge_pool= _new. + * + * @dev: Device for which to map memory and which will manage this pool. + * @size: Size of the pool. + * + * Return: + * Pointer to the newly created SHM Bridge pool with reference count set t= o 1 + * or ERR_PTR(). + */ +struct qcom_shm_bridge_pool * +devm_qcom_shm_bridge_pool_new(struct device *dev, size_t size) +{ + struct qcom_shm_bridge_pool *pool; + int ret; + + pool =3D qcom_shm_bridge_pool_new(size); + if (IS_ERR(pool)) + return pool; + + ret =3D devm_add_action_or_reset(dev, devm_qcom_shm_bridge_pool_unref, + pool); + if (ret) + return ERR_PTR(ret); + + return pool; +} +EXPORT_SYMBOL_GPL(devm_qcom_shm_bridge_pool_new); + +/** + * qcom_shm_bridge_alloc - Allocate a chunk of memory from an SHM Bridge p= ool. + * + * @pool: Pool to allocate memory from. May be NULL. + * @size: Number of bytes to allocate. + * @gfp: Allocation flags. + * + * If pool is NULL then the global fall-back pool is used. + * + * Return: + * Virtual address of the allocated memory or ERR_PTR(). Must be freed usi= ng + * qcom_shm_bridge_free(). + */ +void *qcom_shm_bridge_alloc(struct qcom_shm_bridge_pool *pool, + size_t size, gfp_t gfp) +{ + struct qcom_shm_bridge_chunk *chunk __free(kfree) =3D NULL; + unsigned long vaddr; + int ret; + + if (!pool) { + pool =3D READ_ONCE(qcom_shm_bridge_default_pool); + if (!pool) + return ERR_PTR(-ENODEV); + } + + if (!size || size > pool->size) + return ERR_PTR(-EINVAL); + + size =3D roundup(size, 1 << PAGE_SHIFT); + + chunk =3D kzalloc(sizeof(*chunk), gfp); + if (!chunk) + return ERR_PTR(-ENOMEM); + + guard(spinlock_irqsave)(&pool->lock); + + vaddr =3D gen_pool_alloc(pool->genpool, size); + if (!vaddr) + return ERR_PTR(-ENOMEM); + + chunk->vaddr =3D (void *)vaddr; + chunk->size =3D size; + chunk->parent =3D pool; + list_add_tail(&chunk->siblings, &pool->chunks); + qcom_shm_bridge_pool_ref(pool); + + guard(spinlock_irqsave)(&qcom_shm_bridge_chunks_lock); + + ret =3D radix_tree_insert(&qcom_shm_bridge_chunks, vaddr, chunk); + if (ret) { + gen_pool_free(pool->genpool, vaddr, chunk->size); + return ERR_PTR(ret); + } + + return no_free_ptr(chunk)->vaddr; +} +EXPORT_SYMBOL_GPL(qcom_shm_bridge_alloc); + +/** + * qcom_shm_bridge_free - Free SHM Bridge memory allocated from the pool. + * + * @vaddr: Virtual address of the allocated memory to free. + */ +void qcom_shm_bridge_free(void *vaddr) +{ + struct qcom_shm_bridge_chunk *chunk; + struct qcom_shm_bridge_pool *pool; + + scoped_guard(spinlock_irqsave, &qcom_shm_bridge_chunks_lock) + chunk =3D radix_tree_delete_item(&qcom_shm_bridge_chunks, + (unsigned long)vaddr, NULL); + if (!chunk) + goto out_warn; + + pool =3D chunk->parent; + + guard(spinlock_irqsave)(&pool->lock); + + list_for_each_entry(chunk, &pool->chunks, siblings) { + if (vaddr !=3D chunk->vaddr) + continue; + + gen_pool_free(pool->genpool, (unsigned long)chunk->vaddr, + chunk->size); + list_del(&chunk->siblings); + qcom_shm_bridge_pool_unref(pool); + kfree(chunk); + return; + } + +out_warn: + WARN(1, "Virtual address %p not allocated for SHM bridge", vaddr); +} +EXPORT_SYMBOL_GPL(qcom_shm_bridge_free); + +/** + * devm_qcom_shm_bridge_alloc - Managed variant of qcom_shm_bridge_alloc. + * + * @dev: Managing device. + * @pool: Pool to allocate memory from. + * @size: Number of bytes to allocate. + * @gfp: Allocation flags. + * + * Return: + * Virtual address of the allocated memory or ERR_PTR(). + */ +void *devm_qcom_shm_bridge_alloc(struct device *dev, + struct qcom_shm_bridge_pool *pool, + size_t size, gfp_t gfp) +{ + void *vaddr; + int ret; + + vaddr =3D qcom_shm_bridge_alloc(pool, size, gfp); + if (IS_ERR(vaddr)) + return vaddr; + + ret =3D devm_add_action_or_reset(dev, qcom_shm_bridge_free, vaddr); + if (ret) + return ERR_PTR(ret); + + return vaddr; +} +EXPORT_SYMBOL_GPL(devm_qcom_shm_bridge_alloc); + +/** + * qcom_shm_bridge_to_phys_addr - Translate address from virtual to physic= al. + * + * @vaddr: Virtual address to translate. + * + * Return: + * Physical address corresponding to 'vaddr'. + */ +phys_addr_t qcom_shm_bridge_to_phys_addr(void *vaddr) +{ + struct qcom_shm_bridge_chunk *chunk; + struct qcom_shm_bridge_pool *pool; + + guard(spinlock_irqsave)(&qcom_shm_bridge_chunks_lock); + + chunk =3D radix_tree_lookup(&qcom_shm_bridge_chunks, + (unsigned long)vaddr); + if (!chunk) + return 0; + + pool =3D chunk->parent; + + guard(spinlock_irqsave)(&pool->lock); + + return gen_pool_virt_to_phys(pool->genpool, (unsigned long)vaddr); +} +EXPORT_SYMBOL_GPL(qcom_shm_bridge_to_phys_addr); + +static int qcom_shm_bridge_probe(struct platform_device *pdev) +{ + struct qcom_shm_bridge_pool *default_pool; + struct device *dev =3D &pdev->dev; + int ret; + + /* + * We need to wait for the SCM device to be created and bound to the + * SCM driver. + */ + if (!qcom_scm_is_available()) + return -EPROBE_DEFER; + + ret =3D qcom_scm_enable_shm_bridge(); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable the SHM bridge\n"); + + default_pool =3D qcom_shm_bridge_pool_new_for_dev( + dev, qcom_shm_bridge_default_pool_size); + if (IS_ERR(default_pool)) + return dev_err_probe(dev, PTR_ERR(default_pool), + "Failed to create the default SHM Bridge pool\n"); + + WRITE_ONCE(qcom_shm_bridge_default_pool, default_pool); + + return 0; +} + +static const struct of_device_id qcom_shm_bridge_of_match[] =3D { + { .compatible =3D "qcom,shm-bridge", }, + { } +}; + +static struct platform_driver qcom_shm_bridge_driver =3D { + .driver =3D { + .name =3D "qcom-shm-bridge", + .of_match_table =3D qcom_shm_bridge_of_match, + /* + * Once enabled, the SHM Bridge feature cannot be disabled so + * there's no reason to ever unbind the driver. + */ + .suppress_bind_attrs =3D true, + }, + .probe =3D qcom_shm_bridge_probe, +}; + +static int __init qcom_shm_bridge_init(void) +{ + return platform_driver_register(&qcom_shm_bridge_driver); +} +subsys_initcall(qcom_shm_bridge_init); diff --git a/include/linux/firmware/qcom/shm-bridge.h b/include/linux/firmw= are/qcom/shm-bridge.h new file mode 100644 index 000000000000..df066a2f6d91 --- /dev/null +++ b/include/linux/firmware/qcom/shm-bridge.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Linaro Limited + */ + +#ifndef _LINUX_QCOM_SHM_BRIDGE +#define _LINUX_QCOM_SHM_BRIDGE + +#include +#include +#include +#include + +struct qcom_shm_bridge_pool; + +struct qcom_shm_bridge_pool *qcom_shm_bridge_pool_new(size_t size); +struct qcom_shm_bridge_pool * +qcom_shm_bridge_pool_ref(struct qcom_shm_bridge_pool *pool); +void qcom_shm_bridge_pool_unref(struct qcom_shm_bridge_pool *pool); +struct qcom_shm_bridge_pool * +devm_qcom_shm_bridge_pool_new(struct device *dev, size_t size); + +void *qcom_shm_bridge_alloc(struct qcom_shm_bridge_pool *pool, + size_t size, gfp_t gfp); +void qcom_shm_bridge_free(void *vaddr); +void *devm_qcom_shm_bridge_alloc(struct device *dev, + struct qcom_shm_bridge_pool *pool, + size_t size, gfp_t gfp); + +phys_addr_t qcom_shm_bridge_to_phys_addr(void *vaddr); + +#endif /* _LINUX_QCOM_SHM_BRIDGE */ --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F1B6C83F1E for ; Mon, 28 Aug 2023 19:28:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233277AbjH1T17 (ORCPT ); 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Mon, 28 Aug 2023 12:27:10 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 07/11] firmware: qcom-scm: use SHM bridge if available Date: Mon, 28 Aug 2023 21:25:03 +0200 Message-Id: <20230828192507.117334-8-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allocate the memory for SCM call arguments from the Shared Memory Bridge if it's available. Signed-off-by: Bartosz Golaszewski --- drivers/firmware/qcom_scm-smc.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/qcom_scm-smc.c b/drivers/firmware/qcom_scm-sm= c.c index 16cf88acfa8e..6045be600c2a 100644 --- a/drivers/firmware/qcom_scm-smc.c +++ b/drivers/firmware/qcom_scm-smc.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include "qcom_scm.h" =20 @@ -161,6 +162,7 @@ int __scm_smc_call(struct device *dev, const struct qco= m_scm_desc *desc, ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64; struct arm_smccc_res smc_res; struct arm_smccc_args smc =3D {0}; + bool using_shm_bridge =3D qcom_scm_shm_bridge_available(); =20 smc.args[0] =3D ARM_SMCCC_CALL_VAL( smccc_call_type, @@ -173,8 +175,12 @@ int __scm_smc_call(struct device *dev, const struct qc= om_scm_desc *desc, =20 if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) { alloc_len =3D SCM_SMC_N_EXT_ARGS * sizeof(u64); - args_virt =3D kzalloc(PAGE_ALIGN(alloc_len), flag); - + if (using_shm_bridge) + args_virt =3D qcom_shm_bridge_alloc(NULL, + PAGE_ALIGN(alloc_len), + flag); + else + args_virt =3D kzalloc(PAGE_ALIGN(alloc_len), flag); if (!args_virt) return -ENOMEM; =20 @@ -196,7 +202,10 @@ int __scm_smc_call(struct device *dev, const struct qc= om_scm_desc *desc, DMA_TO_DEVICE); =20 if (dma_mapping_error(dev, args_phys)) { - kfree(args_virt); + if (using_shm_bridge) + qcom_shm_bridge_free(args_virt); + else + kfree(args_virt); return -ENOMEM; } =20 @@ -208,7 +217,10 @@ int __scm_smc_call(struct device *dev, const struct qc= om_scm_desc *desc, =20 if (args_virt) { dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE); - kfree(args_virt); + if (using_shm_bridge) + qcom_shm_bridge_free(args_virt); + else + kfree(args_virt); } =20 if (ret) --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDD1CC83F2E for ; Mon, 28 Aug 2023 19:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233485AbjH1T2O (ORCPT ); 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Mon, 28 Aug 2023 12:27:11 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 08/11] arm64: defconfig: enable Qualcomm SHM bridge module Date: Mon, 28 Aug 2023 21:25:04 +0200 Message-Id: <20230828192507.117334-9-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Most Qualcomm architectures support SHM bridge. Enable it as a built-in module in arm64 defconfig. Signed-off-by: Bartosz Golaszewski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a25d783dfb95..7f982d9966e3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -248,6 +248,7 @@ CONFIG_ARM_SCPI_PROTOCOL=3Dy CONFIG_RASPBERRYPI_FIRMWARE=3Dy CONFIG_INTEL_STRATIX10_SERVICE=3Dy CONFIG_INTEL_STRATIX10_RSU=3Dm +CONFIG_QCOM_SHM_BRIDGE=3Dy CONFIG_EFI_CAPSULE_LOADER=3Dy CONFIG_IMX_SCU=3Dy CONFIG_IMX_SCU_PD=3Dy --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07DF8C83F25 for ; Mon, 28 Aug 2023 19:28:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233427AbjH1T2C (ORCPT ); Mon, 28 Aug 2023 15:28:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233396AbjH1T1e (ORCPT ); Mon, 28 Aug 2023 15:27:34 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFAAB1A4 for ; Mon, 28 Aug 2023 12:27:14 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3ff1c397405so34790035e9.3 for ; Mon, 28 Aug 2023 12:27:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693250833; x=1693855633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BAFaAAYoXtYBwsZEB5803CfYwT2H5kOVyLG4imLw9Ng=; b=sbvAYBnYvMtQ5zHvNb+ucyUQxsfswVBcZM/ar2F0dRfS4ewDAUJjw03AVtS1PWnf/G cqu+nYSS1d4AXk2m0hv8+daSi8iZwzboeUAqMjANlPobyJ4Ql3UmF0YL32U3XIiFpyA8 1DIW9fQFJ5Ip/1DW8HInCGLwdtV4tkc7IRqHHz6jtRn3J21+kMY4qQm/ggf61IbB6uPl oVX11YhXXQLkqHs7C5sR4eZEYLCZMXwEv/mW4idSCkyic1oUUc/H8kIO/YY4dw+mKkah Cs9YlbV6RRiwIYMsXxTH5lNlOFWngcE9JgNT68DaeWEY1CNd2XFQW+FNQxmWbmelwyTK E/IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693250833; x=1693855633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BAFaAAYoXtYBwsZEB5803CfYwT2H5kOVyLG4imLw9Ng=; b=ljzDZzL1K9rZL15M3q1RCqif74l2jk52gSdaGdlQRms5ccGqTFfUXgZ2VD2HCUI5xu cAVeibRg4UaZcEU66qF4gxCMNi8rOMzT+DLDHvNswWk/YWskVreMQloBHrN4gYV166fo Epa19P1tgh+r24YurxuDiut+OFdMcj9YohEi9lsERqlPkpTVY9ufN3Xlb4Gfc6nGvs5P CAd+p2SsdOL82vtAvrlasjOK4CIg5WeAOoYweMzSo49rND3Eg/kKWYtU8VhIOOkU4zSz WIfpdv115QaoJNsttxV1Ff7pu480bFFv/2B6TS5JvLTN9U1HH1iKyqc9KiaugcJnrmA+ ZMMw== X-Gm-Message-State: AOJu0Yx3xZzweYt75Pj/IVtDb1Iaa3GJGk9YwIGXQ9p7y/u0uh+xkrKX bBau3t5glBXWEN+H88JgN2SQrg== X-Google-Smtp-Source: AGHT+IERZ8Tk7ITAPI5IRbPu9geaRPRqJ6/1sXAiQvTPNpFfS2XTgFIfNp/PGkXNe/7dmFA1ZZGAcg== X-Received: by 2002:a1c:7908:0:b0:3fe:22a9:907 with SMTP id l8-20020a1c7908000000b003fe22a90907mr19589642wme.20.1693250833266; Mon, 28 Aug 2023 12:27:13 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:8bd:7f16:d368:115f]) by smtp.gmail.com with ESMTPSA id i20-20020a5d5234000000b003141f96ed36sm11435319wra.0.2023.08.28.12.27.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 12:27:12 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 09/11] arm64: dts: qcom: sm8450: enable SHM bridge Date: Mon, 28 Aug 2023 21:25:05 +0200 Message-Id: <20230828192507.117334-10-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable SHM bridge on sm8450 platforms. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 5cd7296c7660..eacb2658e3ec 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -289,6 +289,10 @@ scm: scm { interconnects =3D <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; #reset-cells =3D <1>; }; + + shm-bridge { + compatible =3D "qcom,shm-bridge-sm8450", "qcom,shm-bridge"; + }; }; =20 clk_virt: interconnect-0 { --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC4FEC83F19 for ; Mon, 28 Aug 2023 19:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233495AbjH1T2Q (ORCPT ); Mon, 28 Aug 2023 15:28:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233420AbjH1T1e (ORCPT ); Mon, 28 Aug 2023 15:27:34 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1171A1AD for ; Mon, 28 Aug 2023 12:27:16 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-31768ce2e81so2980696f8f.1 for ; Mon, 28 Aug 2023 12:27:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693250834; x=1693855634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LCx6rX9XwkuTbZO5oGRhSEBk5e7OaZJRubi6F2ucuO0=; b=kbalgKaBhIdUuKiRYkEoB9PjGYYgWzArZwbNwkwnDpDl2p8QWr0ZHt7WAyE7J9OEVS qOKK+GJCEwqq7V8OTL4qtinpwf74jAJjquHEn6PNN4/WJQxRpQDVmu+fRkkZG9JqCpkZ whLI1B+OhxOabfnsiYrTZPyZaVOdcl2qknkH0MfRSHE7+KHqdC8U9WmWLdNm7HDU02Ov 0bvmWDhy9DMP6lq7X2xzwiPm4Vr9MBkhtIsj3Uu2Qb4ko8nk3PTXPSW/falJDJRPq/Cl 3ud4CiLp3RUSsy9QVbIkVoFL5gMf6QdBrna+VPjN+RpVQnivOz/0mAw4PnlbRy04IAVV 5YmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693250834; x=1693855634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LCx6rX9XwkuTbZO5oGRhSEBk5e7OaZJRubi6F2ucuO0=; b=B6x5t9YL/FkcRDHSGCjimPOj4Irn1rNG9AMXcFpFIxRLdZxsP+hVQoYn4X99+XNza5 F5eyw0O9kkab4wLYq1V8gbZjtU/IVq8X+4qArfSoJ+iiXRniTowoz71YIn9N/Lcv0Jh5 l61p3F1EbazAG63hejmEJWEfseylC2F6MNZJdLTju5H4OuMT0kYD6odeipR5TDzY6VAN Je35RoBlEh+qPvav6ydBp54soNDnYkYCFiVUuzw16PzXEaOUmCV1WHdoRkb8mpKEOTTm Ga5CmJ5GclMdDCIiT1yUsIhdAC/q6iQxlKTT1So+qncKvIBf2ng2bggofB++AoUCPwus eykw== X-Gm-Message-State: AOJu0YzU2qbOUj2w6OvIXzG0Az3L7yL3vcnKfm0qABCFAZgSuObHsG/O ptq1xIxVPHB1t8y9d1zQQx6cbA== X-Google-Smtp-Source: AGHT+IGonPCG2HR4mwHMevXIU/ybI7JuPnQYVr3ZJNLHR2Fi7PQuFZCK98LCZMFUwA5tvpeKIA0xJA== X-Received: by 2002:adf:ef91:0:b0:318:f7a:e3c8 with SMTP id d17-20020adfef91000000b003180f7ae3c8mr20535179wro.57.1693250834586; Mon, 28 Aug 2023 12:27:14 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:8bd:7f16:d368:115f]) by smtp.gmail.com with ESMTPSA id i20-20020a5d5234000000b003141f96ed36sm11435319wra.0.2023.08.28.12.27.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 12:27:14 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 10/11] arm64: dts: qcom: sa8775p: enable SHM bridge Date: Mon, 28 Aug 2023 21:25:06 +0200 Message-Id: <20230828192507.117334-11-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable SHM bridge on sa8775p platforms. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index b130136acffe..d8614d15750e 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -209,6 +209,10 @@ firmware { scm { compatible =3D "qcom,scm-sa8775p", "qcom,scm"; }; + + shm-bridge { + compatible =3D "qcom,shm-bridge-sa8775p", "qcom,shm-bridge"; + }; }; =20 aggre1_noc: interconnect-aggre1-noc { --=20 2.39.2 From nobody Fri Dec 19 12:45:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76926C83F15 for ; Mon, 28 Aug 2023 19:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233466AbjH1T2K (ORCPT ); Mon, 28 Aug 2023 15:28:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233429AbjH1T1e (ORCPT ); Mon, 28 Aug 2023 15:27:34 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FE301B5 for ; Mon, 28 Aug 2023 12:27:17 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-31ad779e6b3so2945441f8f.2 for ; Mon, 28 Aug 2023 12:27:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693250835; x=1693855635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TMIOWWSdqeSoUAfHcjIOH1OC+hMNlEb1paPS+tEaJKg=; b=BCjoeEUS/FckunA7BjsPbj5RT/CgPggSegR9WzbBOoQWtgPXY39sFmaEIE9kfJhJ7j 2zROPjmvS+BGD9EvL5JgTngaatkJ3F77HlSYV6kxCn815OjUP+eP/AO73EyxCRErLTZw G3Mi/2pk0RCWlfDwldSJ/CEtiWSI5MZlNnrrmGibUrL8AyZYetCatMIdEPMu2i9Zpy/H mJ+EPJm4AnLYht0y9tLr/SC1ChgtsaM/N2lu2EoyS9TIZVR60RHwz9eUkjePNntEK65y D6u9+Rt/AbLg15sCE03YMu110ANPN+zdJMBJ8qCvHcKFHWlRZwifdZzCiYtOXka6Dbve BSJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693250835; x=1693855635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TMIOWWSdqeSoUAfHcjIOH1OC+hMNlEb1paPS+tEaJKg=; b=Bjra1ZD9nGekeUOubZHKUEFkSmnxTXq7pCMIX0/PY0EuXzpKo+uKr+VXDk0rGEEuaI lB5u9j9y9xCRTqPmHKsJnH0C+Ef9Nzj7SdnwAO+5UkMnmcWMDDsJbRW8DsreYVb8WbUd C2lEPifz+9t9CNazBmm7SUJUNGgSi9EduruchPuT+Ebr/R8lW3ejvZ3sY8TxIOTfeSMl 5g1nEKi9jqj5tDhaB0YOpymR2yas4p4XHSgMphNPqHALyVFmXqkHBW6/FBzKkM+Vl2ZP 9vmGnAusWoj/UPHXZW+ht12WNHGnPPrAe097vA0ujq7E6jxmUVu/Bot2PnvEiMQnCGm5 KUyA== X-Gm-Message-State: AOJu0Yw2197xpdbiWdcw9XJa5hTKcLm4xpMvfSSWim44w1AVDXKgna/a akyylvLJmpnsRrC6ll3Gt0JXUA== X-Google-Smtp-Source: AGHT+IGwSg/n9slu02mhVXrK3uD2f2TSMnRa4Rgqq9mKJ/qMfRRSzAIiIAyq0Qe05qJxlrLQgd/K1Q== X-Received: by 2002:a5d:414f:0:b0:314:17cc:31d0 with SMTP id c15-20020a5d414f000000b0031417cc31d0mr20153261wrq.34.1693250835788; Mon, 28 Aug 2023 12:27:15 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:8bd:7f16:d368:115f]) by smtp.gmail.com with ESMTPSA id i20-20020a5d5234000000b003141f96ed36sm11435319wra.0.2023.08.28.12.27.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Aug 2023 12:27:15 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Alex Elder , Srini Kandagatla Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH 11/11] arm64: dts: qcom: sm8150: enable SHM bridge Date: Mon, 28 Aug 2023 21:25:07 +0200 Message-Id: <20230828192507.117334-12-bartosz.golaszewski@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> References: <20230828192507.117334-1-bartosz.golaszewski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable SHM bridge on sm8150 platforms. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index b46e55bb8bde..ffb0b9d82bea 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -607,6 +607,10 @@ scm: scm { compatible =3D "qcom,scm-sm8150", "qcom,scm"; #reset-cells =3D <1>; }; + + shm-bridge { + compatible =3D "qcom,shm-bridge-sm8150", "qcom,shm-bridge"; + }; }; =20 memory@80000000 { --=20 2.39.2