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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9DA.mail.protection.outlook.com (10.167.241.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6745.17 via Frontend Transport; Mon, 28 Aug 2023 12:28:37 +0000 Received: from rtg-Artic.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 28 Aug 2023 07:28:33 -0500 From: Arvind Yadav To: , , , , , , , CC: , , "Arvind Yadav" , Christian Koenig Subject: [PATCH v3 3/7] drm/amdgpu: Add new function to put GPU power profile Date: Mon, 28 Aug 2023 17:56:10 +0530 Message-ID: <20230828122614.3815122-4-Arvind.Yadav@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230828122614.3815122-1-Arvind.Yadav@amd.com> References: <20230828122614.3815122-1-Arvind.Yadav@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DA:EE_|PH7PR12MB7939:EE_ X-MS-Office365-Filtering-Correlation-Id: 465fa6a5-9029-45e1-400f-08dba7c24e23 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 12:28:37.8390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 465fa6a5-9029-45e1-400f-08dba7c24e23 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7939 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds a function which will clear the GPU power profile after job finished. This is how it works: - schedular will set the GPU power profile based on ring_type. - Schedular will clear the GPU Power profile once job finished. - Here, the *_workload_profile_set function will set the GPU power profile and the *_workload_profile_put function will schedule the smu_delayed_work task after 100ms delay. This smu_delayed_work task will clear a GPU power profile if any new jobs are not scheduled within 100 ms. But if any new job comes within 100ms then the *_workload_profile_set function will cancel this work and set the GPU power profile based on preferences. v2: - Splitting workload_profile_set and workload_profile_put into two separate patches. - Addressed review comment. v3: - Adressed all the review comment. - Now clearing all the profile in work handler. - Added *_clear_all function to clear all the power profile. - scheduling delay work to clear the power profile when refcount becomes zero. Cc: Shashank Sharma Cc: Christian Koenig Cc: Alex Deucher Signed-off-by: Arvind Yadav --- drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c | 118 +++++++++++++++++- drivers/gpu/drm/amd/include/amdgpu_workload.h | 3 + 2 files changed, 120 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c b/drivers/gpu/drm= /amd/amdgpu/amdgpu_workload.c index 67eacaac6c9b..fbe86ee5b8bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c @@ -24,6 +24,9 @@ =20 #include "amdgpu.h" =20 +/* 100 millsecond timeout */ +#define SMU_IDLE_TIMEOUT msecs_to_jiffies(100) + static enum PP_SMC_POWER_PROFILE ring_to_power_profile(uint32_t ring_type) { @@ -58,16 +61,111 @@ amdgpu_power_profile_set(struct amdgpu_device *adev, return ret; } =20 +static int +amdgpu_power_profile_clear(struct amdgpu_device *adev, + enum PP_SMC_POWER_PROFILE profile) +{ + int ret =3D amdgpu_dpm_switch_power_profile(adev, profile, false); + + if (!ret) { + /* Clear the bit for the submitted workload profile */ + clear_bit(profile, &adev->smu_workload.submit_workload_status); + } + + return ret; +} + +static void +amdgpu_power_profile_clear_all(struct amdgpu_device *adev, + struct amdgpu_smu_workload *workload) +{ + int ret; + int profile =3D PP_SMC_POWER_PROFILE_COMPUTE; + + cancel_delayed_work_sync(&workload->power_profile_work); + mutex_lock(&workload->workload_lock); + + /* Clear all the GPU power profile*/ + for (; profile > 0; profile--) { + atomic_set(&workload->power_profile_ref[profile], 0); + ret =3D amdgpu_power_profile_clear(adev, profile); + if (ret) { + DRM_WARN("Failed to clear workload %s,error =3D %d\n", + amdgpu_workload_mode_name[profile], ret); + } + } + + workload->submit_workload_status =3D 0; + mutex_unlock(&workload->workload_lock); +} + +static void +amdgpu_power_profile_idle_work_handler(struct work_struct *work) +{ + + struct amdgpu_smu_workload *workload =3D container_of(work, + struct amdgpu_smu_workload, + power_profile_work.work); + struct amdgpu_device *adev =3D workload->adev; + int ret; + int profile; + + mutex_lock(&workload->workload_lock); + + /* Clear all the GPU power profile*/ + for_each_set_bit(profile, &workload->submit_workload_status, + PP_SMC_POWER_PROFILE_CUSTOM) { + if (!atomic_read(&workload->power_profile_ref[profile])) { + ret =3D amdgpu_power_profile_clear(adev, profile); + if (ret) { + DRM_WARN("Failed to clear workload %s,error =3D %d\n", + amdgpu_workload_mode_name[profile], ret); + } + } + } + + mutex_unlock(&workload->workload_lock); +} + +void amdgpu_workload_profile_put(struct amdgpu_device *adev, + uint32_t ring_type) +{ + struct amdgpu_smu_workload *workload =3D &adev->smu_workload; + enum PP_SMC_POWER_PROFILE profile =3D ring_to_power_profile(ring_type); + int refcount; + + if (profile =3D=3D PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT) + return; + + mutex_lock(&workload->workload_lock); + + refcount =3D atomic_read(&workload->power_profile_ref[profile]); + if (!refcount) { + DRM_WARN("Power profile %s ref. count error\n", + amdgpu_workload_mode_name[profile]); + } else { + if (refcount =3D=3D 1) + schedule_delayed_work(&workload->power_profile_work, + SMU_IDLE_TIMEOUT); + + atomic_dec(&workload->power_profile_ref[profile]); + } + + mutex_unlock(&workload->workload_lock); +} + void amdgpu_workload_profile_get(struct amdgpu_device *adev, uint32_t ring_type) { struct amdgpu_smu_workload *workload =3D &adev->smu_workload; enum PP_SMC_POWER_PROFILE profile =3D ring_to_power_profile(ring_type); int ret, refcount; + int index; =20 if (profile =3D=3D PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT) return; =20 + cancel_delayed_work_sync(&workload->power_profile_work); mutex_lock(&workload->workload_lock); =20 refcount =3D atomic_read(&workload->power_profile_ref[profile]); @@ -80,6 +178,22 @@ void amdgpu_workload_profile_get(struct amdgpu_device *= adev, } =20 atomic_inc(&adev->smu_workload.power_profile_ref[profile]); + + /* As we cancelled the delayed work, check and clear the pending + * power profiles set by previous jobs which are now done. + */ + for_each_set_bit(index, &workload->submit_workload_status, + PP_SMC_POWER_PROFILE_CUSTOM) { + if (!atomic_read(&workload->power_profile_ref[index]) && + (index !=3D profile)) { + ret =3D amdgpu_power_profile_clear(adev, index); + if (ret) { + DRM_WARN("Failed to clear workload %s, err =3D %d\n", + amdgpu_workload_mode_name[profile], ret); + } + } + } + mutex_unlock(&workload->workload_lock); } =20 @@ -90,6 +204,8 @@ void amdgpu_workload_profile_init(struct amdgpu_device *= adev) adev->smu_workload.initialized =3D true; =20 mutex_init(&adev->smu_workload.workload_lock); + INIT_DELAYED_WORK(&adev->smu_workload.power_profile_work, + amdgpu_power_profile_idle_work_handler); } =20 void amdgpu_workload_profile_fini(struct amdgpu_device *adev) @@ -97,7 +213,7 @@ void amdgpu_workload_profile_fini(struct amdgpu_device *= adev) if (!adev->smu_workload.initialized) return; =20 - adev->smu_workload.submit_workload_status =3D 0; + amdgpu_power_profile_clear_all(adev, &adev->smu_workload); adev->smu_workload.initialized =3D false; mutex_destroy(&adev->smu_workload.workload_lock); } diff --git a/drivers/gpu/drm/amd/include/amdgpu_workload.h b/drivers/gpu/dr= m/amd/include/amdgpu_workload.h index 5fc0bc2a74a4..596a962800e9 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_workload.h +++ b/drivers/gpu/drm/amd/include/amdgpu_workload.h @@ -46,6 +46,9 @@ static const char * const amdgpu_workload_mode_name[] =3D= { "Window3D" }; =20 +void amdgpu_workload_profile_put(struct amdgpu_device *adev, + uint32_t ring_type); + void amdgpu_workload_profile_get(struct amdgpu_device *adev, uint32_t ring_type); =20 --=20 2.34.1