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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D8.mail.protection.outlook.com (10.167.241.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6745.17 via Frontend Transport; Mon, 28 Aug 2023 12:28:09 +0000 Received: from rtg-Artic.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 28 Aug 2023 07:26:58 -0500 From: Arvind Yadav To: , , , , , , , CC: , , "Arvind Yadav" , Christian Koenig Subject: [PATCH v3 1/7] drm/amdgpu: Added init/fini functions for workload Date: Mon, 28 Aug 2023 17:56:08 +0530 Message-ID: <20230828122614.3815122-2-Arvind.Yadav@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230828122614.3815122-1-Arvind.Yadav@amd.com> References: <20230828122614.3815122-1-Arvind.Yadav@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|MN0PR12MB5715:EE_ X-MS-Office365-Filtering-Correlation-Id: 8361316d-a7cd-46cb-4426-08dba7c23cff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Aug 2023 12:28:09.0975 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8361316d-a7cd-46cb-4426-08dba7c23cff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5715 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The'struct amdgpu_smu_workload' initialization/cleanup functions is added by this patch. v2: - Splitting big patch into separate patches. - Added new fini function. v3: - Addressed review comment to change 'power_profile_work' instead of 'smu_delayed_work'. Cc: Christian Koenig Cc: Alex Deucher Reviewed-by: Shashank Sharma Signed-off-by: Arvind Yadav --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c | 44 +++++++++++++++ drivers/gpu/drm/amd/include/amdgpu_workload.h | 53 +++++++++++++++++++ 5 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c create mode 100644 drivers/gpu/drm/amd/include/amdgpu_workload.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdg= pu/Makefile index 415a7fa395c4..6a9e187d61e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -60,7 +60,7 @@ amdgpu-y +=3D amdgpu_device.o amdgpu_kms.o \ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \ amdgpu_fw_attestation.o amdgpu_securedisplay.o \ amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \ - amdgpu_ring_mux.o + amdgpu_ring_mux.o amdgpu_workload.o =20 amdgpu-$(CONFIG_PROC_FS) +=3D amdgpu_fdinfo.o =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdg= pu/amdgpu.h index 02b827785e39..1939fa1af8a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -107,6 +107,7 @@ #include "amdgpu_fdinfo.h" #include "amdgpu_mca.h" #include "amdgpu_ras.h" +#include "amdgpu_workload.h" =20 #define MAX_GPU_INSTANCE 16 =20 @@ -1050,6 +1051,8 @@ struct amdgpu_device { =20 bool job_hang; bool dc_enabled; + + struct amdgpu_smu_workload smu_workload; }; =20 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index 5c7d40873ee2..cd3bf641b630 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2243,6 +2243,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_= device *adev) adev->cg_flags &=3D amdgpu_cg_mask; adev->pg_flags &=3D amdgpu_pg_mask; =20 + amdgpu_workload_profile_init(adev); + return 0; } =20 @@ -2890,6 +2892,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device= *adev) { int i, r; =20 + amdgpu_workload_profile_fini(adev); + if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) amdgpu_virt_release_ras_err_handler_data(adev); =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c b/drivers/gpu/drm= /amd/amdgpu/amdgpu_workload.c new file mode 100644 index 000000000000..32166f482f77 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software= "), + * to deal in the Software without restriction, including without limitati= on + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "amdgpu.h" + +void amdgpu_workload_profile_init(struct amdgpu_device *adev) +{ + adev->smu_workload.adev =3D adev; + adev->smu_workload.submit_workload_status =3D 0; + adev->smu_workload.initialized =3D true; + + mutex_init(&adev->smu_workload.workload_lock); +} + +void amdgpu_workload_profile_fini(struct amdgpu_device *adev) +{ + if (!adev->smu_workload.initialized) + return; + + adev->smu_workload.submit_workload_status =3D 0; + adev->smu_workload.initialized =3D false; + mutex_destroy(&adev->smu_workload.workload_lock); +} diff --git a/drivers/gpu/drm/amd/include/amdgpu_workload.h b/drivers/gpu/dr= m/amd/include/amdgpu_workload.h new file mode 100644 index 000000000000..dc12448764a3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/amdgpu_workload.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software= "), + * to deal in the Software without restriction, including without limitati= on + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _AMDGPU_WORKLOAD_H_ +#define _AMDGPU_WORKLOAD_H_ + +struct amdgpu_smu_workload { + struct amdgpu_device *adev; + struct mutex workload_lock; + struct delayed_work power_profile_work; + unsigned long submit_workload_status; + bool initialized; + atomic_t power_profile_ref[PP_SMC_POWER_PROFILE_COUNT]; +}; + +/* Workload mode names */ +static const char * const amdgpu_workload_mode_name[] =3D { + "Default", + "3D", + "Powersaving", + "Video", + "VR", + "Compute", + "Custom", + "Window3D" +}; + +void amdgpu_workload_profile_init(struct amdgpu_device *adev); + +void amdgpu_workload_profile_fini(struct amdgpu_device *adev); + +#endif --=20 2.34.1