From nobody Thu Dec 18 04:27:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C703C6FA8F for ; Thu, 24 Aug 2023 15:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242207AbjHXPdH (ORCPT ); Thu, 24 Aug 2023 11:33:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236845AbjHXPdD (ORCPT ); Thu, 24 Aug 2023 11:33:03 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2499BCEE for ; Thu, 24 Aug 2023 08:33:01 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-68a1af910e0so3908795b3a.2 for ; Thu, 24 Aug 2023 08:33:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1692891180; x=1693495980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1heW6OffuAP0ul2AbuPI0sVn5slQ3SwOx99vGjvV2yE=; b=fBfgs6F5QbNoASGEkqDOvmfsUp2ZgJsd9gK29T2AgR+9lx9Yq7YZdG+5S+jWL1Ds2L L7hjIkWXBUxSIJXaMwzSoam755X4W6vIteQnXKcxGZmTYZCkw5GFtKx1tT9F/ANcOWk1 8PEeSJACjjp6Atyt9LSoOox6fdWBPuU5AhAeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692891180; x=1693495980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1heW6OffuAP0ul2AbuPI0sVn5slQ3SwOx99vGjvV2yE=; b=AxLjWoqMMK96uzjR4gtsJfIbAj1QQM6deBvPhm11dwWIyKy3Ng7WLOqVpsewHknYEi riZzASSe2c/Com2y+zsJjq4kPvK3e6AZ4haTv+W93eMbbP5bbcWGW3MyZiuU3+5yUoWy 2dfJv2eIQpqq1tm4JsF9io1BuoDm4ITB1BPrrugywgd49balidVNSvGSkMyy5Z/UQCGB aEuaswbQBj8wDvNaWpPCz1XEhUTOMiq3o/KVL8hCb0dRtpkvDDdg72VpiJhtceq68D7d 9pue7BODrBKEDh4eK9OeYtuCdiZRL00UUZ2hcMtzxoWdZNs67/SaqCNfsH5wSiRFyiXX Wesg== X-Gm-Message-State: AOJu0YzNuTMmfuCCzE2LOootwrYCFTNVu+parXWT9dK9fpdoCjoedBEX 97KbwQ850VYXxsDbdCwTyQRp6g== X-Google-Smtp-Source: AGHT+IEv4M4LGNkfwmqZe1my0PmiiMeAPofLo901bcZKMxOHhBpmHlVQlwJgkcS2WXcsvHS/2b0mrw== X-Received: by 2002:a05:6a00:248d:b0:68b:ee34:9729 with SMTP id c13-20020a056a00248d00b0068bee349729mr2610258pfv.24.1692891180526; Thu, 24 Aug 2023 08:33:00 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:afa3:fcf5:1b7f:f7e2]) by smtp.gmail.com with ESMTPSA id m30-20020a63711e000000b0056365ee8603sm11631337pgc.67.2023.08.24.08.32.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 08:32:59 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: "Rafael J . Wysocki" , Ard Biesheuvel , Thomas Gleixner , kgdb-bugreport@lists.sourceforge.net, Lecopzer Chen , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, ito-yuichi@fujitsu.com, Stephen Boyd , Peter Zijlstra , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v11 1/6] irqchip/gic-v3: Enable support for SGIs to act as NMIs Date: Thu, 24 Aug 2023 08:30:27 -0700 Message-ID: <20230824083012.v11.1.I1223c11c88937bd0cbd9b086d4ef216985797302@changeid> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog In-Reply-To: <20230824153233.1006420-1-dianders@chromium.org> References: <20230824153233.1006420-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As of commit 6abbd6988971 ("irqchip/gic, gic-v3: Make SGIs use handle_percpu_devid_irq()") SGIs are treated the same as PPIs/EPPIs and use handle_percpu_devid_irq() by default. Unfortunately, handle_percpu_devid_irq() isn't NMI safe, and so to run in an NMI context those should use handle_percpu_devid_fasteoi_nmi(). In order to accomplish this, we just have to make room for SGIs in the array of refcounts that keeps track of which interrupts are set as NMI. We also rename the array and create a new indexing scheme that accounts for SGIs. Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as IRQs/NMIs happen as part of this routine. Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Signed-off-by: Douglas Anderson --- In v10 I removed the previous Reviewed-by and Tested-by tags since the patch contents changed pretty drastically. I'll also note that this change is a little more black magic to me than others in this series. I don't have a massive amounts of familiarity with all the moving parts of gic-v3, so I mostly just followed Mark Rutland's advice [1]. Please pay extra attention to make sure I didn't do anything too terrible. Mark's advice wasn't a full patch and I ended up doing a bit of work to translate it to reality, so I did not add him as "Co-developed-by" here. Mark: if you would like this tag then please provide it and your Signed-off-by. I certainly won't object. [1] https://lore.kernel.org/r/ZNC-YRQopO0PaIIo@FVFF77S0Q05N.cambridge.arm.c= om (no changes since v10) Changes in v10: - Rewrite as needed for 5.11+ as per Mark Rutland and Sumit. drivers/irqchip/irq-gic-v3.c | 54 ++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index eedfa8e9f077..49d18cf3f636 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -78,6 +78,8 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U) #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer) =20 +#define SGI_NR 16 + /* * The behaviours of RPR and PMR registers differ depending on the value of * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the @@ -125,8 +127,8 @@ EXPORT_SYMBOL(gic_nonsecure_priorities); __priority; \ }) =20 -/* ppi_nmi_refs[n] =3D=3D number of cpus having ppi[n + 16] set as NMI */ -static refcount_t *ppi_nmi_refs; +/* rdist_nmi_refs[n] =3D=3D number of cpus having the rdist interrupt n se= t as NMI */ +static refcount_t *rdist_nmi_refs; =20 static struct gic_kvm_info gic_v3_kvm_info __initdata; static DEFINE_PER_CPU(bool, has_rss); @@ -519,9 +521,22 @@ static u32 __gic_get_ppi_index(irq_hw_number_t hwirq) } } =20 -static u32 gic_get_ppi_index(struct irq_data *d) +static u32 __gic_get_rdist_idx(irq_hw_number_t hwirq) +{ + switch (__get_intid_range(hwirq)) { + case SGI_RANGE: + case PPI_RANGE: + return hwirq; + case EPPI_RANGE: + return hwirq - EPPI_BASE_INTID + 32; + default: + unreachable(); + } +} + +static u32 gic_get_rdist_idx(struct irq_data *d) { - return __gic_get_ppi_index(d->hwirq); + return __gic_get_rdist_idx(d->hwirq); } =20 static int gic_irq_nmi_setup(struct irq_data *d) @@ -545,11 +560,14 @@ static int gic_irq_nmi_setup(struct irq_data *d) =20 /* desc lock should already be held */ if (gic_irq_in_rdist(d)) { - u32 idx =3D gic_get_ppi_index(d); + u32 idx =3D gic_get_rdist_idx(d); =20 - /* Setting up PPI as NMI, only switch handler for first NMI */ - if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { - refcount_set(&ppi_nmi_refs[idx], 1); + /* + * Setting up a percpu interrupt as NMI, only switch handler + * for first NMI + */ + if (!refcount_inc_not_zero(&rdist_nmi_refs[idx])) { + refcount_set(&rdist_nmi_refs[idx], 1); desc->handle_irq =3D handle_percpu_devid_fasteoi_nmi; } } else { @@ -582,10 +600,10 @@ static void gic_irq_nmi_teardown(struct irq_data *d) =20 /* desc lock should already be held */ if (gic_irq_in_rdist(d)) { - u32 idx =3D gic_get_ppi_index(d); + u32 idx =3D gic_get_rdist_idx(d); =20 /* Tearing down NMI, only switch handler for last NMI */ - if (refcount_dec_and_test(&ppi_nmi_refs[idx])) + if (refcount_dec_and_test(&rdist_nmi_refs[idx])) desc->handle_irq =3D handle_percpu_devid_irq; } else { desc->handle_irq =3D handle_fasteoi_irq; @@ -1279,10 +1297,10 @@ static void gic_cpu_init(void) rbase =3D gic_data_rdist_sgi_base(); =20 /* Configure SGIs/PPIs as non-secure Group-1 */ - for (i =3D 0; i < gic_data.ppi_nr + 16; i +=3D 32) + for (i =3D 0; i < gic_data.ppi_nr + SGI_NR; i +=3D 32) writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8); =20 - gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); + gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR, gic_redist_wait_for_rwp); =20 /* initialise system registers */ gic_cpu_sys_reg_init(); @@ -1939,12 +1957,13 @@ static void gic_enable_nmi_support(void) return; } =20 - ppi_nmi_refs =3D kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERN= EL); - if (!ppi_nmi_refs) + rdist_nmi_refs =3D kcalloc(gic_data.ppi_nr + SGI_NR, + sizeof(*rdist_nmi_refs), GFP_KERNEL); + if (!rdist_nmi_refs) return; =20 - for (i =3D 0; i < gic_data.ppi_nr; i++) - refcount_set(&ppi_nmi_refs[i], 0); + for (i =3D 0; i < gic_data.ppi_nr + SGI_NR; i++) + refcount_set(&rdist_nmi_refs[i], 0); =20 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", gic_has_relaxed_pmr_sync() ? "relaxed" : "forced"); @@ -2061,6 +2080,7 @@ static int __init gic_init_bases(phys_addr_t dist_phy= s_base, =20 gic_dist_init(); gic_cpu_init(); + gic_enable_nmi_support(); gic_smp_init(); gic_cpu_pm_init(); =20 @@ -2073,8 +2093,6 @@ static int __init gic_init_bases(phys_addr_t dist_phy= s_base, gicv2m_init(handle, gic_data.domain); } =20 - gic_enable_nmi_support(); - return 0; =20 out_free: --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Thu Dec 18 04:27:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02C23C7EE2C for ; Thu, 24 Aug 2023 15:34:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242229AbjHXPdl (ORCPT ); Thu, 24 Aug 2023 11:33:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242202AbjHXPdF (ORCPT ); Thu, 24 Aug 2023 11:33:05 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6EEA19BA for ; Thu, 24 Aug 2023 08:33:03 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-68a3082c771so21000b3a.0 for ; Thu, 24 Aug 2023 08:33:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1692891183; x=1693495983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S8LQV3FZTWxLTg8jNgV7yvfSpimnidUcb0tZukELwI8=; b=lNensNrtbZ1/JO69cv/X7s17yyTO9pvyYki4jYqN0gNJwZSYaEv3k4Lrs/SWiERqSR MVf/1Ic8euWeBn106GsnAPicEAQZXm8K0jrbF94OgDjO8enkM6T2K63rkyzfF4S+v9HW fV2hiAqantxQwPP3J2uQWDI4t+aiqsMaMaFuo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692891183; x=1693495983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S8LQV3FZTWxLTg8jNgV7yvfSpimnidUcb0tZukELwI8=; b=WWiJ1d5nRh/FS0KlgKsv32+KaQr8MRXhyQ+bZmgc6G333VCZHfkMoOekFa5rTaN6FO qH0p+RvT9WDZMnQ/PNrb7znhkBmt4xoFeqK7RdzhQuszCsZGP3vtDdlDPy0gdjX8iZ9G BkDu+oox66dZVKdI77LHAYKhUqEH0t6lTe0uK6lWMxr2JKedXXR7CLo1W+A5zza/9f/G TxyiD28DNIxqlzID+ZimTelIxdmXGuGG8/TSkGaG7s7fgZIYIUhCz6asaSZhovwqPeLU Pu4Md89WDplwoXjYWBWEXIHaj2blN4hsR2aWpLcPVLW1WSg6r9acwq8O2mDkGrsT5QF4 aG1g== X-Gm-Message-State: AOJu0YyIoBQRucPr/lKO63MMp9+agKfzd3NuXn+FpYcuMsnHqq7wfUwt vYBkrpbRZJTHpshmW/mWcTQbLw== X-Google-Smtp-Source: AGHT+IHtE7/RbB67nJdYB/Ae0mTQ0RJ8uJ9wBeYpGrn270z6LtX1u8780/eo8q0EyT04aZwzQcfYQg== X-Received: by 2002:a05:6a20:9187:b0:125:4d74:cd6a with SMTP id v7-20020a056a20918700b001254d74cd6amr22207369pzd.3.1692891182940; Thu, 24 Aug 2023 08:33:02 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:afa3:fcf5:1b7f:f7e2]) by smtp.gmail.com with ESMTPSA id m30-20020a63711e000000b0056365ee8603sm11631337pgc.67.2023.08.24.08.33.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 08:33:02 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: "Rafael J . Wysocki" , Ard Biesheuvel , Thomas Gleixner , kgdb-bugreport@lists.sourceforge.net, Lecopzer Chen , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, ito-yuichi@fujitsu.com, Stephen Boyd , Peter Zijlstra , Douglas Anderson , Frederic Weisbecker , Guo Ren , Ingo Molnar , linux-kernel@vger.kernel.org Subject: [PATCH v11 2/6] arm64: idle: Tag the arm64 idle functions as __cpuidle Date: Thu, 24 Aug 2023 08:30:28 -0700 Message-ID: <20230824083012.v11.2.I4baba13e220bdd24d11400c67f137c35f07f82c7@changeid> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog In-Reply-To: <20230824153233.1006420-1-dianders@chromium.org> References: <20230824153233.1006420-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As per the (somewhat recent) comment before the definition of `__cpuidle`, the tag is like `noinstr` but also marks a function so it can be identified by cpu_in_idle(). Let's add these markings to arm64 cpuidle functions With this change we get useful backtraces like: NMI backtrace for cpu N skipped: idling at cpu_do_idle+0x94/0x98 instead of useless backtraces when dumping all processors using nmi_cpu_backtrace(). NOTE: this patch won't make cpu_in_idle() work perfectly for arm64, but it doesn't hurt and does catch some cases. Specifically an example that wasn't caught in my testing looked like this: gic_cpu_sys_reg_init+0x1f8/0x314 gic_cpu_pm_notifier+0x40/0x78 raw_notifier_call_chain+0x5c/0x134 cpu_pm_notify+0x38/0x64 cpu_pm_exit+0x20/0x2c psci_enter_idle_state+0x48/0x70 cpuidle_enter_state+0xb8/0x260 cpuidle_enter+0x44/0x5c do_idle+0x188/0x30c Acked-by: Mark Rutland Reviewed-by: Stephen Boyd Signed-off-by: Douglas Anderson Acked-by: Sumit Garg --- Changes in v11: - Updated commit message as per Stephen. Changes in v9: - Added to commit message that this doesn't catch all cases. Changes in v8: - "Tag the arm64 idle functions as __cpuidle" new for v8 arch/arm64/kernel/idle.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/idle.c b/arch/arm64/kernel/idle.c index c1125753fe9b..05cfb347ec26 100644 --- a/arch/arm64/kernel/idle.c +++ b/arch/arm64/kernel/idle.c @@ -20,7 +20,7 @@ * ensure that interrupts are not masked at the PMR (because the core will * not wake up if we block the wake up signal in the interrupt controller). */ -void noinstr cpu_do_idle(void) +void __cpuidle cpu_do_idle(void) { struct arm_cpuidle_irq_context context; =20 @@ -35,7 +35,7 @@ void noinstr cpu_do_idle(void) /* * This is our default idle handler. */ -void noinstr arch_cpu_idle(void) +void __cpuidle arch_cpu_idle(void) { /* * This should do all the clock switching and wait for interrupt --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Thu Dec 18 04:27:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 387A6C88CB9 for ; Thu, 24 Aug 2023 15:34:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242242AbjHXPdn (ORCPT ); Thu, 24 Aug 2023 11:33:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242216AbjHXPdI (ORCPT ); Thu, 24 Aug 2023 11:33:08 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26074CEE for ; Thu, 24 Aug 2023 08:33:06 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-68a1af910e0so3908899b3a.2 for ; Thu, 24 Aug 2023 08:33:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1692891185; x=1693495985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2aMgOf9t5wZdItqfD8SuPWRf/5pRJuQTcqZyNhidj2Y=; b=AZcePvBBhLgkuuo3km02W9zjKJl2IhG7RrpVAOMkpvOcG/2wlGtsOJ8VGUvm88K+0I ULFKV0H5DtB2Ugyi5Um/HOZQERkOQQyNxdBF88kTbiY3YXfvVrp7vkL90VTn6aa6Mfo2 6ad6p5cCSR9M5b7zvmTZ06V8Uk4jid4du5IE8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692891185; x=1693495985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2aMgOf9t5wZdItqfD8SuPWRf/5pRJuQTcqZyNhidj2Y=; b=CpTKui+rSJJzP1Ag1JXPgQvbIifnium6JH2WRGL8m0pBHNFOzy7Wo3q/ybt2Fqpk4X QiVvzkiF0VL1IYVTi3NM4eMsUA22v9gfQJoFI6Y3CN8ubx+gKF7ZeU2DO9Fij59mVQ45 ezfF2h3VNhrB4vWY2IGTmslzTxoENlC9GeQtgVSRChNUJtLlhJuloG8TTMnUTdbZ8/j6 9kETHlW8IIpEPzy0XyGboxbUWUZhbExUjpWloedbOS+RrhgGZimoJYzywkHEdLx9ucLv ZQBxk8ycwJCgOh1n4mnfvWhxwTQFy/c0ybUgQVYa7tNPFhjLVzc8MmRzSA4XZk4pJ4Z5 InDQ== X-Gm-Message-State: AOJu0YwZdrXw6ZXYJYh8bsriAk/YsD9ElGODD5ByWOGGIKEsOoAQcBwZ 36XPOxJ7IEp6pP6X8y/M/jOFnA== X-Google-Smtp-Source: AGHT+IE49YAPoY25JDom7a5S38XfT+jTZ7unVGsTuJC6+qpZJdGADROO+tI9gqgujK1/LGuMovHWQg== X-Received: by 2002:a05:6a20:7354:b0:140:3775:3086 with SMTP id v20-20020a056a20735400b0014037753086mr14235980pzc.59.1692891185652; Thu, 24 Aug 2023 08:33:05 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:afa3:fcf5:1b7f:f7e2]) by smtp.gmail.com with ESMTPSA id m30-20020a63711e000000b0056365ee8603sm11631337pgc.67.2023.08.24.08.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 08:33:05 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: "Rafael J . Wysocki" , Ard Biesheuvel , Thomas Gleixner , kgdb-bugreport@lists.sourceforge.net, Lecopzer Chen , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, ito-yuichi@fujitsu.com, Stephen Boyd , Peter Zijlstra , Douglas Anderson , D Scott Phillips , Josh Poimboeuf , Kees Cook , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Tolvanen , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v11 3/6] arm64: smp: Remove dedicated wakeup IPI Date: Thu, 24 Aug 2023 08:30:29 -0700 Message-ID: <20230824083012.v11.3.I7209db47ef8ec151d3de61f59005bbc59fe8f113@changeid> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog In-Reply-To: <20230824153233.1006420-1-dianders@chromium.org> References: <20230824153233.1006420-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Mark Rutland To enable NMI backtrace and KGDB's NMI cpu roundup, we need to free up at least one dedicated IPI. On arm64 the IPI_WAKEUP IPI is only used for the ACPI parking protocol, which itself is only used on some very early ARMv8 systems which couldn't implement PSCI. Remove the IPI_WAKEUP IPI, and rely on the IPI_RESCHEDULE IPI to wake CPUs from the parked state. This will cause a tiny amonut of redundant work to check the thread flags, but this is miniscule in relation to the cost of taking and handling the IPI in the first place. We can safely handle redundant IPI_RESCHEDULE IPIs, so there should be no functional impact as a result of this change. Signed-off-by: Mark Rutland Signed-off-by: Douglas Anderson Cc: Catalin Marinas Cc: Marc Zyngier Cc: Sumit Garg Cc: Will Deacon Reviewed-by: Stephen Boyd Reviewed-by: Sumit Garg --- I have no idea how to test this. I just took Mark's patch and jammed it into my series. Logicially the patch seems reasonable to me. Changes in v11: - arch_send_wakeup_ipi() now takes an unsigned int. Changes in v10: - ("arm64: smp: Remove dedicated wakeup IPI") new for v10. arch/arm64/include/asm/smp.h | 4 ++-- arch/arm64/kernel/acpi_parking_protocol.c | 2 +- arch/arm64/kernel/smp.c | 28 +++++++++-------------- 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 9b31e6d0da17..efb13112b408 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -89,9 +89,9 @@ extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); =20 #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL -extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); +extern void arch_send_wakeup_ipi(unsigned int cpu); #else -static inline void arch_send_wakeup_ipi_mask(const struct cpumask *mask) +static inline void arch_send_wakeup_ipi(unsigned int cpu) { BUILD_BUG(); } diff --git a/arch/arm64/kernel/acpi_parking_protocol.c b/arch/arm64/kernel/= acpi_parking_protocol.c index b1990e38aed0..e1be29e608b7 100644 --- a/arch/arm64/kernel/acpi_parking_protocol.c +++ b/arch/arm64/kernel/acpi_parking_protocol.c @@ -103,7 +103,7 @@ static int acpi_parking_protocol_cpu_boot(unsigned int = cpu) &mailbox->entry_point); writel_relaxed(cpu_entry->gic_cpu_id, &mailbox->cpu_id); =20 - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + arch_send_wakeup_ipi(cpu); =20 return 0; } diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 960b98b43506..a5848f1ef817 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -72,7 +72,6 @@ enum ipi_msg_type { IPI_CPU_CRASH_STOP, IPI_TIMER, IPI_IRQ_WORK, - IPI_WAKEUP, NR_IPI }; =20 @@ -764,7 +763,6 @@ static const char *ipi_types[NR_IPI] __tracepoint_strin= g =3D { [IPI_CPU_CRASH_STOP] =3D "CPU stop (for crash dump) interrupts", [IPI_TIMER] =3D "Timer broadcast interrupts", [IPI_IRQ_WORK] =3D "IRQ work interrupts", - [IPI_WAKEUP] =3D "CPU wake-up interrupts", }; =20 static void smp_cross_call(const struct cpumask *target, unsigned int ipin= r); @@ -797,13 +795,6 @@ void arch_send_call_function_single_ipi(int cpu) smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); } =20 -#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL -void arch_send_wakeup_ipi_mask(const struct cpumask *mask) -{ - smp_cross_call(mask, IPI_WAKEUP); -} -#endif - #ifdef CONFIG_IRQ_WORK void arch_irq_work_raise(void) { @@ -897,14 +888,6 @@ static void do_handle_IPI(int ipinr) break; #endif =20 -#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL - case IPI_WAKEUP: - WARN_ONCE(!acpi_parking_protocol_valid(cpu), - "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", - cpu); - break; -#endif - default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; @@ -979,6 +962,17 @@ void arch_smp_send_reschedule(int cpu) smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); } =20 +#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL +void arch_send_wakeup_ipi(unsigned int cpu) +{ + /* + * We use a scheduler IPI to wake the CPU as this avoids the need for a + * dedicated IPI and we can safely handle spurious scheduler IPIs. + */ + arch_smp_send_reschedule(cpu); +} +#endif + #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST void tick_broadcast(const struct cpumask *mask) { --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Thu Dec 18 04:27:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AD24C88CB2 for ; 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Thu, 24 Aug 2023 08:33:07 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:afa3:fcf5:1b7f:f7e2]) by smtp.gmail.com with ESMTPSA id m30-20020a63711e000000b0056365ee8603sm11631337pgc.67.2023.08.24.08.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 08:33:07 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: "Rafael J . Wysocki" , Ard Biesheuvel , Thomas Gleixner , kgdb-bugreport@lists.sourceforge.net, Lecopzer Chen , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, ito-yuichi@fujitsu.com, Stephen Boyd , Peter Zijlstra , Douglas Anderson , D Scott Phillips , Ingo Molnar , Josh Poimboeuf , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v11 4/6] arm64: smp: Add arch support for backtrace using pseudo-NMI Date: Thu, 24 Aug 2023 08:30:30 -0700 Message-ID: <20230824083012.v11.4.Ie6c132b96ebbbcddbf6954b9469ed40a6960343c@changeid> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog In-Reply-To: <20230824153233.1006420-1-dianders@chromium.org> References: <20230824153233.1006420-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable arch_trigger_cpumask_backtrace() support on arm64. This enables things much like they are enabled on arm32 (including some of the funky logic around NR_IPI, nr_ipi, and MAX_IPI) but with the difference that, unlike arm32, we'll try to enable the backtrace to use pseudo-NMI. NOTE: this patch is a squash of the little bit of code adding the ability to mark an IPI to try to use pseudo-NMI plus the little bit of code to hook things up for kgdb. This approach was decided upon in the discussion of v9 [1]. This patch depends on commit 36759e343ff9 ("nmi_backtrace: allow excluding an arbitrary CPU") since that commit changed the prototype of arch_trigger_cpumask_backtrace(), which this patch implements. [1] https://lore.kernel.org/r/ZORY51mF4alI41G1@FVFF77S0Q05N Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Co-developed-by: Mark Rutland Signed-off-by: Mark Rutland Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v11: - Adjust comment about NR_IPI/MAX_IPI. - Don't use confusing "backed by" idiom in comment. - Made arm64_backtrace_ipi() static. Changes in v10: - Backtrace now directly supported in smp.c - Squash backtrace into patch adding support for pseudo-NMI IPIs. Changes in v9: - Added comments that we might not be using NMI always. - Fold in v8 patch #10 ("Fallback to a regular IPI if NMI isn't enabled") - Moved header file out of "include" since it didn't need to be there. - Remove arm64_supports_nmi() - Renamed "NMI IPI" to "debug IPI" since it might not be backed by NMI. - arch_trigger_cpumask_backtrace() no longer returns bool Changes in v8: - Removed "#ifdef CONFIG_SMP" since arm64 is always SMP - debug_ipi_setup() and debug_ipi_teardown() no longer take cpu param arch/arm64/include/asm/irq.h | 3 ++ arch/arm64/kernel/smp.c | 86 +++++++++++++++++++++++++++++++----- 2 files changed, 78 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index fac08e18bcd5..50ce8b697ff3 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -6,6 +6,9 @@ =20 #include =20 +void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu= ); +#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace + struct pt_regs; =20 int set_handle_irq(void (*handle_irq)(struct pt_regs *)); diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index a5848f1ef817..c8896cbc5327 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -33,6 +33,7 @@ #include #include #include +#include =20 #include #include @@ -72,12 +73,18 @@ enum ipi_msg_type { IPI_CPU_CRASH_STOP, IPI_TIMER, IPI_IRQ_WORK, - NR_IPI + NR_IPI, + /* + * Any enum >=3D NR_IPI and < MAX_IPI is special and not tracable + * with trace_ipi_* + */ + IPI_CPU_BACKTRACE =3D NR_IPI, + MAX_IPI }; =20 static int ipi_irq_base __read_mostly; static int nr_ipi __read_mostly =3D NR_IPI; -static struct irq_desc *ipi_desc[NR_IPI] __read_mostly; +static struct irq_desc *ipi_desc[MAX_IPI] __read_mostly; =20 static void ipi_setup(int cpu); =20 @@ -845,6 +852,22 @@ static void __noreturn ipi_cpu_crash_stop(unsigned int= cpu, struct pt_regs *regs #endif } =20 +static void arm64_backtrace_ipi(cpumask_t *mask) +{ + __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask); +} + +void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) +{ + /* + * NOTE: though nmi_trigger_cpumask_backtrace has "nmi_" in the name, + * nothing about it truly needs to be implemented using an NMI, it's + * just that it's _allowed_ to work with NMIs. If ipi_should_be_nmi() + * returned false our backtrace attempt will just use a regular IPI. + */ + nmi_trigger_cpumask_backtrace(mask, exclude_cpu, arm64_backtrace_ipi); +} + /* * Main handler for inter-processor interrupts */ @@ -888,6 +911,14 @@ static void do_handle_IPI(int ipinr) break; #endif =20 + case IPI_CPU_BACKTRACE: + /* + * NOTE: in some cases this _won't_ be NMI context. See the + * comment in arch_trigger_cpumask_backtrace(). + */ + nmi_cpu_backtrace(get_irq_regs()); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; @@ -909,6 +940,19 @@ static void smp_cross_call(const struct cpumask *targe= t, unsigned int ipinr) __ipi_send_mask(ipi_desc[ipinr], target); } =20 +static bool ipi_should_be_nmi(enum ipi_msg_type ipi) +{ + if (!system_uses_irq_prio_masking()) + return false; + + switch (ipi) { + case IPI_CPU_BACKTRACE: + return true; + default: + return false; + } +} + static void ipi_setup(int cpu) { int i; @@ -916,8 +960,14 @@ static void ipi_setup(int cpu) if (WARN_ON_ONCE(!ipi_irq_base)) return; =20 - for (i =3D 0; i < nr_ipi; i++) - enable_percpu_irq(ipi_irq_base + i, 0); + for (i =3D 0; i < nr_ipi; i++) { + if (ipi_should_be_nmi(i)) { + prepare_percpu_nmi(ipi_irq_base + i); + enable_percpu_nmi(ipi_irq_base + i, 0); + } else { + enable_percpu_irq(ipi_irq_base + i, 0); + } + } } =20 #ifdef CONFIG_HOTPLUG_CPU @@ -928,8 +978,14 @@ static void ipi_teardown(int cpu) if (WARN_ON_ONCE(!ipi_irq_base)) return; =20 - for (i =3D 0; i < nr_ipi; i++) - disable_percpu_irq(ipi_irq_base + i); + for (i =3D 0; i < nr_ipi; i++) { + if (ipi_should_be_nmi(i)) { + disable_percpu_nmi(ipi_irq_base + i); + teardown_percpu_nmi(ipi_irq_base + i); + } else { + disable_percpu_irq(ipi_irq_base + i); + } + } } #endif =20 @@ -937,15 +993,23 @@ void __init set_smp_ipi_range(int ipi_base, int n) { int i; =20 - WARN_ON(n < NR_IPI); - nr_ipi =3D min(n, NR_IPI); + WARN_ON(n < MAX_IPI); + nr_ipi =3D min(n, MAX_IPI); =20 for (i =3D 0; i < nr_ipi; i++) { int err; =20 - err =3D request_percpu_irq(ipi_base + i, ipi_handler, - "IPI", &cpu_number); - WARN_ON(err); + if (ipi_should_be_nmi(i)) { + err =3D request_percpu_nmi(ipi_base + i, ipi_handler, + "IPI", &cpu_number); + WARN(err, "Could not request IPI %d as NMI, err=3D%d\n", + i, err); + } else { + err =3D request_percpu_irq(ipi_base + i, ipi_handler, + "IPI", &cpu_number); + WARN(err, "Could not request IPI %d as IRQ, err=3D%d\n", + i, err); + } =20 ipi_desc[i] =3D irq_to_desc(ipi_base + i); irq_set_status_flags(ipi_base + i, IRQ_HIDDEN); --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Thu Dec 18 04:27:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A5F5EE49A5 for ; Thu, 24 Aug 2023 15:34:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242252AbjHXPds (ORCPT ); Thu, 24 Aug 2023 11:33:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242233AbjHXPdM (ORCPT ); Thu, 24 Aug 2023 11:33:12 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE225CEE for ; Thu, 24 Aug 2023 08:33:10 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-68a402c1fcdso3409089b3a.1 for ; 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Thu, 24 Aug 2023 08:33:10 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:afa3:fcf5:1b7f:f7e2]) by smtp.gmail.com with ESMTPSA id m30-20020a63711e000000b0056365ee8603sm11631337pgc.67.2023.08.24.08.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 08:33:09 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: "Rafael J . Wysocki" , Ard Biesheuvel , Thomas Gleixner , kgdb-bugreport@lists.sourceforge.net, Lecopzer Chen , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, ito-yuichi@fujitsu.com, Stephen Boyd , Peter Zijlstra , Douglas Anderson , D Scott Phillips , Ingo Molnar , Josh Poimboeuf , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v11 5/6] arm64: smp: IPI_CPU_STOP and IPI_CPU_CRASH_STOP should try for NMI Date: Thu, 24 Aug 2023 08:30:31 -0700 Message-ID: <20230824083012.v11.5.Ifadbfd45b22c52edcb499034dd4783d096343260@changeid> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog In-Reply-To: <20230824153233.1006420-1-dianders@chromium.org> References: <20230824153233.1006420-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There's no reason why IPI_CPU_STOP and IPI_CPU_CRASH_STOP can't be handled as NMI. They are very simple and everything in them is NMI-safe. Mark them as things to use NMI for if NMI is available. Suggested-by: Mark Rutland Reviewed-by: Stephen Boyd Signed-off-by: Douglas Anderson Reviewed-by: Sumit Garg --- I don't actually have any good way to test/validate this patch. It's added to the series at Mark's request. (no changes since v10) Changes in v10: - ("IPI_CPU_STOP and IPI_CPU_CRASH_STOP should try for NMI") new for v10. arch/arm64/kernel/smp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index c8896cbc5327..4566934aaf9f 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -946,6 +946,8 @@ static bool ipi_should_be_nmi(enum ipi_msg_type ipi) return false; =20 switch (ipi) { + case IPI_CPU_STOP: + case IPI_CPU_CRASH_STOP: case IPI_CPU_BACKTRACE: return true; default: --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Thu Dec 18 04:27:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A437EE49A6 for ; Thu, 24 Aug 2023 15:34:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242288AbjHXPdu (ORCPT ); Thu, 24 Aug 2023 11:33:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242237AbjHXPdP (ORCPT ); Thu, 24 Aug 2023 11:33:15 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D739CEE for ; Thu, 24 Aug 2023 08:33:13 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-68a3082c771so21129b3a.0 for ; Thu, 24 Aug 2023 08:33:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1692891193; x=1693495993; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PpvKkEI/e7qDOTO7kkwnbGAWQL/h1j/QJekiYZuCdi8=; b=Eqf7ZSxJom24lSCPPItZp0Jzzsgydj3wjWNxBG8UNQBsegWpHjaQtL61A3HiBfuCSo J6ml8OZW3onJcqmoTMruSdhqZm2KlF9FZfDEflnZQcMt0G9ngDavylngBuvI7gJwipef +GFSyITHnIR+HkAukdoTDl81UHsm3QEZjrhug= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692891193; x=1693495993; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PpvKkEI/e7qDOTO7kkwnbGAWQL/h1j/QJekiYZuCdi8=; b=KNunR+Sp8uju8wJe1/LSzZ542NzA/SGB4B75Mm0DuXkp3iv7xIoxBOMJIsBWmGgkdk lSh7IV2fT2JFJSZf6fS+Jh+6N+XaA+sGm1V57PbYG5z0c5hquOVRSvp/ZM/l3712tsNq gaGfuba4y7Bvi4Gvb9eUnBc0NDIdbeLYQ8UYby29agT6ObVyiEL3s06VBSQFMcEj9Qtk 82NdpuI8rDQgq0nlhS/xa8XZUHyB6C6k82oT8zLW2lu8YzvAtxm6buW7oNI4hsS5Pg0X dswzFejekUc2VUXG8AYRNrxfIEXbeeihL4dYTq0i5OMNNzX5mY9LFfb5V16rGwciZJk9 AsCA== X-Gm-Message-State: AOJu0YxiHoLFBCj1Y52uzQH1aa/yxghSAb0flirW0/ty9TGru/4oGo3U /8e9nW2DThchg8GYd3MlRV0H4tO8lMUKkJzc8xX0TiHF X-Google-Smtp-Source: AGHT+IH3Wlo4UhfEjU/WdEk/Y/44LnzFs3Gaq+1amqWxjKrBJ8EosqQauQzhM/dQC7jvUfImtbjO5A== X-Received: by 2002:a05:6a00:ccd:b0:68a:45a1:c0f7 with SMTP id b13-20020a056a000ccd00b0068a45a1c0f7mr20902029pfv.8.1692891192681; Thu, 24 Aug 2023 08:33:12 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:afa3:fcf5:1b7f:f7e2]) by smtp.gmail.com with ESMTPSA id m30-20020a63711e000000b0056365ee8603sm11631337pgc.67.2023.08.24.08.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 08:33:12 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: "Rafael J . Wysocki" , Ard Biesheuvel , Thomas Gleixner , kgdb-bugreport@lists.sourceforge.net, Lecopzer Chen , linux-perf-users@vger.kernel.org, Masayoshi Mizuma , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, ito-yuichi@fujitsu.com, Stephen Boyd , Peter Zijlstra , Douglas Anderson , D Scott Phillips , Josh Poimboeuf , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v11 6/6] arm64: kgdb: Implement kgdb_roundup_cpus() to enable pseudo-NMI roundup Date: Thu, 24 Aug 2023 08:30:32 -0700 Message-ID: <20230824083012.v11.6.I2ef26d1b3bfbed2d10a281942b0da7d9854de05e@changeid> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog In-Reply-To: <20230824153233.1006420-1-dianders@chromium.org> References: <20230824153233.1006420-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Up until now we've been using the generic (weak) implementation for kgdb_roundup_cpus() when using kgdb on arm64. Let's move to a custom one. The advantage here is that, when pseudo-NMI is enabled on a device, we'll be able to round up CPUs using pseudo-NMI. This allows us to debug CPUs that are stuck with interrupts disabled. If pseudo-NMIs are not enabled then we'll fallback to just using an IPI, which is still slightly better than the generic implementation since it avoids the potential situation described in the generic kgdb_call_nmi_hook(). Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Signed-off-by: Douglas Anderson Reviewed-by: Daniel Thompson Reviewed-by: Stephen Boyd --- I debated whether this should be in "arch/arm64/kernel/smp.c" or if I should try to find a way for it to go into "arch/arm64/kernel/kgdb.c". In the end this is so little code that it didn't seem worth it to find a way to export the IPI defines or to otherwise come up with some API between kgdb.c and smp.c. If someone has strong feelings and wants this to change, please shout and give details of your preferred solution. FWIW, it seems like ~half the other platforms put this in "smp.c" with an ifdef for KGDB and the other half put it in "kgdb.c" with an ifdef for SMP. :-P (no changes since v10) Changes in v10: - Don't allocate the cpumask on the stack; just iterate. - Moved kgdb calls to smp.c to avoid needing to export IPI info. - kgdb now has its own IPI. Changes in v9: - Remove fallback for when debug IPI isn't available. - Renamed "NMI IPI" to "debug IPI" since it might not be backed by NMI. arch/arm64/kernel/smp.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 4566934aaf9f..d440c8b21ea7 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include =20 @@ -79,6 +80,7 @@ enum ipi_msg_type { * with trace_ipi_* */ IPI_CPU_BACKTRACE =3D NR_IPI, + IPI_KGDB_ROUNDUP, MAX_IPI }; =20 @@ -868,6 +870,22 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *m= ask, int exclude_cpu) nmi_trigger_cpumask_backtrace(mask, exclude_cpu, arm64_backtrace_ipi); } =20 +#ifdef CONFIG_KGDB +void kgdb_roundup_cpus(void) +{ + int this_cpu =3D raw_smp_processor_id(); + int cpu; + + for_each_online_cpu(cpu) { + /* No need to roundup ourselves */ + if (cpu =3D=3D this_cpu) + continue; + + __ipi_send_single(ipi_desc[IPI_KGDB_ROUNDUP], cpu); + } +} +#endif + /* * Main handler for inter-processor interrupts */ @@ -919,6 +937,10 @@ static void do_handle_IPI(int ipinr) nmi_cpu_backtrace(get_irq_regs()); break; =20 + case IPI_KGDB_ROUNDUP: + kgdb_nmicallback(cpu, get_irq_regs()); + break; + default: pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); break; @@ -949,6 +971,7 @@ static bool ipi_should_be_nmi(enum ipi_msg_type ipi) case IPI_CPU_STOP: case IPI_CPU_CRASH_STOP: case IPI_CPU_BACKTRACE: + case IPI_KGDB_ROUNDUP: return true; default: return false; --=20 2.42.0.rc1.204.g551eb34607-goog