From nobody Fri Sep 12 01:34:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92529C7EE43 for ; Thu, 24 Aug 2023 08:13:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236154AbjHXINc (ORCPT ); Thu, 24 Aug 2023 04:13:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240769AbjHXIMu (ORCPT ); Thu, 24 Aug 2023 04:12:50 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC9252680; Thu, 24 Aug 2023 01:11:33 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37NJovuw006693; Thu, 24 Aug 2023 01:10:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2eeMYILgzstzqJYBzT/glFZkbgjDBDbKhpBYdCnItOM=; b=P9666dtO8crRP5/5jART5nzzvpbKNMbfuSkBpUOZrBuXgy1xWuJd0k1NZCxMvFhMyS18 feuYwY2azVHFr2NWPsh2rTUpfATjH6TGNqMWCxKDHqktZf1BrUKRyhT5CvbUyrHoeFNd 6mPeshnZ1ILoJvqDxd1pIf6NQjS+dsxw/RPBA9bdnSinlucsPURfxL40VL3nrJCOisGN OwTU2fzV3vBMMqnGHHhvPrzAcM1Leg+OllpJDY45IeHVgMB4YvkYhAjrMuuS62hddcsj ItudQD143cSYxyl9MT0bsXKSd9TSiuMtQ5tRjhHxO0+LJrpGPoMgeWBzrzguHVz8oi1O vA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3snrmcsv8v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 Aug 2023 01:10:53 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 24 Aug 2023 01:10:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 24 Aug 2023 01:10:51 -0700 Received: from localhost.localdomain (unknown [10.28.36.166]) by maili.marvell.com (Postfix) with ESMTP id 56A883F704C; Thu, 24 Aug 2023 01:10:47 -0700 (PDT) From: Suman Ghosh To: , , , , , , , , , , , , Subject: [net PATCH V4 2/3] octeontx2-af: CN10KB: fix PFC configuration Date: Thu, 24 Aug 2023 13:40:31 +0530 Message-ID: <20230824081032.436432-3-sumang@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230824081032.436432-1-sumang@marvell.com> References: <20230824081032.436432-1-sumang@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: T0o8lBgDuxCmXjkPBZQpf2HLqzaPdadn X-Proofpoint-ORIG-GUID: T0o8lBgDuxCmXjkPBZQpf2HLqzaPdadn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-24_05,2023-08-22_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hariprasad Kelam Suppose user has enabled pfc with prio 0,1 on a PF netdev(eth0) dcb pfc set dev eth0 prio-pfc o:on 1:on later user enabled pfc priorities 2 and 3 on the VF interface(eth1) dcb pfc set dev eth1 prio-pfc 2:on 3:on Instead of enabling pfc on all priorities (0..3), the driver only enables on priorities 2,3. This patch corrects the issue by using the proper CSR address. Fixes: b9d0fedc6234 ("octeontx2-af: cn10kb: Add RPM_USX MAC support") Signed-off-by: Hariprasad Kelam --- drivers/net/ethernet/marvell/octeontx2/af/rpm.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/net/= ethernet/marvell/octeontx2/af/rpm.c index b4fcb20c3f4f..af21e2030cff 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c @@ -355,8 +355,8 @@ int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, = u8 tx_pause, =20 void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable) { + u64 cfg, pfc_class_mask_cfg; rpm_t *rpm =3D rpmd; - u64 cfg; =20 /* ALL pause frames received are completely ignored */ cfg =3D rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); @@ -380,9 +380,11 @@ void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id= , bool enable) rpm_write(rpm, 0, RPMX_CMR_CHAN_MSK_OR, ~0ULL); =20 /* Disable all PFC classes */ - cfg =3D rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL); + pfc_class_mask_cfg =3D is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL : + RPMX_CMRX_PRT_CBFC_CTL; + cfg =3D rpm_read(rpm, lmac_id, pfc_class_mask_cfg); cfg =3D FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg); - rpm_write(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL, cfg); + rpm_write(rpm, lmac_id, pfc_class_mask_cfg, cfg); } =20 int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat) @@ -605,8 +607,11 @@ int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx= _pause, u8 rx_pause, u16 p if (!is_lmac_valid(rpm, lmac_id)) return -ENODEV; =20 + pfc_class_mask_cfg =3D is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL : + RPMX_CMRX_PRT_CBFC_CTL; + cfg =3D rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); - class_en =3D rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL); + class_en =3D rpm_read(rpm, lmac_id, pfc_class_mask_cfg); pfc_en |=3D FIELD_GET(RPM_PFC_CLASS_MASK, class_en); =20 if (rx_pause) { @@ -635,10 +640,6 @@ int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx= _pause, u8 rx_pause, u16 p cfg |=3D RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE; =20 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); - - pfc_class_mask_cfg =3D is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL : - RPMX_CMRX_PRT_CBFC_CTL; - rpm_write(rpm, lmac_id, pfc_class_mask_cfg, class_en); =20 return 0; --=20 2.25.1