From nobody Fri Sep 20 14:25:20 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E17BEE4993 for ; Wed, 23 Aug 2023 15:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236911AbjHWPOi (ORCPT ); Wed, 23 Aug 2023 11:14:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234562AbjHWPOI (ORCPT ); Wed, 23 Aug 2023 11:14:08 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBDA2CEE for ; Wed, 23 Aug 2023 08:14:05 -0700 (PDT) X-UUID: ad94ed2c41c711ee9cb5633481061a41-20230823 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IS1+7vTms66ISvJXGfEcHoWuNeX/Ou5/n7YiEV19ic4=; b=lXCr3as6QbTpWvMVjcN6Z+2AlBZY1PRPw6oGRj8ku2DFFUKPkTF6f3IaJBicobWG0enJyfvY2oGnkFHzor+vXu2X/4ku0fYw9K88gNmp5sXqJJcQSjfMxl4Mwi78XO1RiW1s8Mky5NzWmQAPenxaconVgamggpSSx5MZ/1VRFOo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:d7c4b41c-3dc7-4e49-a1a7-4fe2957ba6c9,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.31,REQID:d7c4b41c-3dc7-4e49-a1a7-4fe2957ba6c9,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:0ad78a4,CLOUDID:a604ab1f-33fd-4aaa-bb43-d3fd68d9d5ae,B ulkID:230823231358XFRU34KR,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_SDM,TF_CID_SPAM_ASC,TF_CID_SPAM_FAS, TF_CID_SPAM_FSD X-UUID: ad94ed2c41c711ee9cb5633481061a41-20230823 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 135248443; Wed, 23 Aug 2023 23:13:56 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 23 Aug 2023 23:13:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 23 Aug 2023 23:13:54 +0800 From: Hsiao Chien Sung To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Jassi Brar CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH 15/15] drm/mediatek: Fix errors when reporting rotation capability Date: Wed, 23 Aug 2023 23:13:32 +0800 Message-ID: <20230823151332.28811-16-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230823151332.28811-1-shawn.sung@mediatek.com> References: <20230823151332.28811-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For CRTCs that doesn't support rotation should still return DRM_MODE_ROTATE_0. Since both OVL and OVL adaptor on MTK chip doesn't support rotation, return the capability of the hardware accordingly. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 8 +------- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 5 +++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 +- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 014086d4d7ca..2772423ce0c0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -121,6 +121,7 @@ void mtk_ovl_adaptor_register_vblank_cb(struct device *= dev, void (*vblank_cb)(vo void mtk_ovl_adaptor_unregister_vblank_cb(struct device *dev); void mtk_ovl_adaptor_enable_vblank(struct device *dev); void mtk_ovl_adaptor_disable_vblank(struct device *dev); +unsigned int mtk_ovl_adaptor_supported_rotations(struct device *dev); void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 453db2de3e83..7a7225604fee 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -437,8 +437,7 @@ unsigned int mtk_ovl_layer_nr(struct device *dev) =20 unsigned int mtk_ovl_supported_rotations(struct device *dev) { - return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | - DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; + return DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; } =20 int mtk_ovl_layer_check(struct device *dev, unsigned int idx, @@ -451,11 +450,6 @@ int mtk_ovl_layer_check(struct device *dev, unsigned i= nt idx, DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y); - rotation &=3D ~DRM_MODE_ROTATE_0; - - /* We can only do reflection, not rotation */ - if ((rotation & DRM_MODE_ROTATE_MASK) !=3D 0) - return -EINVAL; =20 /* * TODO: Rotating/reflecting YUV buffers is not supported at this time. diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 64f98b26f4ce..ab5e606a390b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -286,6 +286,11 @@ void mtk_ovl_adaptor_register_vblank_cb(struct device = *dev, void (*vblank_cb)(vo (struct drm_crtc *)vblank_cb_data); } =20 +unsigned int mtk_ovl_adaptor_supported_rotations(struct device *dev) +{ + return DRM_MODE_ROTATE_0; +} + void mtk_ovl_adaptor_unregister_vblank_cb(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index 143136491607..5108b75be11a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -414,6 +414,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = =3D { .remove =3D mtk_ovl_adaptor_remove_comp, .get_formats =3D mtk_ovl_adaptor_get_formats, .get_num_formats =3D mtk_ovl_adaptor_get_num_formats, + .supported_rotations =3D mtk_ovl_adaptor_supported_rotations, }; =20 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/med= iatek/mtk_drm_plane.c index dc19827f6927..f848317e34c8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -324,7 +324,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_p= lane *plane, return err; } =20 - if (supported_rotations & ~DRM_MODE_ROTATE_0) { + if (supported_rotations) { err =3D drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, supported_rotations); --=20 2.18.0