From nobody Wed Dec 17 09:06:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 423D1EE4993 for ; Tue, 22 Aug 2023 10:57:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233871AbjHVK5w (ORCPT ); Tue, 22 Aug 2023 06:57:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233815AbjHVK5v (ORCPT ); Tue, 22 Aug 2023 06:57:51 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3721A1B2 for ; Tue, 22 Aug 2023 03:57:50 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-58cb845f2f2so61983427b3.1 for ; Tue, 22 Aug 2023 03:57:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692701869; x=1693306669; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=eMqZtDvlSX07gyZ0u5Dl6BMVcufM2gRGniU6L1WlEwU=; b=Ix94X6F96wzJuSjo8aNRndBwhpicfnsuKrnh/oKMivxMGel4dqf/ogPNg5Cjxvi5nr AB8AM/bRuJIrrA2LkbIZv5WEt0WUI8brlEapCeVt9GCvMcnD3igwxweGtHcPpHjgvUPP pv9/113iyGn0oOkSawXSC5qJDnIB64Zdyu1HfagqXJnoBMRljhv7MafWdZ08MfLITQzj 21J0HSfeNwlbaaDlfi6LLhjcmPouoCOnSrty8NKTE60KbB8hskmCwJ6xGsM/80vkjilK np0gAcI5YY62LjgdlEyDYVZw6pBStWJBQQYAVoUl0Io2mwf/zMAZy8YXueXOcT35V3v2 YuLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692701869; x=1693306669; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=eMqZtDvlSX07gyZ0u5Dl6BMVcufM2gRGniU6L1WlEwU=; b=gdbfC/+9FnNfRsMBXApoeEEINrQBJYavphWU0F3xpQncG2jbWFC9jrUT+uDKekXlau 7rAygigwoZ/3tC0u7YDeX4pcBhB/K2JjA78yMzPTaBNIgG3AOfgSi1H7h6YI/Ogv5OaS XjJpZXChtjjndNiujV2NVw2v0vvDTdyZoQR95c7/GzwjtbfKkoZaHPCJ6khmthPgTtoG lOUpRihb5+TmNLYwQfuvTGms+kUDHBt8OBkROAWbMdr22Xq5amaW6EZS1l3TmxGGRGrm 0egeL12fRvxPfjf4lJUm+2fuFhmRhgUBXtbNnaskzYyCd4NOGXkAQYKjNCuQbIzhWwDD PmAA== X-Gm-Message-State: AOJu0YwAy9RMFeVLsCjJH1TIOWwU9ATpA1E9CfrHi2IgR39jYaGy2ZCA KHjHShIaNNErH2/bnmPbksiv1/vCDCPJ X-Google-Smtp-Source: AGHT+IFl31R48qo4ur1dLKvDtJJz2U6vSie9HrG6LLwP12qhr8EwPDR8M4v6oArRwgOrfdiaqHOQuhpRrYQ8 X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:44ad:3968:8aaa:c4fe]) (user=mshavit job=sendgmr) by 2002:a0d:ec47:0:b0:579:e07c:2798 with SMTP id r7-20020a0dec47000000b00579e07c2798mr95478ywn.2.1692701869478; Tue, 22 Aug 2023 03:57:49 -0700 (PDT) Date: Tue, 22 Aug 2023 18:56:57 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.1.Ib87a2696f25414e0fc39cc22dc74e31a4415c2a1@changeid> Subject: [RFC PATCH v2 1/9] iommu/arm-smmu-v3: group attached devices by smmu From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Always insert a new master in the devices_list besides other masters that belong to the same smmu. This allows code to batch commands by SMMU when iterating over masters that a domain is attached to. Signed-off-by: Michael Shavit --- Changes in v2: - New commit drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 ++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index f17704c35858d..37b9223c145ba 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2382,6 +2382,24 @@ static void arm_smmu_detach_dev(struct arm_smmu_mast= er *master) arm_smmu_write_ctx_desc(master, 0, NULL); } =20 +static void arm_smmu_domain_device_list_add(struct arm_smmu_domain *smmu_d= omain, + struct arm_smmu_master *master) +{ + struct arm_smmu_master *iter; + unsigned long flags; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + if (list_empty(&smmu_domain->devices)) + list_add(&master->domain_head, &smmu_domain->devices); + else { + list_for_each_entry(iter, &smmu_domain->devices, domain_head) + if (iter->smmu =3D=3D master->smmu) + break; + list_add(&master->domain_head, &iter->domain_head); + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); +} + static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device = *dev) { int ret =3D 0; @@ -2435,9 +2453,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) if (smmu_domain->stage !=3D ARM_SMMU_DOMAIN_BYPASS) master->ats_enabled =3D arm_smmu_ats_supported(master); =20 - spin_lock_irqsave(&smmu_domain->devices_lock, flags); - list_add(&master->domain_head, &smmu_domain->devices); - spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + arm_smmu_domain_device_list_add(smmu_domain, master); =20 if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { if (!master->cd_table.cdtab) { --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Wed Dec 17 09:06:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3024DEE4993 for ; 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Tue, 22 Aug 2023 03:57:55 -0700 (PDT) Date: Tue, 22 Aug 2023 18:56:58 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.2.I9e9adbe1cb8164398d7a8f56907e6823fddb45bf@changeid> Subject: [RFC PATCH v2 2/9] iommu/arm-smmu-v3-sva: Move SVA optimization into arm_smmu_tlb_inv_range_asid From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This will allow the optimization to be decided on a per SMMU basis when arm_smmu_tlb_inv_range_asid operates on multiple SMMUs. Signed-off-by: Michael Shavit --- Changes in v2: - New commit drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 ++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 238ede8368d10..53f65a89a55f9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -230,9 +230,8 @@ static void arm_smmu_mm_invalidate_range(struct mmu_not= ifier *mn, */ size =3D end - start; =20 - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM)) - arm_smmu_tlb_inv_range_asid(start, size, smmu_mn->cd->asid, - PAGE_SIZE, false, smmu_domain); + arm_smmu_tlb_inv_range_asid(start, size, smmu_mn->cd->asid, + PAGE_SIZE, false, true, smmu_domain); arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, start, size); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 37b9223c145ba..db4df9d6aef10 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1974,6 +1974,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, =20 void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, size_t granule, bool leaf, + bool skip_btm_capable_devices, struct arm_smmu_domain *smmu_domain) { struct arm_smmu_cmdq_ent cmd =3D { @@ -1985,6 +1986,9 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova, = size_t size, int asid, }, }; =20 + if (skip_btm_capable_devices && + smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM) + return; __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 83d2790b701e7..05599914eb0a0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -751,6 +751,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *smm= u_master, int ssid, void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, size_t granule, bool leaf, + bool skip_btm_capable_devices, struct arm_smmu_domain *smmu_domain); bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd); int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Wed Dec 17 09:06:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CFBAEE49A3 for ; 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Tue, 22 Aug 2023 03:57:59 -0700 (PDT) Date: Tue, 22 Aug 2023 18:56:59 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.3.I0f149f177e5478e28dc3223c2d10729d8f28d53a@changeid> Subject: [RFC PATCH v2 3/9] iommu/arm-smmu-v3: Issue invalidations commands to multiple SMMUs From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Assume that devices in the smmu_domain->domain list that belong to the same SMMU are adjacent to each other in the list. Batch TLB/ATC invalidation commands for an smmu_domain by the SMMU devices that the domain is installed to. Signed-off-by: Michael Shavit --- Changes in v2: - Moved the ARM_SMMU_FEAT_BTM changes into a new prepatory commit .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 6 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 134 +++++++++++++----- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- 3 files changed, 104 insertions(+), 38 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 53f65a89a55f9..fe88a7880ad57 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -112,7 +112,7 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) arm_smmu_write_ctx_desc_devices(smmu_domain, 0, cd); =20 /* Invalidate TLB entries previously associated with that context */ - arm_smmu_tlb_inv_asid(smmu, asid); + arm_smmu_tlb_inv_asid(smmu_domain, asid); =20 xa_erase(&arm_smmu_asid_xa, asid); return NULL; @@ -252,7 +252,7 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) */ arm_smmu_write_ctx_desc_devices(smmu_domain, mm->pasid, &quiet_cd); =20 - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_mn->cd->asid); + arm_smmu_tlb_inv_asid(smmu_domain, smmu_mn->cd->asid); arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, 0, 0); =20 smmu_mn->cleared =3D true; @@ -340,7 +340,7 @@ static void arm_smmu_mmu_notifier_put(struct arm_smmu_m= mu_notifier *smmu_mn) * new TLB entry can have been formed. */ if (!smmu_mn->cleared) { - arm_smmu_tlb_inv_asid(smmu_domain->smmu, cd->asid); + arm_smmu_tlb_inv_asid(smmu_domain, cd->asid); arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, 0, 0); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index db4df9d6aef10..1d072fd38a2d6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -960,15 +960,28 @@ static int arm_smmu_page_response(struct device *dev, } =20 /* Context descriptor manipulation functions */ -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) +void arm_smmu_tlb_inv_asid(struct arm_smmu_domain *smmu_domain, u16 asid) { + struct arm_smmu_device *smmu =3D NULL; + struct arm_smmu_master *master; struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_ASID : CMDQ_OP_TLBI_NH_ASID, .tlbi.asid =3D asid, }; + unsigned long flags; =20 - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, + domain_head) { + if (!smmu) + smmu =3D master->smmu; + if (smmu !=3D master->smmu || + list_is_last(&master->domain_head, &smmu_domain->devices)) { + cmd.opcode =3D smmu->features & ARM_SMMU_FEAT_E2H ? + CMDQ_OP_TLBI_EL2_ASID : CMDQ_OP_TLBI_NH_ASID, + arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + } + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); } =20 static void arm_smmu_sync_cd(struct arm_smmu_master *master, @@ -1811,14 +1824,13 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain = *smmu_domain, int ssid, unsigned long iova, size_t size) { int i; + int ret =3D 0; unsigned long flags; struct arm_smmu_cmdq_ent cmd; + struct arm_smmu_device *smmu =3D NULL; struct arm_smmu_master *master; struct arm_smmu_cmdq_batch cmds; =20 - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) - return 0; - /* * Ensure that we've completed prior invalidation of the main TLBs * before we read 'nr_ats_masters' in case of a concurrent call to @@ -1839,28 +1851,56 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain = *smmu_domain, int ssid, arm_smmu_atc_inv_to_cmd(ssid, iova, size, &cmd); =20 cmds.num =3D 0; - spin_lock_irqsave(&smmu_domain->devices_lock, flags); list_for_each_entry(master, &smmu_domain->devices, domain_head) { if (!master->ats_enabled) continue; + if (!smmu) + smmu =3D master->smmu; + if (smmu !=3D master->smmu || + list_is_last(&master->domain_head, &smmu_domain->devices)) { + ret =3D arm_smmu_cmdq_batch_submit(smmu, &cmds); + if (ret) + break; + cmds.num =3D 0; + } =20 for (i =3D 0; i < master->num_streams; i++) { cmd.atc.sid =3D master->streams[i].id; - arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); } } spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 - return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); + return ret; +} + +static void arm_smmu_tlb_inv_vmid(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_device *smmu =3D NULL; + struct arm_smmu_master *master; + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D CMDQ_OP_TLBI_S12_VMALL, + .tlbi.vmid =3D smmu_domain->s2_cfg.vmid, + }; + unsigned long flags; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, + domain_head) { + if (!smmu) + smmu =3D master->smmu; + if (smmu !=3D master->smmu || + list_is_last(&master->domain_head, &smmu_domain->devices)) + arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); } =20 /* IO_PGTABLE API */ static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain =3D cookie; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_ent cmd; =20 /* * NOTE: when io-pgtable is in non-strict mode, we may get here with @@ -1870,11 +1910,9 @@ static void arm_smmu_tlb_inv_context(void *cookie) * careful, 007. */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); + arm_smmu_tlb_inv_asid(smmu_domain, smmu_domain->cd.asid); } else { - cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + arm_smmu_tlb_inv_vmid(smmu_domain); } arm_smmu_atc_inv_domain(smmu_domain, 0, 0, 0); } @@ -1882,9 +1920,9 @@ static void arm_smmu_tlb_inv_context(void *cookie) static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, unsigned long iova, size_t size, size_t granule, - struct arm_smmu_domain *smmu_domain) + struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu) { - struct arm_smmu_device *smmu =3D smmu_domain->smmu; unsigned long end =3D iova + size, num_pages =3D 0, tg =3D 0; size_t inv_range =3D granule; struct arm_smmu_cmdq_batch cmds; @@ -1949,21 +1987,36 @@ static void arm_smmu_tlb_inv_range_domain(unsigned = long iova, size_t size, size_t granule, bool leaf, struct arm_smmu_domain *smmu_domain) { + struct arm_smmu_device *smmu =3D NULL; + struct arm_smmu_master *master; struct arm_smmu_cmdq_ent cmd =3D { .tlbi =3D { .leaf =3D leaf, }, }; + unsigned long flags; =20 - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid =3D smmu_domain->cd.asid; - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + if (!smmu) + smmu =3D master->smmu; + if (smmu !=3D master->smmu || + list_is_last(&master->domain_head, &smmu_domain->devices)) { + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { + cmd.opcode =3D smmu->features & + ARM_SMMU_FEAT_E2H ? + CMDQ_OP_TLBI_EL2_VA : + CMDQ_OP_TLBI_NH_VA; + cmd.tlbi.asid =3D smmu_domain->cd.asid; + } else { + cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; + cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; + } + __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, + smmu_domain, smmu); + } } - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 /* * Unfortunately, this can't be leaf-only since we may have @@ -1977,19 +2030,33 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova= , size_t size, int asid, bool skip_btm_capable_devices, struct arm_smmu_domain *smmu_domain) { + struct arm_smmu_device *smmu =3D NULL; + struct arm_smmu_master *master; struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA, .tlbi =3D { .asid =3D asid, .leaf =3D leaf, }, }; + unsigned long flags; =20 - if (skip_btm_capable_devices && - smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM) - return; - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + if (!smmu) + smmu =3D master->smmu; + if (smmu !=3D master->smmu || + list_is_last(&master->domain_head, &smmu_domain->devices)) { + if (skip_btm_capable_devices && + smmu->features & ARM_SMMU_FEAT_BTM) + continue; + cmd.opcode =3D smmu->features & ARM_SMMU_FEAT_E2H ? + CMDQ_OP_TLBI_EL2_VA : + CMDQ_OP_TLBI_NH_VA; + __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, + smmu_domain, smmu); + } + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); } =20 static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather, @@ -2523,8 +2590,7 @@ static void arm_smmu_flush_iotlb_all(struct iommu_dom= ain *domain) { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); =20 - if (smmu_domain->smmu) - arm_smmu_tlb_inv_context(smmu_domain); + arm_smmu_tlb_inv_context(smmu_domain); } =20 static void arm_smmu_iotlb_sync(struct iommu_domain *domain, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 05599914eb0a0..b0cf9c33e6bcd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -748,7 +748,7 @@ extern struct arm_smmu_ctx_desc quiet_cd; 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Tue, 22 Aug 2023 03:58:03 -0700 (PDT) Date: Tue, 22 Aug 2023 18:57:00 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.4.I326c62dc062aed8d901d319aa665dbe983c7904c@changeid> Subject: [RFC PATCH v2 4/9] iommu/arm-smmu-v3-sva: Allocate new ASID from installed_smmus From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pick an ASID that is within the supported range of all SMMUs that the domain is installed to. Signed-off-by: Michael Shavit --- (no changes since v1) .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index fe88a7880ad57..92d2f8c4e90a8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -66,6 +66,20 @@ static int arm_smmu_write_ctx_desc_devices(struct arm_sm= mu_domain *smmu_domain, return ret; } =20 +static u32 arm_smmu_domain_max_asid_bits(struct arm_smmu_domain *smmu_doma= in) +{ + struct arm_smmu_master *master; + unsigned long flags; + u32 asid_bits =3D 16; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, + domain_head) + asid_bits =3D min(asid_bits, master->smmu->asid_bits); + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + return asid_bits; +} + /* * Check if the CPU ASID is available on the SMMU side. If a private conte= xt * descriptor is using it, try to replace it. @@ -76,7 +90,6 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) int ret; u32 new_asid; struct arm_smmu_ctx_desc *cd; - struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain; =20 cd =3D xa_load(&arm_smmu_asid_xa, asid); @@ -92,10 +105,12 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) } =20 smmu_domain =3D container_of(cd, struct arm_smmu_domain, cd); - smmu =3D smmu_domain->smmu; =20 - ret =3D xa_alloc(&arm_smmu_asid_xa, &new_asid, cd, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); + ret =3D xa_alloc( + &arm_smmu_asid_xa, &new_asid, cd, + XA_LIMIT(1, + (1 << arm_smmu_domain_max_asid_bits(smmu_domain)) - 1), + GFP_KERNEL); if (ret) return ERR_PTR(-ENOSPC); /* --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Wed Dec 17 09:06:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC242EE49A8 for ; Tue, 22 Aug 2023 10:58:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234058AbjHVK6Y (ORCPT ); Tue, 22 Aug 2023 06:58:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234062AbjHVK6W (ORCPT ); Tue, 22 Aug 2023 06:58:22 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FDACCD8 for ; Tue, 22 Aug 2023 03:58:08 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-58f9db8bc1dso56380817b3.3 for ; Tue, 22 Aug 2023 03:58:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692701888; x=1693306688; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=ZPo4bS6bgF3iXXZFHRw7dDnws1JAiCkzNYGL3i11bCA=; b=G9KK9ylHQI5OWSDfOp+7cRr1Fivor9iPR8DIjXzyjBh044lMNgN1fqnAOfydp6Hhmw kTncI4gWfYaJubVdTrkAK0lAzqIYbcwLYJ5Jn2LBO5EhgPMsU4Nj3H91PzOJRXPr52+T 5Sj2nysxAoFLiMLc/n9zevqR+3/RYVauTWETV9FWRAeIR2qwnyrVqB5wh43B1GqPl9iP tX+ACphS8chVFv5ZnZ4LkuoVuivQmIySAmW4ghHjXZASRC88TJX5az/jegGpffuSHq7r SU6o4J2Lm2nYNPs4qh5fN+XOhBbDWZko7TGPrVTj3I81cYkD9E5v4+LK5AR8RHvS3wgn AORQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692701888; x=1693306688; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ZPo4bS6bgF3iXXZFHRw7dDnws1JAiCkzNYGL3i11bCA=; b=hZL2mZaBfIt4A+27B2o6wvK8c8rL1u/L9dtdRk8LP0oDV+fjxpev+WsLHQlmLhgFlt mvpAjm9vyCcRlcXeh0WYhLQ5gS/p6ZOFkAtxBv7nS6eUwI75/nICmcZazCiCLQ6oVwDV 1XIoblk6KwEmus1AVVSLC5kVVVRnZY6z0GHxOieLJZHbQL0p0OSEDthxc1Z1RFHVNKAK 1Xe7+Io8G3bFif3lfDapoSe2Doq/KhgHweAVS39F8uRfNGC1w6PzfpuLCOaK4OawezVn XYzZRvBpN4XHPZEb8VQdlIX99Ftckl01Ie5wvLnZxysXtVKDNRA7G/K1Nt/1LgP4jbfV aKJw== X-Gm-Message-State: AOJu0YxJRrzXDubWUFPail6j5lRVDxaAv6XoyIEKtgG9QQn7YQgFoFol eauCo9d3IT6EhQd+tlEAu2xbHf38L1XO X-Google-Smtp-Source: AGHT+IGycL7gl1G8U6+jtg4VRe9A9eG9SI5H/YWMDuChD5JZkIw+01izdKdnZi/mhqaqG1fmzSy3xGc6ZnnE X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:44ad:3968:8aaa:c4fe]) (user=mshavit job=sendgmr) by 2002:a05:690c:368b:b0:589:dbc8:3d11 with SMTP id fu11-20020a05690c368b00b00589dbc83d11mr97018ywb.9.1692701888099; Tue, 22 Aug 2023 03:58:08 -0700 (PDT) Date: Tue, 22 Aug 2023 18:57:01 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.5.If0dc099688d13ce9e661a1e4a1339030f243ff39@changeid> Subject: [RFC PATCH v2 5/9] iommu/arm-smmu-v3: Alloc vmid from global pool From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Consistent with how ASIDs are allocated, allocate VMIds from a global pool instead of a per-SMMU pool. This allows the domain to be attached onto multiple SMMUs. Signed-off-by: Michael Shavit --- As discussed in v1 RFC, an alternative would be to support assigning a different VMID/ASID to a domain for each SMMU that it is installed to. This is more flexible but will require more work to achieve. (no changes since v1) drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 +++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 - 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1d072fd38a2d6..9adc2cedd487b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -73,6 +73,7 @@ struct arm_smmu_option_prop { =20 DEFINE_XARRAY_ALLOC1(arm_smmu_asid_xa); DEFINE_MUTEX(arm_smmu_asid_lock); +DEFINE_IDA(arm_smmu_vmid_ida); =20 /* * Special value used by SVA when a process dies, to quiesce a CD without @@ -2130,7 +2131,6 @@ static struct iommu_domain *arm_smmu_domain_alloc(uns= igned type) static void arm_smmu_domain_free(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - struct arm_smmu_device *smmu =3D smmu_domain->smmu; =20 free_io_pgtable_ops(smmu_domain->pgtbl_ops); =20 @@ -2143,7 +2143,7 @@ static void arm_smmu_domain_free(struct iommu_domain = *domain) } else { struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; if (cfg->vmid) - ida_free(&smmu->vmid_map, cfg->vmid); + ida_free(&arm_smmu_vmid_ida, cfg->vmid); } =20 kfree(smmu_domain); @@ -2195,7 +2195,7 @@ static int arm_smmu_domain_finalise_s2(struct arm_smm= u_domain *smmu_domain, typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr; =20 /* Reserve VMID 0 for stage-2 bypass STEs */ - vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, + vmid =3D ida_alloc_range(&arm_smmu_vmid_ida, 1, (1 << smmu->vmid_bits) - = 1, GFP_KERNEL); if (vmid < 0) return vmid; @@ -3169,9 +3169,6 @@ static int arm_smmu_init_strtab(struct arm_smmu_devic= e *smmu) reg =3D smmu->strtab_cfg.strtab_dma & STRTAB_BASE_ADDR_MASK; reg |=3D STRTAB_BASE_RA; smmu->strtab_cfg.strtab_base =3D reg; - - ida_init(&smmu->vmid_map); - return 0; } =20 @@ -3995,7 +3992,6 @@ static void arm_smmu_device_remove(struct platform_de= vice *pdev) iommu_device_sysfs_remove(&smmu->iommu); arm_smmu_device_disable(smmu); iopf_queue_free(smmu->evtq.iopf); - ida_destroy(&smmu->vmid_map); } =20 static void arm_smmu_device_shutdown(struct platform_device *pdev) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index b0cf9c33e6bcd..1661d3252bac5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -670,7 +670,6 @@ struct arm_smmu_device { =20 #define ARM_SMMU_MAX_VMIDS (1 << 16) unsigned int vmid_bits; - struct ida vmid_map; =20 unsigned int ssid_bits; unsigned int sid_bits; --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Wed Dec 17 09:06:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EAC2EE4993 for ; Tue, 22 Aug 2023 10:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234139AbjHVK6f (ORCPT ); Tue, 22 Aug 2023 06:58:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234062AbjHVK6b (ORCPT ); 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Tue, 22 Aug 2023 03:58:12 -0700 (PDT) Date: Tue, 22 Aug 2023 18:57:02 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.6.I100c49a1e2ce915982965a065f95a494c2e9ad28@changeid> Subject: [RFC PATCH v2 6/9] iommu/arm-smmu-v3: check smmu compatibility on attach From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Verify a domain's compatibility with the smmu when it's being attached to a master belonging to a different smmu device. Signed-off-by: Michael Shavit --- Changes in v2: - Access the pgtbl_cfg from the pgtable_ops instead of storing a copy in the arm_smmu_domain. drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 94 +++++++++++++++++---- 1 file changed, 79 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9adc2cedd487b..2f305037b9250 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2213,10 +2213,41 @@ static int arm_smmu_domain_finalise_s2(struct arm_s= mmu_domain *smmu_domain, return 0; } =20 +static int arm_smmu_prepare_pgtbl_cfg(struct arm_smmu_device *smmu, + enum arm_smmu_domain_stage stage, + struct io_pgtable_cfg *pgtbl_cfg) +{ + unsigned long ias, oas; + + switch (stage) { + case ARM_SMMU_DOMAIN_S1: + ias =3D (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; + ias =3D min_t(unsigned long, ias, VA_BITS); + oas =3D smmu->ias; + break; + case ARM_SMMU_DOMAIN_NESTED: + case ARM_SMMU_DOMAIN_S2: + ias =3D smmu->ias; + oas =3D smmu->oas; + break; + default: + return -EINVAL; + } + + *pgtbl_cfg =3D (struct io_pgtable_cfg) { + .pgsize_bitmap =3D smmu->pgsize_bitmap, + .ias =3D ias, + .oas =3D oas, + .coherent_walk =3D smmu->features & ARM_SMMU_FEAT_COHERENCY, + .tlb =3D &arm_smmu_flush_ops, + .iommu_dev =3D smmu->dev, + }; + return 0; +} + static int arm_smmu_domain_finalise(struct iommu_domain *domain) { int ret; - unsigned long ias, oas; enum io_pgtable_fmt fmt; struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; @@ -2238,16 +2269,11 @@ static int arm_smmu_domain_finalise(struct iommu_do= main *domain) =20 switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: - ias =3D (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; - ias =3D min_t(unsigned long, ias, VA_BITS); - oas =3D smmu->ias; fmt =3D ARM_64_LPAE_S1; finalise_stage_fn =3D arm_smmu_domain_finalise_s1; break; case ARM_SMMU_DOMAIN_NESTED: case ARM_SMMU_DOMAIN_S2: - ias =3D smmu->ias; - oas =3D smmu->oas; fmt =3D ARM_64_LPAE_S2; finalise_stage_fn =3D arm_smmu_domain_finalise_s2; break; @@ -2255,14 +2281,9 @@ static int arm_smmu_domain_finalise(struct iommu_dom= ain *domain) return -EINVAL; } =20 - pgtbl_cfg =3D (struct io_pgtable_cfg) { - .pgsize_bitmap =3D smmu->pgsize_bitmap, - .ias =3D ias, - .oas =3D oas, - .coherent_walk =3D smmu->features & ARM_SMMU_FEAT_COHERENCY, - .tlb =3D &arm_smmu_flush_ops, - .iommu_dev =3D smmu->dev, - }; + ret =3D arm_smmu_prepare_pgtbl_cfg(smmu, smmu_domain->stage, &pgtbl_cfg); + if (ret) + return ret; =20 pgtbl_ops =3D alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); if (!pgtbl_ops) @@ -2424,6 +2445,48 @@ static void arm_smmu_disable_pasid(struct arm_smmu_m= aster *master) pci_disable_pasid(pdev); } =20 +static int +arm_smmu_verify_domain_compatible(struct arm_smmu_device *smmu, + struct arm_smmu_domain *smmu_domain) +{ + struct io_pgtable_cfg pgtbl_cfg; + struct io_pgtable_cfg *domain_pgtbl_cfg =3D + &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; + int ret; + + if (smmu_domain->domain.type =3D=3D IOMMU_DOMAIN_IDENTITY) + return 0; + + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S2) { + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) + return -EINVAL; + if (smmu_domain->s2_cfg.vmid >> smmu->vmid_bits) + return -EINVAL; + } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) + return -EINVAL; + if (smmu_domain->cd.asid >> smmu->asid_bits) + return -EINVAL; + } + + ret =3D arm_smmu_prepare_pgtbl_cfg(smmu, smmu_domain->stage, &pgtbl_cfg); + if (ret) + return ret; + + if (domain_pgtbl_cfg->ias > pgtbl_cfg.ias || + domain_pgtbl_cfg->oas > pgtbl_cfg.oas || + /* + * The supported pgsize_bitmap must be a superset of the domain's + * pgsize_bitmap. + */ + (domain_pgtbl_cfg->pgsize_bitmap ^ pgtbl_cfg.pgsize_bitmap) & + domain_pgtbl_cfg->pgsize_bitmap || + domain_pgtbl_cfg->coherent_walk !=3D pgtbl_cfg.coherent_walk) + return -EINVAL; + + return 0; +} + static void arm_smmu_detach_dev(struct arm_smmu_master *master) { unsigned long flags; @@ -2505,7 +2568,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) ret =3D arm_smmu_domain_finalise(domain); if (ret) smmu_domain->smmu =3D NULL; - } else if (smmu_domain->smmu !=3D smmu) + } else if (smmu_domain->smmu !=3D smmu || + !arm_smmu_verify_domain_compatible(smmu, smmu_domain)) ret =3D -EINVAL; =20 mutex_unlock(&smmu_domain->init_mutex); --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Wed Dec 17 09:06:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37B17EE4993 for ; Tue, 22 Aug 2023 10:58:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234191AbjHVK6k (ORCPT ); Tue, 22 Aug 2023 06:58:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234115AbjHVK6e (ORCPT ); Tue, 22 Aug 2023 06:58:34 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51630CFC for ; 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Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the usage of arm_smmu_domain->smmu in arm_smmu_domain_finalise as it will be removed in a subsequent commit. Signed-off-by: Michael Shavit --- (no changes since v1) drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 2f305037b9250..7c9897702bcde 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2150,11 +2150,11 @@ static void arm_smmu_domain_free(struct iommu_domai= n *domain) } =20 static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu, struct io_pgtable_cfg *pgtbl_cfg) { int ret; u32 asid; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_c= fg.tcr; =20 @@ -2187,10 +2187,10 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, } =20 static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu, struct io_pgtable_cfg *pgtbl_cfg) { int vmid; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr; =20 @@ -2245,16 +2245,17 @@ static int arm_smmu_prepare_pgtbl_cfg(struct arm_sm= mu_device *smmu, return 0; } =20 -static int arm_smmu_domain_finalise(struct iommu_domain *domain) +static int arm_smmu_domain_finalise(struct iommu_domain *domain, + struct arm_smmu_device *smmu) { int ret; enum io_pgtable_fmt fmt; struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; int (*finalise_stage_fn)(struct arm_smmu_domain *, + struct arm_smmu_device *, struct io_pgtable_cfg *); struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - struct arm_smmu_device *smmu =3D smmu_domain->smmu; =20 if (domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) { smmu_domain->stage =3D ARM_SMMU_DOMAIN_BYPASS; @@ -2293,7 +2294,7 @@ static int arm_smmu_domain_finalise(struct iommu_doma= in *domain) domain->geometry.aperture_end =3D (1UL << pgtbl_cfg.ias) - 1; domain->geometry.force_aperture =3D true; =20 - ret =3D finalise_stage_fn(smmu_domain, &pgtbl_cfg); + ret =3D finalise_stage_fn(smmu_domain, smmu, &pgtbl_cfg); if (ret < 0) { free_io_pgtable_ops(pgtbl_ops); return ret; @@ -2565,7 +2566,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) =20 if (!smmu_domain->smmu) { smmu_domain->smmu =3D smmu; - ret =3D arm_smmu_domain_finalise(domain); + ret =3D arm_smmu_domain_finalise(domain, smmu); if (ret) smmu_domain->smmu =3D NULL; } else if (smmu_domain->smmu !=3D smmu || --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Wed Dec 17 09:06:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAD7EEE4993 for ; Tue, 22 Aug 2023 10:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234167AbjHVK6r (ORCPT ); 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Tue, 22 Aug 2023 03:58:21 -0700 (PDT) Date: Tue, 22 Aug 2023 18:57:04 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.8.I65dd382de382428dcb33333342b35405903ac768@changeid> Subject: [RFC PATCH v2 8/9] iommu/arm-smmu-v3: check for domain initialization using pgtbl_ops From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to remove smmu_domain->smmu in the next commit Signed-off-by: Michael Shavit --- (no changes since v1) drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 7c9897702bcde..9f8b701771fc3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2894,7 +2894,7 @@ static int arm_smmu_enable_nesting(struct iommu_domai= n *domain) int ret =3D 0; =20 mutex_lock(&smmu_domain->init_mutex); - if (smmu_domain->smmu) + if (smmu_domain->pgtbl_ops) ret =3D -EPERM; else smmu_domain->stage =3D ARM_SMMU_DOMAIN_NESTED; --=20 2.42.0.rc1.204.g551eb34607-goog From nobody Wed Dec 17 09:06:27 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46492EE4993 for ; Tue, 22 Aug 2023 10:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234254AbjHVK67 (ORCPT ); Tue, 22 Aug 2023 06:58:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234115AbjHVK65 (ORCPT ); Tue, 22 Aug 2023 06:58:57 -0400 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 090E8196 for ; Tue, 22 Aug 2023 03:58:31 -0700 (PDT) Received: by mail-pj1-x1049.google.com with SMTP id 98e67ed59e1d1-268476c3b2aso6561292a91.1 for ; Tue, 22 Aug 2023 03:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692701906; x=1693306706; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=gv8qs8tb5+ht3xEXCO2MlfdAXc51HHEhUztVM4QYf7k=; b=XxR0LNcd6ZMLLCXEsgVSgiM0m2dvGOpGJ0H2y2I3Ztbzt8plf5Zs/4VNYjeQOFpry+ PH2HqrjjVyT6YxZ0ZowGRVgJRmlhAZziZAfr8pHS5GaUhXmpfF+xIN8sFcmU+VoQt6jf vg3KT/vuCq2HJIN/0b20FjE97XCf5ZOP7uVIA8O/OCVtNAP0HVbSntANTxWg/EcMcSxH R2UP3T6vuQvik0z9gG1HI/Zbn+2pPHPvZv+kPu+c7PlQhUh/60zo8gc/U/LQaRzF5NLz gJKIgjHkQfwHgvdR7MHN1Gw86BsVoxJ55knBkY5sEEGZdpPjIn/teqw7obJvPgVEFyXC Op7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692701906; x=1693306706; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=gv8qs8tb5+ht3xEXCO2MlfdAXc51HHEhUztVM4QYf7k=; b=ak3rqvZW+xS4TDT+LO24DYP75rHZ7PVTymlF69c0/T6VWLqMPr0hxh+su0vzgkcphJ XWWfJzhaj7+b0Mctxx3hZ185HrJRb2k2dFCg7LYn+2f9RjbKfvY38FSLikIP/hVUDGvz kbsEC02kAauwS0tsZRipDhjFt2WEhc/qZaU3f3bTE4baahSRJw9/SymJtvCruB3ry19F LSfQTcyj90J5W9q5KJt/9rG59dIvxSBfMyyhC2PydxYnqoM6cqCkApp91DJFlOshUcL2 HH5Trr1wz/6Fgm6t4khRuBmPfNqK3EUUeR0LDF/VnYYDTS/yOdw6wkuGxOEtBgcFenwQ Ln0g== X-Gm-Message-State: AOJu0YyJeZq6tcjH0gM5wguGhkgzTOWISxUXit7/piy/Sak97XZLap0n dyLGOxWQr8eh7tyc8WCbupnDb6Ax+YLz X-Google-Smtp-Source: AGHT+IHY7P3AGtuprqqUV/dDekDb2kOfyGnlyTzMrT8+CEylyDp3RWzdk6ztQiyu+b0tkcWobWMgKFfrKVgj X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:44ad:3968:8aaa:c4fe]) (user=mshavit job=sendgmr) by 2002:a17:90a:a58f:b0:268:38e3:34f0 with SMTP id b15-20020a17090aa58f00b0026838e334f0mr1756657pjq.2.1692701906060; Tue, 22 Aug 2023 03:58:26 -0700 (PDT) Date: Tue, 22 Aug 2023 18:57:05 +0800 In-Reply-To: <20230822105738.1607365-1-mshavit@google.com> Mime-Version: 1.0 References: <20230822105738.1607365-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230822185632.RFC.v2.9.I5d374dbc818b209e911ef5fbf43de6df0d7ac40b@changeid> Subject: [RFC PATCH v2 9/9] iommu/arm-smmu-v3: allow multi-SMMU domain installs. From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, will@kernel.org, robin.murphy@arm.com, jgg@nvidia.com, Michael Shavit , Dawei Li , Jason Gunthorpe , Joerg Roedel , "Kirill A. Shutemov" , Lu Baolu , Mark Brown Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the arm_smmu_domain->smmu handle now that a domain may be attached to devices with different upstream SMMUs. Signed-off-by: Michael Shavit --- (no changes since v1) drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 +++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +-- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9f8b701771fc3..55c0b8aecfb0a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2564,13 +2564,9 @@ static int arm_smmu_attach_dev(struct iommu_domain *= domain, struct device *dev) =20 mutex_lock(&smmu_domain->init_mutex); =20 - if (!smmu_domain->smmu) { - smmu_domain->smmu =3D smmu; - ret =3D arm_smmu_domain_finalise(domain, smmu); - if (ret) - smmu_domain->smmu =3D NULL; - } else if (smmu_domain->smmu !=3D smmu || - !arm_smmu_verify_domain_compatible(smmu, smmu_domain)) + if (!smmu_domain->pgtbl_ops) + ret =3D arm_smmu_domain_finalise(&smmu_domain->domain, smmu); + else if (!arm_smmu_verify_domain_compatible(smmu, smmu_domain)) ret =3D -EINVAL; =20 mutex_unlock(&smmu_domain->init_mutex); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 1661d3252bac5..fcf3845f4659c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -716,8 +716,7 @@ enum arm_smmu_domain_stage { }; =20 struct arm_smmu_domain { - struct arm_smmu_device *smmu; - struct mutex init_mutex; /* Protects smmu pointer */ + struct mutex init_mutex; /* Protects pgtbl_ops pointer */ =20 struct io_pgtable_ops *pgtbl_ops; atomic_t nr_ats_masters; --=20 2.42.0.rc1.204.g551eb34607-goog