From nobody Wed Dec 17 10:59:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 681D2EE49A3 for ; Tue, 22 Aug 2023 16:20:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237665AbjHVQUH (ORCPT ); Tue, 22 Aug 2023 12:20:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237614AbjHVQUF (ORCPT ); Tue, 22 Aug 2023 12:20:05 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E4FA193 for ; Tue, 22 Aug 2023 09:20:03 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 97E941211; Tue, 22 Aug 2023 18:18:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692721124; bh=JrwUDETZB5eMPJTDxOAxu4s6pxxmetjU3ZvnBP+Q+9E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=vJCLO2P3ohgUmaam0xE6l1KCAYaD3FrRslzzklUiA5Wp+RShHzpR4rb24GZVqF7pg 7Ibeoh7tBvPXepmxKVCAnYpjdu6siLD7siFNlp1ZVZu07QjyJAyRMJWzr1TPa1V7Cj QZC0hTiB9bifah6hDKoWHYlHFU4NR/+N2lfVvcdk= From: Tomi Valkeinen Date: Tue, 22 Aug 2023 19:19:34 +0300 Subject: [PATCH v3 01/12] drm/tegra: rgb: Parameterize V- and H-sync polarities MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-1-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Thierry Reding , Thierry Reding X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1899; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=sL6zTXqRvJeIplRfAhFNbyY7r8WIKADc5W6NZoL5o+U=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAqU5MuEmEFpSME7lAO3Fy/cQBYySuCZUqj/ aasICiJWvyJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgKgAKCRD6PaqMvJYe 9Wa2D/9dsXKpNX70WeLAUVLc4MA8l2ppNEaZn495yXdwRF+kWbUwDjoy50fm3mUCXWE+A5p2nXh AyfCv33a6DtYOtWAE9kvmxypkBojQQLcO7tvpJJyy3HKXQFX651ybDvbEeHJbCZo74UXl9Wso8W 0/Rji29G/dYvf7EFr+iy6BbPebSUO5m4cg1sqLDkq+ekhFCVgYK+fj7acmYknIQwMLgKF6Yv8s8 TvTKY08VDE6I/V5kuF5ut44bfmkLyJ7i/XLrQ75P0EevKWE/+qCCm+/B5G+3vsovhq5zb/LMyN3 8puYiYSEqqhh66xGysr4W/jERE1xSaauQwTLOgCpQ4XnZrCy0ApytfhxfZHQgWRy1ApXwqhSnbZ PzRkOcvHEl4jNo7E6+8nVCqv9XtfuikZvzMWqtTCqBRbwq+4L5Elxnv1skoHneo2zz7Sh0nG55N P4vckn3Rj5FIH4nP8DyEJkSTcJKEsSlwkNrQdbcBXaXBUtn+kSFLNErnq4B9VPl0oXU8My8RDlZ 0YU9wOpHGaAkc4Zi68yd3aCnW213mKVKubVUlAPL25+/MhJeprBS8YGuzKoSljx9ei4njz1FDPg G0UUvCNrV1BbGNXtgxIHnomHi4KwYxPKRvxg/PMg8k50z/lBwiJqffXZNKcOSD/1RTD552DEHAV yPCJJz5uQ1eTRBA== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thierry Reding The polarities of the V- and H-sync signals are encoded as flags in the display mode, so use the existing information to setup the signals for the RGB interface. Signed-off-by: Thierry Reding Cc: Thierry Reding [tomi.valkeinen@ideasonboard.com: default to positive sync] Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/tegra/rgb.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c index 79566c9ea8ff..fc66bbd913b2 100644 --- a/drivers/gpu/drm/tegra/rgb.c +++ b/drivers/gpu/drm/tegra/rgb.c @@ -99,6 +99,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder = *encoder) =20 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder) { + struct drm_display_mode *mode =3D &encoder->crtc->state->adjusted_mode; struct tegra_output *output =3D encoder_to_output(encoder); struct tegra_rgb *rgb =3D to_rgb(output); u32 value; @@ -108,10 +109,19 @@ static void tegra_rgb_encoder_enable(struct drm_encod= er *encoder) value =3D DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); =20 - /* XXX: parameterize? */ + /* configure H- and V-sync signal polarities */ value =3D tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); - value &=3D ~LVS_OUTPUT_POLARITY_LOW; - value &=3D ~LHS_OUTPUT_POLARITY_LOW; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + value |=3D LHS_OUTPUT_POLARITY_LOW; + else + value &=3D ~LHS_OUTPUT_POLARITY_LOW; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + value |=3D LVS_OUTPUT_POLARITY_LOW; + else + value &=3D ~LVS_OUTPUT_POLARITY_LOW; + tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); =20 /* XXX: parameterize? */ --=20 2.34.1