From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 681D2EE49A3 for ; Tue, 22 Aug 2023 16:20:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237665AbjHVQUH (ORCPT ); Tue, 22 Aug 2023 12:20:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237614AbjHVQUF (ORCPT ); Tue, 22 Aug 2023 12:20:05 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E4FA193 for ; Tue, 22 Aug 2023 09:20:03 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 97E941211; Tue, 22 Aug 2023 18:18:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692721124; bh=JrwUDETZB5eMPJTDxOAxu4s6pxxmetjU3ZvnBP+Q+9E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=vJCLO2P3ohgUmaam0xE6l1KCAYaD3FrRslzzklUiA5Wp+RShHzpR4rb24GZVqF7pg 7Ibeoh7tBvPXepmxKVCAnYpjdu6siLD7siFNlp1ZVZu07QjyJAyRMJWzr1TPa1V7Cj QZC0hTiB9bifah6hDKoWHYlHFU4NR/+N2lfVvcdk= From: Tomi Valkeinen Date: Tue, 22 Aug 2023 19:19:34 +0300 Subject: [PATCH v3 01/12] drm/tegra: rgb: Parameterize V- and H-sync polarities MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-1-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Thierry Reding , Thierry Reding X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1899; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=sL6zTXqRvJeIplRfAhFNbyY7r8WIKADc5W6NZoL5o+U=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAqU5MuEmEFpSME7lAO3Fy/cQBYySuCZUqj/ aasICiJWvyJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgKgAKCRD6PaqMvJYe 9Wa2D/9dsXKpNX70WeLAUVLc4MA8l2ppNEaZn495yXdwRF+kWbUwDjoy50fm3mUCXWE+A5p2nXh AyfCv33a6DtYOtWAE9kvmxypkBojQQLcO7tvpJJyy3HKXQFX651ybDvbEeHJbCZo74UXl9Wso8W 0/Rji29G/dYvf7EFr+iy6BbPebSUO5m4cg1sqLDkq+ekhFCVgYK+fj7acmYknIQwMLgKF6Yv8s8 TvTKY08VDE6I/V5kuF5ut44bfmkLyJ7i/XLrQ75P0EevKWE/+qCCm+/B5G+3vsovhq5zb/LMyN3 8puYiYSEqqhh66xGysr4W/jERE1xSaauQwTLOgCpQ4XnZrCy0ApytfhxfZHQgWRy1ApXwqhSnbZ PzRkOcvHEl4jNo7E6+8nVCqv9XtfuikZvzMWqtTCqBRbwq+4L5Elxnv1skoHneo2zz7Sh0nG55N P4vckn3Rj5FIH4nP8DyEJkSTcJKEsSlwkNrQdbcBXaXBUtn+kSFLNErnq4B9VPl0oXU8My8RDlZ 0YU9wOpHGaAkc4Zi68yd3aCnW213mKVKubVUlAPL25+/MhJeprBS8YGuzKoSljx9ei4njz1FDPg G0UUvCNrV1BbGNXtgxIHnomHi4KwYxPKRvxg/PMg8k50z/lBwiJqffXZNKcOSD/1RTD552DEHAV yPCJJz5uQ1eTRBA== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thierry Reding The polarities of the V- and H-sync signals are encoded as flags in the display mode, so use the existing information to setup the signals for the RGB interface. Signed-off-by: Thierry Reding Cc: Thierry Reding [tomi.valkeinen@ideasonboard.com: default to positive sync] Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/tegra/rgb.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c index 79566c9ea8ff..fc66bbd913b2 100644 --- a/drivers/gpu/drm/tegra/rgb.c +++ b/drivers/gpu/drm/tegra/rgb.c @@ -99,6 +99,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder = *encoder) =20 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder) { + struct drm_display_mode *mode =3D &encoder->crtc->state->adjusted_mode; struct tegra_output *output =3D encoder_to_output(encoder); struct tegra_rgb *rgb =3D to_rgb(output); u32 value; @@ -108,10 +109,19 @@ static void tegra_rgb_encoder_enable(struct drm_encod= er *encoder) value =3D DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); =20 - /* XXX: parameterize? */ + /* configure H- and V-sync signal polarities */ value =3D tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); - value &=3D ~LVS_OUTPUT_POLARITY_LOW; - value &=3D ~LHS_OUTPUT_POLARITY_LOW; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + value |=3D LHS_OUTPUT_POLARITY_LOW; + else + value &=3D ~LHS_OUTPUT_POLARITY_LOW; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + value |=3D LVS_OUTPUT_POLARITY_LOW; + else + value &=3D ~LVS_OUTPUT_POLARITY_LOW; + tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); =20 /* XXX: parameterize? */ --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07FABEE4993 for ; Tue, 22 Aug 2023 16:20:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237670AbjHVQUL (ORCPT ); Tue, 22 Aug 2023 12:20:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237657AbjHVQUG (ORCPT ); Tue, 22 Aug 2023 12:20:06 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58397137 for ; Tue, 22 Aug 2023 09:20:05 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id D1C7836B0; Tue, 22 Aug 2023 18:18:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692721125; bh=H9tKJAtqfyF3Tg+LrApw0c7XP90L7b2wllmYTxOJ35w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ndqigfXnut1kEzuR/hcGMtal8PW1O0+gCoO2JCZrG8aUGdUb+qWy2CzWOeDtmtGWX gxVf/QzytMw0j0KXQ91XB7Fq2LIrIGJCXJwqYY7TjbuOPDzk9OT2d/XdZP5cPRIzY/ DIkd5seolSSoC6tkaAJNMI8ufn5eVeGmQf3ztbWE= From: Tomi Valkeinen Date: Tue, 22 Aug 2023 19:19:35 +0300 Subject: [PATCH v3 02/12] drm/bridge: tc358768: Fix use of uninitialized variable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-2-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=965; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=H9tKJAtqfyF3Tg+LrApw0c7XP90L7b2wllmYTxOJ35w=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAr2Jb15icUZGZo0Hl9/ue+3pkcbi4HlgH7B Tmv48jgIBGJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgKwAKCRD6PaqMvJYe 9V6VEACakcIJsHgJjcr2+GAA7F7X27NlUhZEIzY77K8qGEdkCdBckE7GllkTNo2qoXMhv80njGS 5ZC/E7QxEAWWjZzfjJsg2cMgf1zIrXr8b6GAJlXxHpJjwQj/9KLA4hmEUqpAsctmMx0QOD/5P9j SZ2ozfGiZIRzQgESVtBgWWzye/kqVzW98RnMa1Ztyv9OeMo58xrAgzW0t8JW3sbFGdLI1n/x8l3 dZ832wby6NrY/h7ZA/g1RlzlLFFT7yXScL3xz+009iOt2ehFi112/jdzoDkXalxhT5dymyhpSCM N1sRcex+HiZCtKBS7ghqspNj8u86YZdBQwUC2q6/DeXEFYBww834jOhZhUS9cW9vwzFj5ozpMpg mvUHe+y1DMiWcGDebJd77UksSQMUKtgjlZs7OxBH3a5pg0DXlFPW+lpdkVLZdDUFCJaXeHsI2ns fWs/YR39+1w/WvpyLhUShEcVoaRehtF3tzg1qvsXYnd662rUEl8LxzSeqNTQ5NRRHhXuG6fmvLE g0manHm5v8CKSo5I043WDOrS+JVxic5/ZBqes6zKmtcHMoTArvhT3Y2+2asbwnYKbEZISSQAVtH 5qepUgw3uEPF5JVi4p1bbdlLby86b9PIfYSmS+bRb/VMLHJ04pguEpoGuI7jsdUD2PVc/bmHMBX lMfxCCmCfdYz0dw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org smatch reports: drivers/gpu/drm/bridge/tc358768.c:223 tc358768_update_bits() error: uniniti= alized symbol 'orig'. Fix this by bailing out from tc358768_update_bits() if the tc358768_read() produces an error. Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 819a4b6ec2a0..bc97a837955b 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -216,6 +216,10 @@ static void tc358768_update_bits(struct tc358768_priv = *priv, u32 reg, u32 mask, u32 tmp, orig; =20 tc358768_read(priv, reg, &orig); + + if (priv->error) + return; + tmp =3D orig & ~mask; tmp |=3D val & mask; if (tmp !=3D orig) --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B07BEE4996 for ; Tue, 22 Aug 2023 16:20:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237675AbjHVQUM (ORCPT ); Tue, 22 Aug 2023 12:20:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237662AbjHVQUH (ORCPT ); Tue, 22 Aug 2023 12:20:07 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 938B6193 for ; Tue, 22 Aug 2023 09:20:05 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ED89A396B; Tue, 22 Aug 2023 18:18:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692721126; bh=i2HNd7b6c0+SS31D7H33sfozItm4ogRGGiR+cHco6Pg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VbguhQGhGkUMoaJ+sEYUqA+oppNqRChCPSMblBcPV2MrMr1SeErdLtueixF+CKmcK ZzZZQFYc/ASVhIAU6hKVP4Z3AQOWd2cIw5wiLRZJWP6Kf4K72YCgFNOm4a+c9uS/t+ 8G+ff5AnxpC0oqYeHXQ6JZXcd3qH9QQ85UNd3kJE= From: Tomi Valkeinen Date: Tue, 22 Aug 2023 19:19:36 +0300 Subject: [PATCH v3 03/12] drm/bridge: tc358768: Default to positive h/v syncs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-3-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1641; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=i2HNd7b6c0+SS31D7H33sfozItm4ogRGGiR+cHco6Pg=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OArZOTa0MBh6DjLpQLuLnOI1/+Vn3Ue5STCL 09Qm45WL/OJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgKwAKCRD6PaqMvJYe 9cgeD/9LznZrNM/mPS/mWfeakHjq0U8b74PtV13c2KaVaph/y22CM55QSHh4AjIfSupvk4xzbq5 fTSVn/6zjB+en39eP/JmNPV9AafqEeyXOBBfoMoAwPSX+1/M/EQMIVDR/Q5c544fdKqhQL5QTqa QQGyp6wRJzWJ+pX6Gg6+OQgkIO0QYv4DQAZEq/OfHXysRPZl16aCTQjeDzsh8Q97Jb+k3Sp5tFH xAj80sgJ/Iyz6am6JYl+fwTrGTx5S4O0vsmTw82CNO/WIpUD3Y8r7dH4Ut8WB8Y3/GXsPY3//E4 bzNtCFzBaRrQL1U+nGXcdycLlmPJ+DKSAQtNgIO5mxLHWY0PpvdRYNP5HfLnCKb0wQSwo2T86iw 5BF047ZNmR0Ppu0IAOXrB551/StUy7/0uivZpecuNkp8w23DuOxcaqyaDiBZ+v/1Jx8jMYnPYL9 GZgVnv2FWMBzOP7ng7/6IOBJ17acSfrm7DNw+daEPKJpErPeyf1QdwOVQka97HY84dPlnhmu8uS Oc1tE+mY8buN5xX7p9R7CpvYdgwsG+INaQwUlsgL3qtFvXujsuXX3nxnN2cjEpWIjbKIaeMwlPJ QhsaPxF89YSo5qqGHvQBCGCuqYTI2CHIrQNHkECj7B1bjvC4l5Fvtfjpm2FcHZsMhnmkMIU+Gby 7tEFyQd+3P286WA== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As the TC358768 is a DPI to DSI bridge, the DSI side does not need to define h/v sync polarities. This means that sometimes we have a mode without defined sync polarities, which does not work on the DPI side. Add a mode_fixup hook to default to positive sync polarities. Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index bc97a837955b..963ac550509b 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -963,9 +963,27 @@ tc358768_atomic_get_input_bus_fmts(struct drm_bridge *= bridge, return input_fmts; } =20 +static bool tc358768_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + /* Default to positive sync */ + + if (!(adjusted_mode->flags & + (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) + adjusted_mode->flags |=3D DRM_MODE_FLAG_PHSYNC; + + if (!(adjusted_mode->flags & + (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) + adjusted_mode->flags |=3D DRM_MODE_FLAG_PVSYNC; + + return true; +} + static const struct drm_bridge_funcs tc358768_bridge_funcs =3D { .attach =3D tc358768_bridge_attach, .mode_valid =3D tc358768_bridge_mode_valid, + .mode_fixup =3D tc358768_mode_fixup, .pre_enable =3D tc358768_bridge_pre_enable, .enable =3D tc358768_bridge_enable, .disable =3D tc358768_bridge_disable, --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4227EE4993 for ; Tue, 22 Aug 2023 16:20:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237688AbjHVQUQ (ORCPT ); Tue, 22 Aug 2023 12:20:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236596AbjHVQUK (ORCPT ); Tue, 22 Aug 2023 12:20:10 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50935CE7 for ; Tue, 22 Aug 2023 09:20:07 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 1492D87E0; Tue, 22 Aug 2023 18:18:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692721128; bh=oiBuwIaPMPE+jS3H7n/2pUtTE6Vc2yzE7HECj902nxU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EzxZlWVIeYSKn/4nUdgNYrkW56Ui7W5yQi3XQ7RaYewIaHbIrv/Nda7H5JgtzuC59 CAkxNOgFp8Ujye6Q7QRybLecRvKhKgZYjZk5E9UL3tdaQWkVfxL+dvUnjdC1DV2Zie ZOwFAS+nE8JvMJ0256zKJRjucX4+25LpHTk5lO2E= From: Tomi Valkeinen Date: Tue, 22 Aug 2023 19:19:37 +0300 Subject: [PATCH v3 04/12] drm/bridge: tc358768: Fix bit updates MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-4-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2022; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=oiBuwIaPMPE+jS3H7n/2pUtTE6Vc2yzE7HECj902nxU=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAr8GpwKXhNo0EzpZhs7CgeXIe5yS51dSq+h kLEVSIuawOJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgKwAKCRD6PaqMvJYe 9YjWEACAFAp2icbhM5YxVPRVxXacwjSPc4w50GnByzqLcxBzVOdyTHT7LCws0BTZ9lV/krurxOM oDlUFUnveSQp+/VrYa4qhmu0OSAecPiu6W87RbV+2ZiqJlylngmqjDwuEPkcCbqftvMhRCyXux/ zn1IqkOZqwUy1fZ6mMVGnnVqK/kaPAQ0Z9YzmVUdIpcRxsjy8GlxO6eBafV1zN05a324RAQpAs1 3EbLaHoCsC89xaXfr3JWqWCoDcFYpKaW7I43arBSv1vdYkVZ8e4cr1BgNF5AE1VMzoj+MCF4Ve9 AZGgQNV971ajReSC5nPuaE04EI7RZVIyl3bxC9tqJ6OMHFDeZ59Q5Csjh4ae6eobm08mizX81OY vFXwEBzXQscrGTiAfOFp3QrU+LrGofhCeqIVURBij+bGmN+PLGjwED74Ez8M92kYaiFcc2yjrQ4 tDGTiRlE9dO7Ya90ErJjcxYTJA1RUtynnRs5JYW5HQc6ki/8/dwZCwmunhRp+rLfJzkXfHVtYzA zznxQ2oVRUMauZeDF9kPmotyA/xCAmqD4GwXCXxPLf7VUVFdAn6pKRSJ8Mffty19cU/06+UaL/N 1LH0GWn7SjPZpRS+DUK8knDFf2buZUA32elkVgwMP365PWN321gHUypKtoK7wL41GB6JWMfnq2L Ek9jJHHqO26Iu0w== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver has a few places where it does: if (thing_is_enabled_in_config) update_thing_bit_in_hw() This means that if the thing is _not_ enabled, the bit never gets cleared. This affects the h/vsyncs and continuous DSI clock bits. Fix the driver to always update the bit. Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 963ac550509b..99992af23f1e 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -794,8 +794,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) val |=3D BIT(i + 1); tc358768_write(priv, TC358768_HSTXVREGEN, val); =20 - if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) - tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); + tc358768_write(priv, TC358768_TXOPTIONCNTRL, + (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ val =3D tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); @@ -861,11 +861,12 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_DSI_HACT, hact); =20 /* VSYNC polarity */ - if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) - tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); + tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), + (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); + /* HSYNC polarity */ - if (mode->flags & DRM_MODE_FLAG_PHSYNC) - tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); + tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), + (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0); =20 /* Start DSI Tx */ tc358768_write(priv, TC358768_DSI_START, 0x1); --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D291AEE49AC for ; Tue, 22 Aug 2023 16:20:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237693AbjHVQUT (ORCPT ); Tue, 22 Aug 2023 12:20:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237667AbjHVQUK (ORCPT ); Tue, 22 Aug 2023 12:20:10 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92DE9CDF for ; Tue, 22 Aug 2023 09:20:07 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 3162687E1; Tue, 22 Aug 2023 18:18:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692721129; bh=PZWyhC5dbXtcQIPCQnixR51q/63Hv20ub79Oc4c8dPc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tD8AtyDbESZPURfG7WTY47Qldu86Yh9/JRnPZTeCf0PKuZ4GCggMXC+/B7YlDxW3b /MS3a6YER5acYSXvon9auNZV6aYOX/us3izob9b2NGqHifBVCNaPvqW/lCiCclIvJ3 iwB5G76RWD5ezM3B+BVLtAMqyXp1/tKK7/UfGOUA= From: Tomi Valkeinen Date: Tue, 22 Aug 2023 19:19:38 +0300 Subject: [PATCH v3 05/12] drm/bridge: tc358768: Cleanup PLL calculations MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-5-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2543; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=PZWyhC5dbXtcQIPCQnixR51q/63Hv20ub79Oc4c8dPc=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAsXsMFM7hC1l9gz3dS7LioxUL6d6mGfbglO D15zCBtIWKJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgLAAKCRD6PaqMvJYe 9Q/qD/wNTI5SV6F0s47NHHdMSlmVAYcBZE4u8Sv+xyasR172qllVfKjZASiT7qccB3EAtkUnYBG W1DlhQCgNXVYgU+i0X2QSMwElJxeOiSGjP6hrZ12Tc1Prhjq61fp+EDdxV/azo6A05F42thRGTs lRtttA5YUGOENZAFku7aPq896Yal6654a8sjRK0kMW/kwk5qSs+Thn4Xo36lS9OjuBeKR+3tXWA Is39dd6U3Wwc+jEappVufAPkpg9SMPg2S3v56AR04upIsM73whD7ID1DlaxOpyEAnRW+Wt++yOw wjDuiw/feUm744HfQ+KQgTtpwQ69/zD0VWFVUv2fsoDHRIjCiFeF879K7oXbywqPoYLQIY6QE3B aZR986ewMnGw1aRicCCXbSpOVP1lAznR1zYDKQQ/jaNMn95+y5G84IrBH9yUba2t65jzwd5uPqh w7ZzPevn8gX18z+qGLADxjIwOxI23QmykS2tqSUIZbe/8+BAKLjvBCuyIQteI2UGAcOKTu9B2/b Fus8YSRQaEw0w+vFm9kTN8uJdmv7eFbPWEthh0rrRLYOd0IhA3v03iiWaKLCad9mviq7u0n3469 EL52GZiNPvZ0iLnXtSKjjHrP4W2xym1rPsziytuqBGkeu6Ydpz527pe6l0u/mkskgfYKZ5iCYi0 K02hlPMrPkLSUWw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As is quite common, some of TC358768's PLL register fields are to be programmed with (value - 1). Specifically, the FBD and PRD, multiplier and divider, are such fields. However, what the driver currently does is that it considers that the formula used for PLL rate calculation is: RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] where FBD and PRD are values directly from the registers, while a more sensible way to look at it is: RefClk * FBD / PRD * (1 / (2^FRS)) and when the FBD and PRD values are written to the registers, they will be subtracted by one. Change the driver accordingly, as it simplifies the PLL code. Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 99992af23f1e..a465674f1e2e 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -316,7 +316,7 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, =20 target_pll =3D tc358768_pclk_to_pll(priv, mode->clock * 1000); =20 - /* pll_clk =3D RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */ + /* pll_clk =3D RefClk * FBD / PRD * (1 / (2^FRS)) */ =20 for (i =3D 0; i < ARRAY_SIZE(frs_limits); i++) if (target_pll >=3D frs_limits[i]) @@ -336,19 +336,19 @@ static int tc358768_calc_pll(struct tc358768_priv *pr= iv, best_prd =3D 0; best_fbd =3D 0; =20 - for (prd =3D 0; prd < 16; ++prd) { - u32 divisor =3D (prd + 1) * (1 << frs); + for (prd =3D 1; prd <=3D 16; ++prd) { + u32 divisor =3D prd * (1 << frs); u32 fbd; =20 - for (fbd =3D 0; fbd < 512; ++fbd) { + for (fbd =3D 1; fbd <=3D 512; ++fbd) { u32 pll, diff, pll_in; =20 - pll =3D (u32)div_u64((u64)refclk * (fbd + 1), divisor); + pll =3D (u32)div_u64((u64)refclk * fbd, divisor); =20 if (pll >=3D max_pll || pll < min_pll) continue; =20 - pll_in =3D (u32)div_u64((u64)refclk, prd + 1); + pll_in =3D (u32)div_u64((u64)refclk, prd); if (pll_in < 4000000) continue; =20 @@ -611,7 +611,7 @@ static int tc358768_setup_pll(struct tc358768_priv *pri= v, mode->clock * 1000); =20 /* PRD[15:12] FBD[8:0] */ - tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd); + tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); =20 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ tc358768_write(priv, TC358768_PLLCTL1, --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 479F5EE49A3 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-6-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4794; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=/fdTwIinfOD1dWCn53BwEEqB2YEiF7umOj7mqg3kQGQ=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAsMFyHoqmCmk10GeRJyyZo4n7xKVACnmvGD vfojc9l+xGJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgLAAKCRD6PaqMvJYe 9f6bEACq5/CQnJO/Qvxo2o1ZBfTTIX/YBQICBvB/Ty0LyqWUi+2ExBKXXqjU1/VR0xu95sdejWG tz+nNns3Fs7mT400bfUyOv7UucOSgq19N2aWqn+KKFBkOTXIxSbvxWmCGlXUrmcCm1HWFEVI2/K PI1WCy20Jm2u/jrptjk6nEAJyefKmAAfCHHc/og+Pid2B8I/LTfPKfxb9UUque+O3RN/xu4zIb7 eUA6itqpgWYDcE5y3aa8ULHsgYx+i7CHirSi/zn2s86Pzh9T8xc3hJX119mHQAFEErU2sQPNP0V UhnezSdVj7WpbyhYnwTsLRHi2JQXyKowlS1JOoTdIyHSRvnY2gixv81HeqtMgY/z44ArcGN1wK3 j08r28NS4HfDaHObesL/XHE1nehr58rro5dsmqlg2g5dCMVImgg9fXjqgdYU7+hy15q1op7bRgS Byl5Zg8cnuKMB1cCzdzi3gB05NEdsT40itl8AO/ySdf6t25m6hgLMMYeI286+KuEKTI8YPB0aRc MYCtnXvIeY1WU3JP4LvMBfFpWgk6JmV82+HCNWiVQ0Z7hDA1E5U6Ix/PTqu4trfumKriovxLyFi mn0L/VM+F5WpqI2l7m+7NmNKXMcxNUv8hF4PVS+R8R673FwLwCm4EcMmhXRIenNQCavx5lJpEuh zfNfa+s2khpHTkQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The TC358768 documentation uses HFP, HBP, etc. values to deal with the video mode, while the driver currently uses the DRM display mode (htotal, hsync_start, etc). Change the driver to convert the DRM display mode to struct videomode, which then allows us to use the same units the documentation uses. This makes it much easier to work on the code when using the TC358768 documentation as a reference. Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 45 +++++++++++++++++++++--------------= ---- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index a465674f1e2e..b98c517c4726 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -650,6 +650,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) u32 dsiclk, dsibclk, video_start; const u32 internal_delay =3D 40; int ret, i; + struct videomode vm; =20 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling bac= k to continuous\n"); @@ -673,6 +674,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) return; } =20 + drm_display_mode_to_videomode(mode, &vm); + dsiclk =3D priv->dsiclk; dsibclk =3D dsiclk / 4; =20 @@ -681,28 +684,28 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) switch (dsi_dev->format) { case MIPI_DSI_FMT_RGB888: val |=3D (0x3 << 4); - hact =3D mode->hdisplay * 3; - video_start =3D (mode->htotal - mode->hsync_start) * 3; + hact =3D vm.hactive * 3; + video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: val |=3D (0x4 << 4); - hact =3D mode->hdisplay * 3; - video_start =3D (mode->htotal - mode->hsync_start) * 3; + hact =3D vm.hactive * 3; + video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; break; =20 case MIPI_DSI_FMT_RGB666_PACKED: val |=3D (0x4 << 4) | BIT(3); - hact =3D mode->hdisplay * 18 / 8; - video_start =3D (mode->htotal - mode->hsync_start) * 18 / 8; + hact =3D vm.hactive * 18 / 8; + video_start =3D (vm.hsync_len + vm.hback_porch) * 18 / 8; data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; =20 case MIPI_DSI_FMT_RGB565: val |=3D (0x5 << 4); - hact =3D mode->hdisplay * 2; - video_start =3D (mode->htotal - mode->hsync_start) * 2; + hact =3D vm.hactive * 2; + video_start =3D (vm.hsync_len + vm.hback_porch) * 2; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: @@ -814,43 +817,43 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_DSI_EVENT, 0); =20 /* vact */ - tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); + tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); =20 /* vsw */ - tc358768_write(priv, TC358768_DSI_VSW, - mode->vsync_end - mode->vsync_start); + tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len); + /* vbp */ - tc358768_write(priv, TC358768_DSI_VBPR, - mode->vtotal - mode->vsync_end); + tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); =20 /* hsw * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->hsync_end - mode->hsync_start) * + val =3D (u32)div_u64(vm.hsync_len * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 /* hbp * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->htotal - mode->hsync_end) * + val =3D (u32)div_u64(vm.hback_porch * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HBPR, val); } else { /* Set event mode */ tc358768_write(priv, TC358768_DSI_EVENT, 1); =20 /* vact */ - tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); + tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); =20 /* vsw (+ vbp) */ tc358768_write(priv, TC358768_DSI_VSW, - mode->vtotal - mode->vsync_start); + vm.vsync_len + vm.vback_porch); + /* vbp (not used in event mode) */ tc358768_write(priv, TC358768_DSI_VBPR, 0); =20 /* (hsw + hbp) * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->htotal - mode->hsync_start) * + val =3D (u32)div_u64((vm.hsync_len + vm.hback_porch) * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 /* hbp (not used in event mode) */ --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6E9BEE4996 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-7-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4217; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=iDd9OrJ4bpmdl8qtzo/3tkFMlKMFCIwaFWqa4j8y33E=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAsEl6Q8ufgvMP/BxJYbWiuFtQ8WUKiNwJjJ wrxgcoCKdSJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgLAAKCRD6PaqMvJYe 9RjPD/97ZXakRJ9h99taRFa4/PZKCitu2IvkUHsUjHvy9ji47SYpZR1qTv2j4ynzu1UDiQQ1lh8 fi+lx4UaPNhx66JkVI6wxqwPmdrCA4iFgSxhs61c0rp7Ygxp6AKT6UKyP3CQdjy1x4KaAymbrOF /YJZhW6O1LGFMjrqQH6pAsTv3/KuHZeNgMPnzA8eyU4ucFKlunf3GBb83dPUpbQdZ7ODEqa0PK0 6vjP5Sk21klElTlktIR1APF1/GopwFhwOnuTyPAdu7mbqf25PQuPgGZwpjE+oWaE8nXcNgMy/Gz 0959vyRiX6eNRsk5lMS5mAlV3VXIEzkOhNY4iRa98DDpX/9GkWG7+ZvtnVht8ykz/fqXnhCFdqX Oxx6kbFVapjQIn0NoI9rL2pAkrLi8vz4mGQ6mTDslyTLE7pnjkK8pA3Z8jUvk/3XClvRQF870CY VUk9LNr1hixKiYYs/mYX2dKwYTWIILY1T7qYrMwndGASK2B5jmKYzzuo5b76sugUisnuLZUz7KO M+7OuyGHPrYZlOYQXTFZRV8k1tOkQT5gz98PeSAhk8eiwkLFMZswYskSBsNEtnPq1QgRP5wri4g tgAOTdRdyLYk9I+wFX8mprkqdQNEMVrQ4v7TJ1lqEhPCb10TFZaFJUTPM5u514pzoU8KNnLEFCT Di4qhcJeURO7T9g== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver debug prints DSI related timings as raw register values in hex. It is much more useful to see the "logical" value of the timing, not the register value. Change the prints to print the values separately, in case a single register contains multiple values, and use %u to have it in a more human consumable form. Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index b98c517c4726..88060f961064 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -739,57 +739,59 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) =20 /* LP11 > 100us for D-PHY Rx Init */ val =3D tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; - dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val); + dev_dbg(priv->dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ val =3D tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; lptxcnt =3D val; - dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val); + dev_dbg(priv->dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ val =3D tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; + dev_dbg(priv->dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 2; + dev_dbg(priv->dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; - dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_n= sk) - 5; val =3D clamp(raw_val, 0, 127); - dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val); + dev_dbg(priv->dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ val =3D 50 + tc358768_to_ns(4 * ui_nsk); val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; + dev_dbg(priv->dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_= nsk) - 10; val2 =3D clamp(raw_val, 0, 127); + dev_dbg(priv->dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; - dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val); tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ val =3D tc358768_ns_to_cnt(1020000, dsibclk_nsk); val =3D val / (lptxcnt + 1) - 1; - dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val); + dev_dbg(priv->dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), dsibclk_nsk) - 3; - dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val); + dev_dbg(priv->dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), dsibclk_nsk) - 4; val =3D clamp(raw_val, 0, 15); - dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val); + dev_dbg(priv->dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); =20 val =3D BIT(0); @@ -803,10 +805,11 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ val =3D tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1; + dev_dbg(priv->dev, "TXTAGOCNT: %u\n", val); val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), dsibclk_nsk) - 2; + dev_dbg(priv->dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; - dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); tc358768_write(priv, TC358768_BTACNTRL1, val); =20 /* START[0] */ --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF711EE4993 for ; Tue, 22 Aug 2023 16:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237715AbjHVQU2 (ORCPT ); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-8-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6270; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=u+DcBHsth8iLUe90ZutFhI69CnV6usN42nvbbGlJHmY=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAtpG2wc9F+3edvkBQ6jPSLXC9zSp0G7jPP1 AzICicuUreJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgLQAKCRD6PaqMvJYe 9Y+hEACNREARMzt8bh17vPxWQ+OdI3EoHW52AF0afCSAuv+fXr6AvABf14w74bgt1J1T0yShgOJ MKewt/Jh4UFDsdgqIh/20ciOb5XNNwIJ2xlTOEVdtBRdPJJKL6Uc+jH294XaawKTbJwqf88ebg2 /iqmRGxakcrlfdkD8u8lONqthihstjXwoAvkF6Om4hy986CbAJrmdGQBir9XF5ScPPqMqqHNcOk M7/E06XGHP+q+rJNla3O2Yc4EIe2qfWlp6ZRi/gc6C1oqz1LKSIoVJ/ePUoNOH93SKRXOxqPEIO 6VvPEcKSu8mTI2ApszcI1IvR3T6q75vasBHmmsrvVr/7H6yRRC1uLQQfXS5aiaxkeRFbZtYOSKe ae0Nd78PRSHWflde5LMmNjM2F2jjAxzkmomq3aPM9a2nEBVLpPkhVPC1LIq49tebYPD5BqFDVw2 kEBKXAx7K8cUKXFOZHxj1v1lZ3ecBzVVRG9iKiGwLUL+JsGEytGlLfNo553Bt/kf7TxnE2wa+wK Az9ZEos20Y2isguRl9KWMrJsoj3NBWQXeoZcyJO3dMctaiOwGi0lNTGdTQHjzvGco7kK3s8D7Ue Bk1bXgmwf395Gf7Lpc9923yExuTps7yZcIdA240iURAeTCGcpFDwpijtxMf+hbtbu8+DY+Z6CMK VCSHllCCeatBi9Q== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Simplify the code by capturing the priv->dev value to dev variable, and use it. Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 41 ++++++++++++++++++++---------------= ---- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 88060f961064..6297d28250e9 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -651,9 +651,10 @@ static void tc358768_bridge_pre_enable(struct drm_brid= ge *bridge) const u32 internal_delay =3D 40; int ret, i; struct videomode vm; + struct device *dev =3D priv->dev; =20 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { - dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling bac= k to continuous\n"); + dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to c= ontinuous\n"); mode_flags &=3D ~MIPI_DSI_CLOCK_NON_CONTINUOUS; } =20 @@ -661,7 +662,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) =20 ret =3D tc358768_sw_reset(priv); if (ret) { - dev_err(priv->dev, "Software reset failed: %d\n", ret); + dev_err(dev, "Software reset failed: %d\n", ret); tc358768_hw_disable(priv); return; } @@ -669,7 +670,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) mode =3D &bridge->encoder->crtc->state->adjusted_mode; ret =3D tc358768_setup_pll(priv, mode); if (ret) { - dev_err(priv->dev, "PLL setup failed: %d\n", ret); + dev_err(dev, "PLL setup failed: %d\n", ret); tc358768_hw_disable(priv); return; } @@ -709,7 +710,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: - dev_err(priv->dev, "Invalid data format (%u)\n", + dev_err(dev, "Invalid data format (%u)\n", dsi_dev->format); tc358768_hw_disable(priv); return; @@ -733,65 +734,65 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) dsibclk); dsiclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); ui_nsk =3D dsiclk_nsk / 2; - dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk); - dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk); - dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk); + dev_dbg(dev, "dsiclk_nsk: %u\n", dsiclk_nsk); + dev_dbg(dev, "ui_nsk: %u\n", ui_nsk); + dev_dbg(dev, "dsibclk_nsk: %u\n", dsibclk_nsk); =20 /* LP11 > 100us for D-PHY Rx Init */ val =3D tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; - dev_dbg(priv->dev, "LINEINITCNT: %u\n", val); + dev_dbg(dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ val =3D tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; lptxcnt =3D val; - dev_dbg(priv->dev, "LPTXTIMECNT: %u\n", val); + dev_dbg(dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ val =3D tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; - dev_dbg(priv->dev, "TCLK_PREPARECNT %u\n", val); + dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 2; - dev_dbg(priv->dev, "TCLK_ZEROCNT %u\n", val2); + dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_n= sk) - 5; val =3D clamp(raw_val, 0, 127); - dev_dbg(priv->dev, "TCLK_TRAILCNT: %u\n", val); + dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ val =3D 50 + tc358768_to_ns(4 * ui_nsk); val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; - dev_dbg(priv->dev, "THS_PREPARECNT %u\n", val); + dev_dbg(dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_= nsk) - 10; val2 =3D clamp(raw_val, 0, 127); - dev_dbg(priv->dev, "THS_ZEROCNT %u\n", val2); + dev_dbg(dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ val =3D tc358768_ns_to_cnt(1020000, dsibclk_nsk); val =3D val / (lptxcnt + 1) - 1; - dev_dbg(priv->dev, "TWAKEUP: %u\n", val); + dev_dbg(dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), dsibclk_nsk) - 3; - dev_dbg(priv->dev, "TCLK_POSTCNT: %u\n", val); + dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), dsibclk_nsk) - 4; val =3D clamp(raw_val, 0, 15); - dev_dbg(priv->dev, "THS_TRAILCNT: %u\n", val); + dev_dbg(dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); =20 val =3D BIT(0); @@ -805,10 +806,10 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ val =3D tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1; - dev_dbg(priv->dev, "TXTAGOCNT: %u\n", val); + dev_dbg(dev, "TXTAGOCNT: %u\n", val); val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), dsibclk_nsk) - 2; - dev_dbg(priv->dev, "RXTASURECNT: %u\n", val2); + dev_dbg(dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; tc358768_write(priv, TC358768_BTACNTRL1, val); =20 @@ -902,7 +903,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) =20 ret =3D tc358768_clear_error(priv); if (ret) { - dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret); + dev_err(dev, "Bridge pre_enable failed: %d\n", ret); tc358768_bridge_disable(bridge); tc358768_bridge_post_disable(bridge); } --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4943EE49A3 for ; Tue, 22 Aug 2023 16:20:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237701AbjHVQUb (ORCPT ); Tue, 22 Aug 2023 12:20:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237713AbjHVQU0 (ORCPT ); Tue, 22 Aug 2023 12:20:26 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B9A5CF0 for ; Tue, 22 Aug 2023 09:20:12 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id BB48F396B; Tue, 22 Aug 2023 18:18:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692721133; bh=dfvDuc3+OJeVTyiiwUXOv9K+PGAuzxd6tO3qEoOctDw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=X9hYlW9Xjwzwq7eUrYJUdv2nx73lICt9qbFKSviUXdrtQxWkZRWlhUU7eN6uTvs8q Jo9rGSiDCNFP64aFiWBJrr82/y9F4RmOPh2n7r1UvlcufWbq1tK4p+g0Dn2mr0NgHJ I5iCwglI204JlZsZVfqx4gCHTZMStNAL7dSoHFlY= From: Tomi Valkeinen Date: Tue, 22 Aug 2023 19:19:42 +0300 Subject: [PATCH v3 09/12] drm/bridge: tc358768: Rename dsibclk to hsbyteclk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-9-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7362; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=dfvDuc3+OJeVTyiiwUXOv9K+PGAuzxd6tO3qEoOctDw=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAt7iW4LNztF4KjC75OeOjaYehOdMGnRvedl KUHh+2ZEfqJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgLQAKCRD6PaqMvJYe 9Q2ZD/49qnm8OXtFtT5rjgwLRzX9ldGBSxmibb655ooYOEcNpS34mbF9gPQXgJDNFY67/Cz7bQ9 6ou77Zy6+WedlkwwCPP/GJgzO0kQ6+7vyIRaL1QvURNgYwbCItvZE/phhsk0x4eK9D9NoeUsvqD NBd5Ejm+BZ+RHhTIbA7OxhHAU8L9ZuCszLy4IoTAh7Hu6yX/VNJyiNYePeY3OfihdW+xkjhUn4j QjnCfsr6A7ahZnkKrX9OcMgeX0uwEpgqIw2iVHk3PK1pc7p5wT1wWwIOg4fhBTByYHFsU+/BKTf eh6R5TnXhJcbWS4WGEdgbuapeS5OEF4ppNeVSKJqV0zrLR23aidy2WCoM273KhDAWu942cgxVOG KRLBO6IzCfbir+cQ9PvfndMtIoJFQkMGVCGsuU/z6iAGCpZdqIBBtZdZxGTXwFaGW/EulCg5hoJ h8aGstcfFQnxOBhZh5BdbjBPMu6HGPGs9URqSuJ9kDfwuG2bXrltdvqnp9zkJ4E9Y+3s/PE5jIX 6Czd98xnOpsvheZaHex97YSOq/oGJwk8VzWmu4ayugBrua+cnScPfd1zMQ0I52f2J0OETU8wGWv bcb22jSipHERvhL/lvxAe6kVr9iuOzOIFwOcfdf0p6IGpPxn8x4rNuZwFc7uHyWZ+VXeYNHUkbn NjVkkJs/kBa/oaQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Toshiba documentation talks about HSByteClk when referring to the DSI HS byte clock, whereas the driver uses 'dsibclk' name. Also, in a few places the driver calculates the byte clock from the DSI clock, even if the byte clock is already available in a variable. To align the driver with the documentation, change the 'dsibclk' variable to 'hsbyteclk'. This also make it easier to visually separate 'dsibclk' and 'dsiclk' variables. Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 48 +++++++++++++++++++----------------= ---- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 6297d28250e9..0f117d673b14 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -604,7 +604,7 @@ static int tc358768_setup_pll(struct tc358768_priv *pri= v, =20 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", clk_get_rate(priv->refclk), fbd, prd, frs); - dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n", + dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", tc358768_pll_to_pclk(priv, priv->dsiclk * 2), @@ -646,8 +646,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) u32 val, val2, lptxcnt, hact, data_type; s32 raw_val; const struct drm_display_mode *mode; - u32 dsibclk_nsk, dsiclk_nsk, ui_nsk; - u32 dsiclk, dsibclk, video_start; + u32 hsbyteclk_nsk, dsiclk_nsk, ui_nsk; + u32 dsiclk, hsbyteclk, video_start; const u32 internal_delay =3D 40; int ret, i; struct videomode vm; @@ -678,7 +678,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) drm_display_mode_to_videomode(mode, &vm); =20 dsiclk =3D priv->dsiclk; - dsibclk =3D dsiclk / 4; + hsbyteclk =3D dsiclk / 4; =20 /* Data Format Control Register */ val =3D BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ @@ -730,67 +730,67 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); =20 /* DSI Timings */ - dsibclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, - dsibclk); + hsbyteclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, + hsbyteclk); dsiclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); ui_nsk =3D dsiclk_nsk / 2; dev_dbg(dev, "dsiclk_nsk: %u\n", dsiclk_nsk); dev_dbg(dev, "ui_nsk: %u\n", ui_nsk); - dev_dbg(dev, "dsibclk_nsk: %u\n", dsibclk_nsk); + dev_dbg(dev, "hsbyteclk_nsk: %u\n", hsbyteclk_nsk); =20 /* LP11 > 100us for D-PHY Rx Init */ - val =3D tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(100 * 1000, hsbyteclk_nsk) - 1; dev_dbg(dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ - val =3D tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(50, hsbyteclk_nsk) - 1; lptxcnt =3D val; dev_dbg(dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ - val =3D tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(65, hsbyteclk_nsk) - 1; dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), - dsibclk_nsk) - 2; + hsbyteclk_nsk) - 2; dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ - raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_n= sk) - 5; + raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), hsbyteclk= _nsk) - 5; val =3D clamp(raw_val, 0, 127); dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ val =3D 50 + tc358768_to_ns(4 * ui_nsk); - val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) - 1; dev_dbg(dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ - raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_= nsk) - 10; + raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), hsbytecl= k_nsk) - 10; val2 =3D clamp(raw_val, 0, 127); dev_dbg(dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ - val =3D tc358768_ns_to_cnt(1020000, dsibclk_nsk); + val =3D tc358768_ns_to_cnt(1020000, hsbyteclk_nsk); val =3D val / (lptxcnt + 1) - 1; dev_dbg(dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), - dsibclk_nsk) - 3; + hsbyteclk_nsk) - 3; dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), - dsibclk_nsk) - 4; + hsbyteclk_nsk) - 4; val =3D clamp(raw_val, 0, 15); dev_dbg(dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); @@ -804,11 +804,11 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ - val =3D tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); - val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1; + val =3D tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk * 4); + val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) / 4 - 1; dev_dbg(dev, "TXTAGOCNT: %u\n", val); - val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), - dsibclk_nsk) - 2; + val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk), + hsbyteclk_nsk) - 2; dev_dbg(dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; tc358768_write(priv, TC358768_BTACNTRL1, val); @@ -831,13 +831,13 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) =20 /* hsw * byteclk * ndl / pclk */ val =3D (u32)div_u64(vm.hsync_len * - ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + (u64)hsbyteclk * priv->dsi_lanes, vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 /* hbp * byteclk * ndl / pclk */ val =3D (u32)div_u64(vm.hback_porch * - ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + (u64)hsbyteclk * priv->dsi_lanes, vm.pixelclock); tc358768_write(priv, TC358768_DSI_HBPR, val); } else { @@ -856,7 +856,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) =20 /* (hsw + hbp) * byteclk * ndl / pclk */ val =3D (u32)div_u64((vm.hsync_len + vm.hback_porch) * - ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + (u64)hsbyteclk * priv->dsi_lanes, vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4BBEEE49AE for ; Tue, 22 Aug 2023 16:20:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237726AbjHVQUd (ORCPT ); Tue, 22 Aug 2023 12:20:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237724AbjHVQU0 (ORCPT ); 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver defines TC358768_PRECISION as 1000, and uses "nsk" to refer to clock periods. The original author does not remember where all this came from. Effectively the driver is using picoseconds as the unit for clock periods, yet referring to them by "nsk". Clean this up by just saying the periods are in picoseconds. Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 60 +++++++++++++++++++----------------= ---- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 0f117d673b14..9ce8d120b50c 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include #include @@ -627,15 +628,14 @@ static int tc358768_setup_pll(struct tc358768_priv *p= riv, return tc358768_clear_error(priv); } =20 -#define TC358768_PRECISION 1000 -static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk) +static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) { - return (ns * TC358768_PRECISION + period_nsk) / period_nsk; + return (ns * 1000 + period_ps) / period_ps; } =20 -static u32 tc358768_to_ns(u32 nsk) +static u32 tc358768_ps_to_ns(u32 ps) { - return (nsk / TC358768_PRECISION); + return ps / 1000; } =20 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) @@ -646,7 +646,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) u32 val, val2, lptxcnt, hact, data_type; s32 raw_val; const struct drm_display_mode *mode; - u32 hsbyteclk_nsk, dsiclk_nsk, ui_nsk; + u32 hsbyteclk_ps, dsiclk_ps, ui_ps; u32 dsiclk, hsbyteclk, video_start; const u32 internal_delay =3D 40; int ret, i; @@ -730,67 +730,65 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); =20 /* DSI Timings */ - hsbyteclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, - hsbyteclk); - dsiclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); - ui_nsk =3D dsiclk_nsk / 2; - dev_dbg(dev, "dsiclk_nsk: %u\n", dsiclk_nsk); - dev_dbg(dev, "ui_nsk: %u\n", ui_nsk); - dev_dbg(dev, "hsbyteclk_nsk: %u\n", hsbyteclk_nsk); + hsbyteclk_ps =3D (u32)div_u64(PICO, hsbyteclk); + dsiclk_ps =3D (u32)div_u64(PICO, dsiclk); + ui_ps =3D dsiclk_ps / 2; + dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps, + ui_ps, hsbyteclk_ps); =20 /* LP11 > 100us for D-PHY Rx Init */ - val =3D tc358768_ns_to_cnt(100 * 1000, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; dev_dbg(dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ - val =3D tc358768_ns_to_cnt(50, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; lptxcnt =3D val; dev_dbg(dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ - val =3D tc358768_ns_to_cnt(65, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ - val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), - hsbyteclk_nsk) - 2; + val2 =3D tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), + hsbyteclk_ps) - 2; dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ - raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), hsbyteclk= _nsk) - 5; + raw_val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbytec= lk_ps) - 5; val =3D clamp(raw_val, 0, 127); dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ - val =3D 50 + tc358768_to_ns(4 * ui_nsk); - val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) - 1; + val =3D 50 + tc358768_ps_to_ns(4 * ui_ps); + val =3D tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; dev_dbg(dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ - raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), hsbytecl= k_nsk) - 10; + raw_val =3D tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyte= clk_ps) - 10; val2 =3D clamp(raw_val, 0, 127); dev_dbg(dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ - val =3D tc358768_ns_to_cnt(1020000, hsbyteclk_nsk); + val =3D tc358768_ns_to_cnt(1020000, hsbyteclk_ps); val =3D val / (lptxcnt + 1) - 1; dev_dbg(dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ - val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), - hsbyteclk_nsk) - 3; + val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), + hsbyteclk_ps) - 3; dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ - raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), - hsbyteclk_nsk) - 4; + raw_val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), + hsbyteclk_ps) - 4; val =3D clamp(raw_val, 0, 15); dev_dbg(dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); @@ -804,11 +802,11 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ - val =3D tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk * 4); - val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) / 4 - 1; + val =3D tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); + val =3D tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; dev_dbg(dev, "TXTAGOCNT: %u\n", val); - val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk), - hsbyteclk_nsk) - 2; + val2 =3D tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_p= s), + hsbyteclk_ps) - 2; dev_dbg(dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; tc358768_write(priv, TC358768_BTACNTRL1, val); --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDD03EE4996 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-11-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=956; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=LO6DVrF7Wy//586q71JqmvhJ6yqjCtp6tNE4HEdX3hc=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAuWjKWskwExcfKQDmgn/U8rq857fNH5jATm ZR/kqZaJDiJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgLgAKCRD6PaqMvJYe 9ZwAEACr5jOQagaCCvcZpT8sfneYHY7YPSelKldZoR04bQCAK7S5k5aa3SpTIQ/EeTBc53dOjkq ewlV4E2veNj+RKf5HA8f243swDg9tdU4WBj60XglDh1JCKwEgkaWDSYzgZnKtXuH2pz9MGv5oKd VbBaBkEiU3f+AxL+tLLHS5fifFJIJ08ZMSjhLuo82pQYJ9BSOGQPzmDFLkW3kQUgE38rgrHh3mw jEAKEqSbd6c5EejvSEq7ynzJDVB0I4i6iJtiIJuXdVh7uIBwqRdtvRXrpRRHIza2Kg/LRRCwGV4 /OB8+3sRs1HaQzT1o75L+Zro0IJlJBlkDNgJ2DZAkISO1Yfk+83vFod1nhDow5Nmvg7L+rW9fqN RVImT2DTJb9H297Xf9TFVrg96UWwUd9pI2OTsc0xnDo5lNYV45Nq5w6KOacgvfT9v42Zf9c9oC1 mglS612hxEXQg1q3ES2jiwHWpPVp8EaP0qLSryjMKhaVD18dsClBh779ZCG2jNbrx6wakpfHLf4 4DEl1eRGAFULetw0heN5UGHyiw+6J+CGbCQVtX+T6xQHNO0DFSaovXA4twlKXtHdHVHzQ8YVTEG u6xJOQtqgQO/cjNe8MDQQaRt0A2hMoooMU9wqyd4I3OOf2U94/WccXaKBsFzr3SriP+GMOdsiNj LimPFRnaGpghTFQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The tc358768_ns_to_cnt() is, most likely, supposed to do a div-round-up operation, but it misses subtracting one from the dividend. Fix this by just using DIV_ROUND_UP(). Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 9ce8d120b50c..f41bf56b7d6b 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -630,7 +630,7 @@ static int tc358768_setup_pll(struct tc358768_priv *pri= v, =20 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) { - return (ns * 1000 + period_ps) / period_ps; + return DIV_ROUND_UP(ns * 1000, period_ps); } =20 static u32 tc358768_ps_to_ns(u32 ps) --=20 2.34.1 From nobody Wed Dec 17 09:18:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00E7BEE4993 for ; Tue, 22 Aug 2023 16:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237725AbjHVQUm (ORCPT ); Tue, 22 Aug 2023 12:20:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237751AbjHVQUa (ORCPT ); Tue, 22 Aug 2023 12:20:30 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53665E7D for ; Tue, 22 Aug 2023 09:20:18 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 1F8D187E0; Tue, 22 Aug 2023 18:18:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692721137; bh=UCJ7G3SL/2XJgCRc32al7SVXfZM1E9ZVdnanyH+XJS0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lXZRONy2fVQneUKqitEkyktOL0PO5EtVuP/ViIZM3+yTrMhXMzIOdxmwh8bQVdB5Q WJIIauQYkUUiy1IMrglkBDDf2EHaZZ9fk5qM1tIjfCtthm9Jes74t8MY09HV7HNEPX u+hEfSO6v0Cty6K3hG1r6uQYBXv6TenCC2uMYoc4= From: Tomi Valkeinen Date: Tue, 22 Aug 2023 19:19:45 +0300 Subject: [PATCH v3 12/12] drm/bridge: tc358768: Attempt to fix DSI horizontal timings MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230822-tc358768-v3-12-c82405dac0c1@ideasonboard.com> References: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> In-Reply-To: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=11770; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=UCJ7G3SL/2XJgCRc32al7SVXfZM1E9ZVdnanyH+XJS0=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk5OAuS3GEfvOwZ0Ix1SQ07BuuGxi6p6737luU+ 8vc6V3+TJCJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZOTgLgAKCRD6PaqMvJYe 9SLPEACjcZ07UM38SBQXPrwwy0N9AoCv2l2T3y1b20DYU6bGTn3ZoJZT9n05by6IG7GEdmgijfq Jk99g+sbm8ggR2TKNnAmkBM2OwFmtD7PaFieCIPegSHyXRwnvkVlJSRcymX6wzbgVnlZyus8cE+ 3VkkEsIFOTHcPhjLtRYZtfhd08MBsc4yZrdovGrr0drBgiVbPFPrG+O3jzzxGopV7DmiCvZHd12 /auOG2Gpe/ClsvmwMd+zONg4Zwd0qa/kOCvlFdvWpMraykEXIzhrN0nXVVdn3nfu4Oa0kC+HX44 Am4oe2lpy3twsMQWKL6X5xQzB3gDfqavhxL5Kv9pLmOoA5f8pFjXKucgIEGU4wGr+jweBKPYo3N QZZIbKTEn4bdlm6ztT+Aq9qlx+8Mg3mBz9o1w5EEQuN4fEaEMO6zrgr170VC8UZ4FU4kXC3l3Km 68Lc0RVd6ArL3klUZjnAGqV5mLRjSxBaHJTEUrFQUoCnZxRSGBISpg09phWhDWHLXONncaH3mxk hqYTW97TrKbOBe5Wg9E7RAH9+0vOrENRkL9SLZVjLyoRUspZTDDtLYXKXWS36aFojpjkpakoGiz GaTwZbex4Gqxgi63+sDUvylAFV7+aHf7VBRoCL+Qzif/F1exv/nvmJYOkx8eIsEALmAji1DpcTX xXpOrs0pygUKJgQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The DSI horizontal timing calculations done by the driver seem to often lead to underflows or overflows, depending on the videomode. There are two main things the current driver doesn't seem to get right: DSI HSW and HFP, and VSDly. However, even following Toshiba's documentation it seems we don't always get a working display. This patch attempts to fix the horizontal timings for DSI event mode, and on a system with a DSI->HDMI encoder, a lot of standard HDMI modes now seem to work. The work relies on Toshiba's documentation, but also quite a bit on empirical testing. This also adds timing related debug prints to make it easier to improve on this later. The DSI pulse mode has only been tested with a fixed-resolution panel, which limits the testing of different modes on DSI pulse mode. However, as the VSDly calculation also affects pulse mode, so this might cause a regression. Reviewed-by: Peter Ujfalusi Signed-off-by: Tomi Valkeinen Tested-by: Maxim Schwalm # Asus TF700T --- drivers/gpu/drm/bridge/tc358768.c | 211 +++++++++++++++++++++++++++++++++-= ---- 1 file changed, 183 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index f41bf56b7d6b..b465e0a31d09 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -157,6 +158,7 @@ struct tc358768_priv { u32 frs; /* PLL Freqency range for HSCK (post divider) */ =20 u32 dsiclk; /* pll_clk / 2 */ + u32 pclk; /* incoming pclk rate */ }; =20 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_h= ost @@ -380,6 +382,7 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, priv->prd =3D best_prd; priv->frs =3D frs; priv->dsiclk =3D best_pll / 2; + priv->pclk =3D mode->clock * 1000; =20 return 0; } @@ -638,6 +641,28 @@ static u32 tc358768_ps_to_ns(u32 ps) return ps / 1000; } =20 +static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) +{ + return (u32)div_u64((u64)val * NANO, pclk); +} + +/* Convert value in DPI pixel clock units to DSI byte count */ +static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) +{ + u64 m =3D (u64)val * priv->dsiclk / 4 * priv->dsi_lanes; + u64 n =3D priv->pclk; + + return (u32)div_u64(m + n - 1, n); +} + +static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) +{ + u64 m =3D (u64)val * NANO; + u64 n =3D priv->dsiclk / 4 * priv->dsi_lanes; + + return (u32)div_u64(m, n); +} + static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) { struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); @@ -647,11 +672,19 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) s32 raw_val; const struct drm_display_mode *mode; u32 hsbyteclk_ps, dsiclk_ps, ui_ps; - u32 dsiclk, hsbyteclk, video_start; - const u32 internal_delay =3D 40; + u32 dsiclk, hsbyteclk; int ret, i; struct videomode vm; struct device *dev =3D priv->dev; + /* In pixelclock units */ + u32 dpi_htot, dpi_data_start; + /* In byte units */ + u32 dsi_dpi_htot, dsi_dpi_data_start; + u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp; + const u32 dsi_hss =3D 4; /* HSS is a short packet (4 bytes) */ + /* In hsbyteclk units */ + u32 dsi_vsdly; + const u32 internal_dly =3D 40; =20 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to c= ontinuous\n"); @@ -686,27 +719,23 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) case MIPI_DSI_FMT_RGB888: val |=3D (0x3 << 4); hact =3D vm.hactive * 3; - video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: val |=3D (0x4 << 4); hact =3D vm.hactive * 3; - video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; break; =20 case MIPI_DSI_FMT_RGB666_PACKED: val |=3D (0x4 << 4) | BIT(3); hact =3D vm.hactive * 18 / 8; - video_start =3D (vm.hsync_len + vm.hback_porch) * 18 / 8; data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; =20 case MIPI_DSI_FMT_RGB565: val |=3D (0x5 << 4); hact =3D vm.hactive * 2; - video_start =3D (vm.hsync_len + vm.hback_porch) * 2; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: @@ -716,9 +745,150 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) return; } =20 + /* + * There are three important things to make TC358768 work correctly, + * which are not trivial to manage: + * + * 1. Keep the DPI line-time and the DSI line-time as close to each + * other as possible. + * 2. TC358768 goes to LP mode after each line's active area. The DSI + * HFP period has to be long enough for entering and exiting LP mode. + * But it is not clear how to calculate this. + * 3. VSDly (video start delay) has to be long enough to ensure that the + * DSI TX does not start transmitting util we have started receiving + * pixel data from the DPI input. It is not clear how to calculate + * this either. + */ + + dpi_htot =3D vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch; + dpi_data_start =3D vm.hsync_len + vm.hback_porch; + + dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u =3D %u\n", + vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch, + dpi_htot); + + dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u =3D %u\n", + tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), + tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), + tc358768_dpi_to_ns(vm.hactive, vm.pixelclock), + tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock), + tc358768_dpi_to_ns(dpi_htot, vm.pixelclock)); + + dev_dbg(dev, "dpi data start (ns): %u + %u =3D %u\n", + tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), + tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), + tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock)); + + dsi_dpi_htot =3D tc358768_dpi_to_dsi_bytes(priv, dpi_htot); + dsi_dpi_data_start =3D tc358768_dpi_to_dsi_bytes(priv, dpi_data_start); + + if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + dsi_hsw =3D tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len); + dsi_hbp =3D tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch); + } else { + /* HBP is included in HSW in event mode */ + dsi_hbp =3D 0; + dsi_hsw =3D tc358768_dpi_to_dsi_bytes(priv, + vm.hsync_len + vm.hback_porch); + + /* + * The pixel packet includes the actual pixel data, and: + * DSI packet header =3D 4 bytes + * DCS code =3D 1 byte + * DSI packet footer =3D 2 bytes + */ + dsi_hact =3D hact + 4 + 1 + 2; + + dsi_hfp =3D dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; + + /* + * Here we should check if HFP is long enough for entering LP + * and exiting LP, but it's not clear how to calculate that. + * Instead, this is a naive algorithm that just adjusts the HFP + * and HSW so that HFP is (at least) roughly 2/3 of the total + * blanking time. + */ + if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) { + u32 old_hfp =3D dsi_hfp; + u32 old_hsw =3D dsi_hsw; + u32 tot =3D dsi_hfp + dsi_hsw + dsi_hss; + + dsi_hsw =3D tot / 3; + + /* + * Seems like sometimes HSW has to be divisible by num-lanes, but + * not always... + */ + dsi_hsw =3D roundup(dsi_hsw, priv->dsi_lanes); + + dsi_hfp =3D dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; + + dev_dbg(dev, + "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n", + old_hfp, old_hsw, dsi_hfp, dsi_hsw); + } + + dev_dbg(dev, + "dsi horiz timing (bytes): %u, %u + %u + %u + %u =3D %u\n", + dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp, + dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp); + + dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u =3D %u\n", + tc358768_dsi_bytes_to_ns(priv, dsi_hss), + tc358768_dsi_bytes_to_ns(priv, dsi_hsw), + tc358768_dsi_bytes_to_ns(priv, dsi_hbp), + tc358768_dsi_bytes_to_ns(priv, dsi_hact), + tc358768_dsi_bytes_to_ns(priv, dsi_hfp), + tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw + dsi_hbp + dsi_hact += dsi_hfp)); + } + + /* VSDly calculation */ + + /* Start with the HW internal delay */ + dsi_vsdly =3D internal_dly; + + /* Convert to byte units as the other variables are in byte units */ + dsi_vsdly *=3D priv->dsi_lanes; + + /* Do we need more delay, in addition to the internal? */ + if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) { + dsi_vsdly =3D dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp; + dsi_vsdly =3D roundup(dsi_vsdly, priv->dsi_lanes); + } + + dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u =3D %u\n", + dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp, + dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp); + + dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u =3D %u\n", + tc358768_dsi_bytes_to_ns(priv, dsi_vsdly), + tc358768_dsi_bytes_to_ns(priv, dsi_hss), + tc358768_dsi_bytes_to_ns(priv, dsi_hsw), + tc358768_dsi_bytes_to_ns(priv, dsi_hbp), + tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp)); + + /* Convert back to hsbyteclk */ + dsi_vsdly /=3D priv->dsi_lanes; + + /* + * The docs say that there is an internal delay of 40 cycles. + * However, we get underflows if we follow that rule. If we + * instead ignore the internal delay, things work. So either + * the docs are wrong or the calculations are wrong. + * + * As a temporary fix, add the internal delay here, to counter + * the subtraction when writing the register. + */ + dsi_vsdly +=3D internal_dly; + + /* Clamp to the register max */ + if (dsi_vsdly - internal_dly > 0x3ff) { + dev_warn(dev, "VSDly too high, underflows likely\n"); + dsi_vsdly =3D 0x3ff + internal_dly; + } + /* VSDly[9:0] */ - video_start =3D max(video_start, internal_delay + 1) - internal_delay; - tc358768_write(priv, TC358768_VSDLY, video_start); + tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); =20 tc358768_write(priv, TC358768_DATAFMT, val); tc358768_write(priv, TC358768_DSITX_DT, data_type); @@ -826,18 +996,6 @@ static void tc358768_bridge_pre_enable(struct drm_brid= ge *bridge) =20 /* vbp */ tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); - - /* hsw * byteclk * ndl / pclk */ - val =3D (u32)div_u64(vm.hsync_len * - (u64)hsbyteclk * priv->dsi_lanes, - vm.pixelclock); - tc358768_write(priv, TC358768_DSI_HSW, val); - - /* hbp * byteclk * ndl / pclk */ - val =3D (u32)div_u64(vm.hback_porch * - (u64)hsbyteclk * priv->dsi_lanes, - vm.pixelclock); - tc358768_write(priv, TC358768_DSI_HBPR, val); } else { /* Set event mode */ tc358768_write(priv, TC358768_DSI_EVENT, 1); @@ -851,16 +1009,13 @@ static void tc358768_bridge_pre_enable(struct drm_br= idge *bridge) =20 /* vbp (not used in event mode) */ tc358768_write(priv, TC358768_DSI_VBPR, 0); + } =20 - /* (hsw + hbp) * byteclk * ndl / pclk */ - val =3D (u32)div_u64((vm.hsync_len + vm.hback_porch) * - (u64)hsbyteclk * priv->dsi_lanes, - vm.pixelclock); - tc358768_write(priv, TC358768_DSI_HSW, val); + /* hsw (bytes) */ + tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw); =20 - /* hbp (not used in event mode) */ - tc358768_write(priv, TC358768_DSI_HBPR, 0); - } + /* hbp (bytes) */ + tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp); =20 /* hact (bytes) */ tc358768_write(priv, TC358768_DSI_HACT, hact); --=20 2.34.1