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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00001509.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6699.14 via Frontend Transport; Mon, 21 Aug 2023 06:48:47 +0000 Received: from rtg-System-Product-Name.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 21 Aug 2023 01:48:43 -0500 From: Arvind Yadav To: , , , , , , , CC: , , "Arvind Yadav" , Christian Koenig Subject: [PATCH v2 3/7] drm/amdgpu: Add new function to put GPU power profile Date: Mon, 21 Aug 2023 12:17:55 +0530 Message-ID: <20230821064759.94223-4-Arvind.Yadav@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230821064759.94223-1-Arvind.Yadav@amd.com> References: <20230821064759.94223-1-Arvind.Yadav@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001509:EE_|MN2PR12MB4358:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fc91acb-27d5-4ea8-57bc-08dba212abcb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2023 06:48:47.7773 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fc91acb-27d5-4ea8-57bc-08dba212abcb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001509.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4358 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds a function which will clear the GPU power profile after job finished. This is how it works: - schedular will set the GPU power profile based on ring_type. - Schedular will clear the GPU Power profile once job finished. - Here, the *_workload_profile_set function will set the GPU power profile and the *_workload_profile_put function will schedule the smu_delayed_work task after 100ms delay. This smu_delayed_work task will clear a GPU power profile if any new jobs are not scheduled within 100 ms. But if any new job comes within 100ms then the *_workload_profile_set function will cancel this work and set the GPU power profile based on preferences. v2: - Splitting workload_profile_set and workload_profile_put into two separate patches. - Addressed review comment. Cc: Shashank Sharma Cc: Christian Koenig Cc: Alex Deucher Signed-off-by: Arvind Yadav --- drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c | 97 +++++++++++++++++++ drivers/gpu/drm/amd/include/amdgpu_workload.h | 3 + 2 files changed, 100 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c b/drivers/gpu/drm= /amd/amdgpu/amdgpu_workload.c index e661cc5b3d92..6367eb88a44d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c @@ -24,6 +24,9 @@ =20 #include "amdgpu.h" =20 +/* 100 millsecond timeout */ +#define SMU_IDLE_TIMEOUT msecs_to_jiffies(100) + static enum PP_SMC_POWER_PROFILE ring_to_power_profile(uint32_t ring_type) { @@ -59,6 +62,80 @@ amdgpu_power_profile_set(struct amdgpu_device *adev, return ret; } =20 +static int +amdgpu_power_profile_clear(struct amdgpu_device *adev, + enum PP_SMC_POWER_PROFILE profile) +{ + int ret =3D amdgpu_dpm_switch_power_profile(adev, profile, false); + + if (!ret) { + /* Clear the bit for the submitted workload profile */ + adev->smu_workload.submit_workload_status &=3D ~(1 << profile); + } + + return ret; +} + +static void +amdgpu_power_profile_idle_work_handler(struct work_struct *work) +{ + + struct amdgpu_smu_workload *workload =3D container_of(work, + struct amdgpu_smu_workload, + smu_delayed_work.work); + struct amdgpu_device *adev =3D workload->adev; + bool reschedule =3D false; + int index =3D fls(workload->submit_workload_status); + int ret; + + mutex_lock(&workload->workload_lock); + for (; index > 0; index--) { + int val =3D atomic_read(&workload->power_profile_ref[index]); + + if (val) { + reschedule =3D true; + } else { + if (workload->submit_workload_status & + (1 << index)) { + ret =3D amdgpu_power_profile_clear(adev, index); + if (ret) { + DRM_WARN("Failed to clear workload %s,error =3D %d\n", + amdgpu_workload_mode_name[index], ret); + goto exit; + } + } + } + } + if (reschedule) + schedule_delayed_work(&workload->smu_delayed_work, + SMU_IDLE_TIMEOUT); +exit: + mutex_unlock(&workload->workload_lock); +} + +void amdgpu_workload_profile_put(struct amdgpu_device *adev, + uint32_t ring_type) +{ + struct amdgpu_smu_workload *workload =3D &adev->smu_workload; + enum PP_SMC_POWER_PROFILE profile =3D ring_to_power_profile(ring_type); + + if (profile =3D=3D PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT) + return; + + mutex_lock(&workload->workload_lock); + + if (!atomic_read(&workload->power_profile_ref[profile])) { + DRM_WARN("Power profile %s ref. count error\n", + amdgpu_workload_mode_name[profile]); + } else { + atomic_dec(&workload->power_profile_ref[profile]); + schedule_delayed_work(&workload->smu_delayed_work, + SMU_IDLE_TIMEOUT); + } + + mutex_unlock(&workload->workload_lock); +} + void amdgpu_workload_profile_set(struct amdgpu_device *adev, uint32_t ring_type) { @@ -70,13 +147,30 @@ void amdgpu_workload_profile_set(struct amdgpu_device = *adev, return; =20 mutex_lock(&workload->workload_lock); + cancel_delayed_work_sync(&workload->smu_delayed_work); =20 ret =3D amdgpu_power_profile_set(adev, profile); if (ret) { DRM_WARN("Failed to set workload profile to %s, error =3D %d\n", amdgpu_workload_mode_name[profile], ret); + goto exit; + } + + /* Clear the already finished jobs of higher power profile*/ + for (int index =3D fls(workload->submit_workload_status); + index > profile; index--) { + if (!atomic_read(&workload->power_profile_ref[index]) && + workload->submit_workload_status & (1 << index)) { + ret =3D amdgpu_power_profile_clear(adev, index); + if (ret) { + DRM_WARN("Failed to clear workload %s, err =3D %d\n", + amdgpu_workload_mode_name[profile], ret); + goto exit; + } + } } =20 +exit: mutex_unlock(&workload->workload_lock); } =20 @@ -87,6 +181,8 @@ void amdgpu_workload_profile_init(struct amdgpu_device *= adev) adev->smu_workload.initialized =3D true; =20 mutex_init(&adev->smu_workload.workload_lock); + INIT_DELAYED_WORK(&adev->smu_workload.smu_delayed_work, + amdgpu_power_profile_idle_work_handler); } =20 void amdgpu_workload_profile_fini(struct amdgpu_device *adev) @@ -94,6 +190,7 @@ void amdgpu_workload_profile_fini(struct amdgpu_device *= adev) if (!adev->smu_workload.initialized) return; =20 + cancel_delayed_work_sync(&adev->smu_workload.smu_delayed_work); adev->smu_workload.submit_workload_status =3D 0; adev->smu_workload.initialized =3D false; mutex_destroy(&adev->smu_workload.workload_lock); diff --git a/drivers/gpu/drm/amd/include/amdgpu_workload.h b/drivers/gpu/dr= m/amd/include/amdgpu_workload.h index 5022f28fc2f9..ee1f87257f2d 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_workload.h +++ b/drivers/gpu/drm/amd/include/amdgpu_workload.h @@ -46,6 +46,9 @@ static const char * const amdgpu_workload_mode_name[] =3D= { "Window3D" }; =20 +void amdgpu_workload_profile_put(struct amdgpu_device *adev, + uint32_t ring_type); + void amdgpu_workload_profile_set(struct amdgpu_device *adev, uint32_t ring_type); =20 --=20 2.34.1