From nobody Wed Dec 17 12:42:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0B90EE49A5 for ; Mon, 21 Aug 2023 04:52:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233068AbjHUEwi (ORCPT ); Mon, 21 Aug 2023 00:52:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229535AbjHUEwh (ORCPT ); Mon, 21 Aug 2023 00:52:37 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0AFD3A3; Sun, 20 Aug 2023 21:52:35 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5CF602F4; Sun, 20 Aug 2023 21:53:15 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.42.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AE6AA3F740; Sun, 20 Aug 2023 21:52:30 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 1/3] coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus Date: Mon, 21 Aug 2023 10:22:14 +0530 Message-Id: <20230821045216.641499-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821045216.641499-1-anshuman.khandual@arm.com> References: <20230821045216.641499-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This work arounds errata 1490853 on Cortex-A76, and Neoverse-N1, errata 1491015 on Cortex-A77, errata 1502854 on Cortex-X1, and errata 1619801 on Neoverse-V1, based affected cpus, where software read for TRCIDR3.CCITMIN field in ETM gets an wrong value. If software uses the value returned by the TRCIDR3.CCITMIN register field, then it will limit the range which could be used for programming the ETM. In reality, the ETM could be programmed with a much smaller value than what is indicated by the TRCIDR3.CCITMIN field and still function correctly. If software reads the TRCIDR3.CCITMIN register field, corresponding to the instruction trace counting minimum threshold, observe the value 0x100 or a minimum cycle count threshold of 256. The correct value should be 0x4 or a minimum cycle count threshold of 4. This work arounds the problem via storing 4 in drvdata->ccitmin on affected systems where the TRCIDR3.CCITMIN has been 256, thus preserving cycle count threshold granularity. These errata information has been updated in arch/arm64/silicon-errata.rst, but without their corresponding configs because these have been implemented directly in the driver. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- Documentation/arch/arm64/silicon-errata.rst | 10 ++++++ .../coresight/coresight-etm4x-core.c | 36 +++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index bedd3a1d7b42..b08f33eda5f1 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -107,6 +107,10 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_14632= 25 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | Cortex-A76 | #1490853 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | Cortex-A77 | #1491015 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_15084= 12 | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_20516= 78 | @@ -125,6 +129,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_26451= 98 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | Cortex-X1 | #1502854 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_21198= 58 | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_22244= 89 | @@ -133,6 +139,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Neoverse-N1 | #1349291 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | Neoverse-N1 | #1490853 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_15424= 19 | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_21392= 08 | @@ -141,6 +149,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_22531= 38 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | Neoverse-V1 | #1619801 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | MMU-500 | #841119,826419 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | MMU-600 | #1076982,1209401| N/A = | diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 7e307022303a..1308d89f58d1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1131,6 +1131,39 @@ static void cpu_detect_trace_filtering(struct etmv4_= drvdata *drvdata) drvdata->trfcr =3D trfcr; } =20 +/* + * The following errata on applicable cpu ranges, affect the CCITMIN filed + * in TCRIDR3 register. Software read for the field returns 0x100 limiting + * the cycle threshold granularity, whereas the right value should have + * been 0x4, which is well supported in the hardware. + */ +static struct midr_range etm_wrong_ccitmin_cpus[] =3D { + /* Erratum #1490853 - Cortex-A76 */ + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0), + /* Erratum #1490853 - Neoverse-N1 */ + MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0), + /* Erratum #1491015 - Cortex-A77 */ + MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0), + /* Erratum #1502854 - Cortex-X1 */ + MIDR_REV(MIDR_CORTEX_X1, 0, 0), + /* Erratum #1619801 - Neoverse-V1 */ + MIDR_REV(MIDR_NEOVERSE_V1, 0, 0), + {}, +}; + +static bool etm4_core_reads_wrong_ccitmin(struct etmv4_drvdata *drvdata) +{ + /* + * Erratum affected cpus will read 256 as the minimum + * instruction trace cycle counting threshold whereas + * the correct value should be 4 instead. Override the + * recorded value for 'drvdata->ccitmin' to workaround + * this problem. + */ + return is_midr_in_range_list(read_cpuid_id(), etm_wrong_ccitmin_cpus) && + (drvdata->ccitmin =3D=3D 256); +} + static void etm4_init_arch_data(void *info) { u32 etmidr0; @@ -1195,6 +1228,9 @@ static void etm4_init_arch_data(void *info) etmidr3 =3D etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ drvdata->ccitmin =3D FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); + if (etm4_core_reads_wrong_ccitmin(drvdata)) + drvdata->ccitmin =3D 4; + /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ drvdata->s_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); drvdata->config.s_ex_level =3D drvdata->s_ex_level; --=20 2.25.1 From nobody Wed Dec 17 12:42:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDE67EE4996 for ; Mon, 21 Aug 2023 04:52:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233075AbjHUEwm (ORCPT ); Mon, 21 Aug 2023 00:52:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229535AbjHUEwl (ORCPT ); Mon, 21 Aug 2023 00:52:41 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BCA44A8; Sun, 20 Aug 2023 21:52:39 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E56D1FB; Sun, 20 Aug 2023 21:53:20 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.42.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4ED3B3F740; Sun, 20 Aug 2023 21:52:35 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 2/3] coresight: etm: Make cycle count threshold user configurable Date: Mon, 21 Aug 2023 10:22:15 +0530 Message-Id: <20230821045216.641499-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821045216.641499-1-anshuman.khandual@arm.com> References: <20230821045216.641499-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Cycle counting is enabled, when requested and supported but with a default threshold value ETM_CYC_THRESHOLD_DEFAULT i.e 0x100 getting into TRCCCCTLR, representing the minimum interval between cycle count trace packets. This makes cycle threshold user configurable, from the user space via perf event attributes. Although it falls back using ETM_CYC_THRESHOLD_DEFAULT, in case no explicit request. As expected it creates a sysfs file as well. /sys/bus/event_source/devices/cs_etm/format/cc_threshold New 'cc_threshold' uses 'event->attr.config3' as no more space is available in 'event->attr.config1' or 'event->attr.config2'. Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Leo Yan Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mike Leach Signed-off-by: Anshuman Khandual --- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 +++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index 5ca6278baff4..09f75dffae60 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -68,6 +68,7 @@ PMU_FORMAT_ATTR(preset, "config:0-3"); PMU_FORMAT_ATTR(sinkid, "config2:0-31"); /* config ID - set if a system configuration is selected */ PMU_FORMAT_ATTR(configid, "config2:32-63"); +PMU_FORMAT_ATTR(cc_threshold, "config3:0-11"); =20 =20 /* @@ -101,6 +102,7 @@ static struct attribute *etm_config_formats_attr[] =3D { &format_attr_preset.attr, &format_attr_configid.attr, &format_attr_branch_broadcast.attr, + &format_attr_cc_threshold.attr, NULL, }; =20 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 1308d89f58d1..9edba406f523 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -635,7 +635,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, struct etmv4_config *config =3D &drvdata->config; struct perf_event_attr *attr =3D &event->attr; unsigned long cfg_hash; - int preset; + int preset, cc_threshold; =20 /* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config)); @@ -658,7 +658,12 @@ static int etm4_parse_event_config(struct coresight_de= vice *csdev, if (attr->config & BIT(ETM_OPT_CYCACC)) { config->cfg |=3D TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - config->ccctlr =3D ETM_CYC_THRESHOLD_DEFAULT; + cc_threshold =3D attr->config3 & ETM_CYC_THRESHOLD_MASK; + if (!cc_threshold) + cc_threshold =3D ETM_CYC_THRESHOLD_DEFAULT; + if (cc_threshold < drvdata->ccitmin) + cc_threshold =3D drvdata->ccitmin; + config->ccctlr =3D cc_threshold; } if (attr->config & BIT(ETM_OPT_TS)) { /* --=20 2.25.1 From nobody Wed Dec 17 12:42:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD19AEE4996 for ; Mon, 21 Aug 2023 04:52:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233038AbjHUEws (ORCPT ); Mon, 21 Aug 2023 00:52:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229535AbjHUEwr (ORCPT ); Mon, 21 Aug 2023 00:52:47 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 93801B1; Sun, 20 Aug 2023 21:52:44 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E99461FB; Sun, 20 Aug 2023 21:53:24 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.42.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 214853F740; Sun, 20 Aug 2023 21:52:39 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 3/3] Documentation: coresight: Add cc_threshold tunable Date: Mon, 21 Aug 2023 10:22:16 +0530 Message-Id: <20230821045216.641499-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821045216.641499-1-anshuman.khandual@arm.com> References: <20230821045216.641499-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This updates config option to include 'cc_threshold' tunable value. Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Jonathan Corbet Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed by: Mike Leach Signed-off-by: Anshuman Khandual --- Documentation/trace/coresight/coresight.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/tr= ace/coresight/coresight.rst index 4a71ea6cb390..ce55adb80b82 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -624,6 +624,10 @@ They are also listed in the folder /sys/bus/event_sour= ce/devices/cs_etm/format/ * - timestamp - Session local version of the system wide setting: :ref:`ETMv4_MODE_= TIMESTAMP ` + * - cc_threshold + - Cycle count threshold value. If nothing is provided here or the pro= vided value is 0, then the + default value i.e 0x100 will be used. If provided value is less tha= n minimum cycles threshold + value, as indicated via TRCIDR3.CCITMIN, then the minimum value wil= l be used instead. =20 How to use the STM module ------------------------- --=20 2.25.1