From nobody Wed Dec 17 14:23:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E94BC7115A for ; Fri, 18 Aug 2023 13:19:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377070AbjHRNSq (ORCPT ); Fri, 18 Aug 2023 09:18:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377058AbjHRNSN (ORCPT ); Fri, 18 Aug 2023 09:18:13 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06E0F26A5; Fri, 18 Aug 2023 06:18:11 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37IDHrhB094311; Fri, 18 Aug 2023 08:17:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1692364673; bh=A7PO+ZQXUU49U7Thnx8tUXylQaCbtQVoEH+MFXAWi9k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BYBZlNQd0YsXtNx2DH0YNLiCxzFwsURk2IEa8jZBuHN4stC/w5a6aMLwtHUkXQUq+ lHQ7bqLSvUQNWZcrxPz2+4jlavngO8CvVRLGkrHZ2fjMvWMyzrv0Ed6ho+mLD3aB7Q E9EXIwLHMY6UrIOdgfzRouVSlF5b5c+0JjSH7nGs= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37IDHr4b114444 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Aug 2023 08:17:53 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 18 Aug 2023 08:17:53 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 18 Aug 2023 08:17:53 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37IDHqfw021213; Fri, 18 Aug 2023 08:17:52 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Devarsh Thakkar , Jayesh Choudhary , Jai Luthra , Aradhya Bhatia Subject: [PATCH 1/2] dt-bindings: display: ti: Add support for am62a7 dss Date: Fri, 18 Aug 2023 18:47:49 +0530 Message-ID: <20230818131750.4779-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230818131750.4779-1-a-bhatia1@ti.com> References: <20230818131750.4779-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DSS controller on TI's AM62A7 SoC is an update from that on TI's AM625 SoC. Like the DSS in AM625, the DSS in this SoC has 2 video pipelines, but unlike the former, the latter only has one output port on VP2 to service DPI display sinks. Add the new controller's compatible. Signed-off-by: Aradhya Bhatia --- .../bindings/display/ti/ti,am65x-dss.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index ae09cd3cbce1..b6767ef0d24d 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - ti,am625-dss + - ti,am62a7,dss - ti,am65x-dss =20 reg: @@ -87,6 +88,7 @@ properties: For AM65x DSS, the OLDI output port node from video port 1. For AM625 DSS, the internal DPI output port node from video port 1. + For AM62A7 DSS, the port is tied off inside the SoC. =20 port@1: $ref: /schemas/graph.yaml#/properties/port @@ -108,6 +110,18 @@ properties: Input memory (from main memory to dispc) bandwidth limit in bytes per second =20 +allOf: + - if: + properties: + compatible: + contains: + const: ti,am62a7-dss + then: + properties: + ports: + properties: + port@0: false + required: - compatible - reg --=20 2.40.1 From nobody Wed Dec 17 14:23:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BE37C7115B for ; Fri, 18 Aug 2023 13:19:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377097AbjHRNSv (ORCPT ); Fri, 18 Aug 2023 09:18:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377072AbjHRNSV (ORCPT ); Fri, 18 Aug 2023 09:18:21 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D443273C; Fri, 18 Aug 2023 06:18:19 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37IDHsM4109099; Fri, 18 Aug 2023 08:17:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1692364674; bh=y6Wcn+Ep7psdW2qFD1MlnMaWhzI088g5k1UW//q3SPo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hzgObYZnqeJxJXc3e/p6JWB5wJOOzegsSVAtL0PPag8eadatrbTP0wCO7eXFbQM7Z KEAS9lNtxs1YRVAy5k5CtIltCV6rUKWIqaUf0tX+ebFY1x0nv9x5hkw0Cme8mnUGcb t0JPzYu32sBa6eh06JYmBksmHjY9W883HmUJV2/c= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37IDHsNw126019 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Aug 2023 08:17:54 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 18 Aug 2023 08:17:54 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 18 Aug 2023 08:17:54 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37IDHrop009286; Fri, 18 Aug 2023 08:17:54 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Devarsh Thakkar , Jayesh Choudhary , Jai Luthra , Aradhya Bhatia Subject: [PATCH 2/2] drivers/tidss: Add support for AM62A7 DSS Date: Fri, 18 Aug 2023 18:47:50 +0530 Message-ID: <20230818131750.4779-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230818131750.4779-1-a-bhatia1@ti.com> References: <20230818131750.4779-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the DSS controller on TI's AM62A7 SoC in the tidss driver. This contrller has 2 video pipelines that can render 2 video planes on over a screen, using the overlay managers. The output of the DSS comes from video port 2 (VP2) in the form of RGB88 DPI signals, while the VP1 is tied off inside the SoC. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 53 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 9d9dee7abaef..0e2d55d9a0d7 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -322,6 +322,54 @@ const struct dispc_features dispc_am625_feats =3D { .vid_order =3D { 1, 0 }, }; =20 +const struct dispc_features dispc_am62a7_feats =3D { + .max_pclk_khz =3D { + [DISPC_VP_DPI] =3D 165000, + }, + + .scaling =3D { + .in_width_max_5tap_rgb =3D 1280, + .in_width_max_3tap_rgb =3D 2560, + .in_width_max_5tap_yuv =3D 2560, + .in_width_max_3tap_yuv =3D 4096, + .upscale_limit =3D 16, + .downscale_limit_5tap =3D 4, + .downscale_limit_3tap =3D 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max =3D 32, + }, + + .subrev =3D DISPC_AM62A7, + + .common =3D "common", + .common_regs =3D tidss_am65x_common_regs, + + .num_vps =3D 2, + .vp_name =3D { "vp1", "vp2" }, + .ovr_name =3D { "ovr1", "ovr2" }, + .vpclk_name =3D { "vp1", "vp2" }, + .vp_bus_type =3D { DISPC_VP_INTERNAL, DISPC_VP_DPI }, + + .vp_feat =3D { .color =3D { + .has_ctm =3D true, + .gamma_size =3D 256, + .gamma_type =3D TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes =3D 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name =3D { "vid", "vidl1" }, + .vid_lite =3D { false, true, }, + .vid_order =3D { 1, 0 }, +}; + static const u16 *dispc_common_regmap; =20 struct dss_vp_data { @@ -823,6 +871,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc= _device *dispc) switch (dispc->feat->subrev) { case DISPC_K2G: return dispc_k2g_read_and_clear_irqstatus(dispc); + case DISPC_AM62A7: case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: @@ -839,6 +888,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, di= spc_irq_t mask) case DISPC_K2G: dispc_k2g_set_irqenable(dispc, mask); break; + case DISPC_AM62A7: case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: @@ -1330,6 +1380,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, = u32 hw_plane, dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); break; + case DISPC_AM62A7: case DISPC_AM625: case DISPC_AM65X: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, @@ -2249,6 +2300,7 @@ static void dispc_plane_init(struct dispc_device *dis= pc) case DISPC_K2G: dispc_k2g_plane_init(dispc); break; + case DISPC_AM62A7: case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: @@ -2356,6 +2408,7 @@ static void dispc_vp_write_gamma_table(struct dispc_d= evice *dispc, case DISPC_K2G: dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); break; + case DISPC_AM62A7: case DISPC_AM625: case DISPC_AM65X: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/ti= dss_dispc.h index 33ac5ad7a423..2aa1c814ea2a 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -59,6 +59,7 @@ enum dispc_vp_bus_type { =20 enum dispc_dss_subrevision { DISPC_K2G, + DISPC_AM62A7, DISPC_AM625, DISPC_AM65X, DISPC_J721E, @@ -88,6 +89,7 @@ struct dispc_features { =20 extern const struct dispc_features dispc_k2g_feats; extern const struct dispc_features dispc_am625_feats; +extern const struct dispc_features dispc_am62a7_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; =20 diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tids= s_drv.c index 4d063eb9cd0b..edf69d020544 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -231,6 +231,7 @@ static void tidss_shutdown(struct platform_device *pdev) static const struct of_device_id tidss_of_table[] =3D { { .compatible =3D "ti,k2g-dss", .data =3D &dispc_k2g_feats, }, { .compatible =3D "ti,am625-dss", .data =3D &dispc_am625_feats, }, + { .compatible =3D "ti,am62a7-dss", .data =3D &dispc_am62a7_feats, }, { .compatible =3D "ti,am65x-dss", .data =3D &dispc_am65x_feats, }, { .compatible =3D "ti,j721e-dss", .data =3D &dispc_j721e_feats, }, { } --=20 2.40.1