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Thu, 17 Aug 2023 18:21:19 -0700 From: Asmaa Mnebhi To: , , , , , CC: Asmaa Mnebhi Subject: [PATCH v3 2/2] gpio: mlxbf3: Support add_pin_ranges() Date: Thu, 17 Aug 2023 21:21:11 -0400 Message-ID: <20230818012111.22947-3-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20230818012111.22947-1-asmaa@nvidia.com> References: <20230818012111.22947-1-asmaa@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529F:EE_|DM4PR12MB5102:EE_ X-MS-Office365-Filtering-Correlation-Id: cdf8cf55-3397-4e49-5d08-08db9f897794 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2S+0r3Agirg1hZ8TowpJ8VZTikXfGkPi0B0wXUZ3AvAIwaOfLMhdkxch7XGTKcoUlEIx4EOj4Quuf2sv1+vIp6iZMQB7IrH97XbdWgqiT8Wyd3+q01DsnDdeK0r4D1e+2OkEGL/geDelklrX2GUD17xoFM1Vu2Wuq0tyRm4jETAryDWb5nzrhR/PimGzahHtH7ongICZplvZtyL+XgRT2Ul5qogLxQWxwLUbrbQaAl3acOdYUDIjVAyKMVxgFPharQxoGPc6VbgGusWs2SYIcQ/BDS2HvFmaiZPf1Sru/5UsYR+irND471605pyTtZO9SvTp11PrIp/D8pSZt+u8uIBPF8hxKmmMMC0Zi24THrOBzKiywqAk0t11KKg9E3PY7Po2jLioo0aSehPU6qgX+nzYEYXUDmjR1J2HEtYkKEz7Rxwa79HOcF4cFl3Ta6vXZbB6gDCya+gMrlONdtECnqDvuuHN4wtdnF4wSJvXsNI6e6MFvt5ooUSnXhFcRJ2hWYEy+g7V48Vyh8pNAmsVBouPfU5pBxyOi/P1z46DvUeWusCN2tmIJrFOnW7G9F9LtTlhuIChz0enHMJZt82/o5Depb0iNUbmHNjxFQNXJTjVV/IV+YITPm/JWeN/8E+4V3RZpUfTg+DMTSQM2iVGZPTDD5p4OmqT3Pm3s1WLgwD3wRBXYvRD8tCjxF4PF49fVWDtXcnH3pxT59JgrU0/ErV/IYBdHD6VSjrMAWQ/5cPq7PEFS68PJLF9N11A7vw35IiP6N361NPVCMbxk0xUdg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(136003)(39860400002)(396003)(451199024)(186009)(1800799009)(82310400011)(46966006)(40470700004)(36840700001)(86362001)(36756003)(82740400003)(356005)(7636003)(40480700001)(478600001)(5660300002)(107886003)(2616005)(110136005)(70206006)(70586007)(26005)(6666004)(7696005)(316002)(1076003)(4326008)(8676002)(41300700001)(8936002)(40460700003)(47076005)(336012)(36860700001)(2906002)(426003)(83380400001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2023 01:21:36.7198 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdf8cf55-3397-4e49-5d08-08db9f897794 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5102 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Support add_pin_ranges() so that pinctrl_gpio_request() can be called. The GPIO value is not modified when the user runs the "gpioset" tool. This is because when gpiochip_generic_request is invoked by the gpio-mlxbf3 driver, "pin_ranges" is empty so it skips "pinctrl_gpio_request()". pinctrl_gpio_request() is essential in the code flow because it changes the mux value so that software has control over modifying the GPIO value. Adding add_pin_ranges() creates a dependency on the pinctrl-mlxbf3.c driver. Fixes: cd33f216d24 ("gpio: mlxbf3: Add gpio driver support") Signed-off-by: Asmaa Mnebhi Reviewed-by: Andy Shevchenko --- v2->v3: - Replace boolean logic by clear switch statement logic in mlxbf3_gpio_add_pin_ranges() v1->v2: - Cleanup mlxbf3_gpio_add_pin_ranges() drivers/gpio/gpio-mlxbf3.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c index e30cee108986..436b0bb5ebb1 100644 --- a/drivers/gpio/gpio-mlxbf3.c +++ b/drivers/gpio/gpio-mlxbf3.c @@ -19,6 +19,8 @@ * gpio[1]: HOST_GPIO32->HOST_GPIO55 */ #define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32 +#define MLXBF3_GPIO_MAX_PINS_BLOCK0 MLXBF3_GPIO_MAX_PINS_PER_BLOCK +#define MLXBF3_GPIO_MAX_PINS_BLOCK1 24 =20 /* * fw_gpio[x] block registers and their offset @@ -158,6 +160,26 @@ static const struct irq_chip gpio_mlxbf3_irqchip =3D { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 +static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + unsigned int id; + + switch(chip->ngpio) { + case MLXBF3_GPIO_MAX_PINS_BLOCK0: + id =3D 0; + break; + case MLXBF3_GPIO_MAX_PINS_BLOCK1: + id =3D 1; + break; + default: + return -EINVAL; + } + + return gpiochip_add_pin_range(chip, "MLNXBF34:00", + chip->base, id * MLXBF3_GPIO_MAX_PINS_PER_BLOCK, + chip->ngpio); +} + static int mlxbf3_gpio_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -197,6 +219,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pd= ev) gc->request =3D gpiochip_generic_request; gc->free =3D gpiochip_generic_free; gc->owner =3D THIS_MODULE; + gc->add_pin_ranges =3D mlxbf3_gpio_add_pin_ranges; =20 irq =3D platform_get_irq(pdev, 0); if (irq >=3D 0) { @@ -243,6 +266,7 @@ static struct platform_driver mlxbf3_gpio_driver =3D { }; module_platform_driver(mlxbf3_gpio_driver); =20 +MODULE_SOFTDEP("pre: pinctrl-mlxbf3"); MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver"); MODULE_AUTHOR("Asmaa Mnebhi "); MODULE_LICENSE("Dual BSD/GPL"); --=20 2.30.1