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Thu, 17 Aug 2023 18:21:16 -0700 From: Asmaa Mnebhi To: , , , , , CC: Asmaa Mnebhi Subject: [PATCH v3 1/2] pinctrl: mlxbf3: Remove gpio_disable_free() Date: Thu, 17 Aug 2023 21:21:10 -0400 Message-ID: <20230818012111.22947-2-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20230818012111.22947-1-asmaa@nvidia.com> References: <20230818012111.22947-1-asmaa@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|LV2PR12MB5797:EE_ X-MS-Office365-Filtering-Correlation-Id: 20ea9396-1169-485f-dcb1-08db9f89753d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 361qddnL1nPffaERVZMPu3c6NOY3ptEcL0UbItSRpyifpfelVfTS9DMPGM4ZO2ZBzjdgupbJB01N0R+yUsillCtMbaOnY0piqCtJE1UEtqtpHMJznXASkl0owWr3vDsH9cndNZYMFqqsR4GQqpX7gN0byUk0Ju/8HXRopHYrf72qqPDDJUpvlLyRCcIT67EqRe4iHlWv91Hm+LKP6Nnp9VzMnffdSReRn/QKdfNvUO8KMVeZKwDh+wmvndz/Na353qE5JX1z8d5pHSMCbW5+saQnq5VgwrDTMDf9mMQk6WQjoXYr1TeZvW+03JRPvF1gxwOpTHd1lo9twYP+elLthHpzGrhLO+o0u4+ULusx28p/CfIDSJI3bzgihEVnjhUqXq+XNOgciWIYK8WIG3+Hnd0TLDKA812/H16iMf6/ltbqpivaIGqvh/yl8V007hDx4V8rXswmz/MatM+M4Qcr3xfrjrYe7IrRtBpF1HJ8ZTW2dKnFd9M7nI5m1LxdQQjpXmLkbVwtXjhuLd6s1Mo24XKdNtAOgO8cZABkD4XpOnZFEO6Av5BVSO5xeb7ZkBZtuHlJaFW1rZYcnqpxIibL7mN2KcA6do5uW8HsYNf3pwt6KLED3W+JQjxUP3lhNo13AM3s/T1/z/dC8QGIQeRjJTyHWXMqgwSycJ0fYIDCm7ByNm94jiKB79cotZSTKA80oV5TbRlIajhTbOfrGJ4Wu18t0gzd/Lsz1LKpxMZorHxLtxrgtSVg3DAuT6sJRQ+T+QidoTkZiNfn3gHPzPTt1g== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(136003)(396003)(39860400002)(451199024)(1800799009)(82310400011)(186009)(40470700004)(46966006)(36840700001)(86362001)(36756003)(82740400003)(356005)(7636003)(40480700001)(107886003)(2616005)(5660300002)(110136005)(70586007)(478600001)(70206006)(7696005)(6666004)(316002)(26005)(1076003)(4326008)(8676002)(8936002)(41300700001)(40460700003)(47076005)(336012)(36860700001)(83380400001)(426003)(2906002)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2023 01:21:32.8442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20ea9396-1169-485f-dcb1-08db9f89753d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5797 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove support for gpio_disable_free() because it is called when the libgpi= od command "gpioset" is invoked. This gives the GPIO control back to hardware = which cancels out the effort to set the GPIO value. Reminder of the code flow to change a GPIO value from software: 1) All GPIOs are controlled by hardware by default 2) To change the GPIO value, enable software control via a mux. 3) Once software has control over the GPIO pin, the gpio-mlxbf3 driver will be able to change the direction and value of the GPIO. When the user runs "gpioset gpiochip0 0=3D0" for example, the gpio pin value should change from 1 to 0. In this case, mlxbf3_gpio_request_enab= le() is called via gpiochip_generic_request(). The latter switches GPIO control = from hardware to software. Then the GPIO value is changed from 1 to 0. However, gpio_disable_free() is also called which changes control back to hardware which changes the GPIO value back to 1. Fixes: d11f932808d ("pinctrl: mlxbf3: Add pinctrl driver support") Signed-off-by: Asmaa Mnebhi --- v2->v3: - No changes v1->v2: - No changes=20 drivers/pinctrl/pinctrl-mlxbf3.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlx= bf3.c index d9944e6a0af9..0e852a0d5ec2 100644 --- a/drivers/pinctrl/pinctrl-mlxbf3.c +++ b/drivers/pinctrl/pinctrl-mlxbf3.c @@ -223,26 +223,12 @@ static int mlxbf3_gpio_request_enable(struct pinctrl_= dev *pctldev, return 0; } =20 -static void mlxbf3_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct mlxbf3_pinctrl *priv =3D pinctrl_dev_get_drvdata(pctldev); - - /* disable GPIO functionality by giving control back to hardware */ - if (offset < MLXBF3_NGPIOS_GPIO0) - writel(BIT(offset), priv->fw_ctrl_clr0); - else - writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1); -} - static const struct pinmux_ops mlxbf3_pmx_ops =3D { .get_functions_count =3D mlxbf3_pmx_get_funcs_count, .get_function_name =3D mlxbf3_pmx_get_func_name, .get_function_groups =3D mlxbf3_pmx_get_groups, .set_mux =3D mlxbf3_pmx_set, .gpio_request_enable =3D mlxbf3_gpio_request_enable, - .gpio_disable_free =3D mlxbf3_gpio_disable_free, }; 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Thu, 17 Aug 2023 18:21:20 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 17 Aug 2023 18:21:19 -0700 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Thu, 17 Aug 2023 18:21:19 -0700 From: Asmaa Mnebhi To: , , , , , CC: Asmaa Mnebhi Subject: [PATCH v3 2/2] gpio: mlxbf3: Support add_pin_ranges() Date: Thu, 17 Aug 2023 21:21:11 -0400 Message-ID: <20230818012111.22947-3-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20230818012111.22947-1-asmaa@nvidia.com> References: <20230818012111.22947-1-asmaa@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529F:EE_|DM4PR12MB5102:EE_ X-MS-Office365-Filtering-Correlation-Id: cdf8cf55-3397-4e49-5d08-08db9f897794 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2023 01:21:36.7198 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdf8cf55-3397-4e49-5d08-08db9f897794 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5102 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Support add_pin_ranges() so that pinctrl_gpio_request() can be called. The GPIO value is not modified when the user runs the "gpioset" tool. This is because when gpiochip_generic_request is invoked by the gpio-mlxbf3 driver, "pin_ranges" is empty so it skips "pinctrl_gpio_request()". pinctrl_gpio_request() is essential in the code flow because it changes the mux value so that software has control over modifying the GPIO value. Adding add_pin_ranges() creates a dependency on the pinctrl-mlxbf3.c driver. Fixes: cd33f216d24 ("gpio: mlxbf3: Add gpio driver support") Signed-off-by: Asmaa Mnebhi Reviewed-by: Andy Shevchenko --- v2->v3: - Replace boolean logic by clear switch statement logic in mlxbf3_gpio_add_pin_ranges() v1->v2: - Cleanup mlxbf3_gpio_add_pin_ranges() drivers/gpio/gpio-mlxbf3.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c index e30cee108986..436b0bb5ebb1 100644 --- a/drivers/gpio/gpio-mlxbf3.c +++ b/drivers/gpio/gpio-mlxbf3.c @@ -19,6 +19,8 @@ * gpio[1]: HOST_GPIO32->HOST_GPIO55 */ #define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32 +#define MLXBF3_GPIO_MAX_PINS_BLOCK0 MLXBF3_GPIO_MAX_PINS_PER_BLOCK +#define MLXBF3_GPIO_MAX_PINS_BLOCK1 24 =20 /* * fw_gpio[x] block registers and their offset @@ -158,6 +160,26 @@ static const struct irq_chip gpio_mlxbf3_irqchip =3D { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 +static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + unsigned int id; + + switch(chip->ngpio) { + case MLXBF3_GPIO_MAX_PINS_BLOCK0: + id =3D 0; + break; + case MLXBF3_GPIO_MAX_PINS_BLOCK1: + id =3D 1; + break; + default: + return -EINVAL; + } + + return gpiochip_add_pin_range(chip, "MLNXBF34:00", + chip->base, id * MLXBF3_GPIO_MAX_PINS_PER_BLOCK, + chip->ngpio); +} + static int mlxbf3_gpio_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -197,6 +219,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pd= ev) gc->request =3D gpiochip_generic_request; gc->free =3D gpiochip_generic_free; gc->owner =3D THIS_MODULE; + gc->add_pin_ranges =3D mlxbf3_gpio_add_pin_ranges; =20 irq =3D platform_get_irq(pdev, 0); if (irq >=3D 0) { @@ -243,6 +266,7 @@ static struct platform_driver mlxbf3_gpio_driver =3D { }; module_platform_driver(mlxbf3_gpio_driver); =20 +MODULE_SOFTDEP("pre: pinctrl-mlxbf3"); MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver"); MODULE_AUTHOR("Asmaa Mnebhi "); MODULE_LICENSE("Dual BSD/GPL"); --=20 2.30.1