From nobody Fri Dec 19 01:49:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D0FEC83F16 for ; Mon, 28 Aug 2023 16:00:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232643AbjH1QAA (ORCPT ); Mon, 28 Aug 2023 12:00:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbjH1P7V (ORCPT ); Mon, 28 Aug 2023 11:59:21 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B12E2115 for ; Mon, 28 Aug 2023 08:59:18 -0700 (PDT) Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1qaee0-0005pk-3q; Mon, 28 Aug 2023 17:59:12 +0200 From: Michael Tretter Date: Mon, 28 Aug 2023 17:59:08 +0200 Subject: [PATCH 3/5] drm/bridge: samsung-dsim: update PLL reference clock MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230818-samsung-dsim-v1-3-b39716db6b7a@pengutronix.de> References: <20230818-samsung-dsim-v1-0-b39716db6b7a@pengutronix.de> In-Reply-To: <20230818-samsung-dsim-v1-0-b39716db6b7a@pengutronix.de> To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, Michael Tretter X-Mailer: b4 0.12.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: m.tretter@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PLL requires a clock between 2 MHz and 30 MHz after the pre-divider. The reference clock for the PLL may change due to changes to it's parent clock. Thus, the frequency may be out of range or unsuited for generating the high speed clock for MIPI DSI. Try to keep the pre-devider small, and set the reference clock close to 30 MHz before recalculating the PLL configuration. Use a divider with a power of two for the reference clock as this seems to work best in my tests. Signed-off-by: Michael Tretter Reviewed-by: Marco Felsch --- drivers/gpu/drm/bridge/samsung-dsim.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index da90c2038042..4de6e4f116db 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -611,10 +611,21 @@ static unsigned long samsung_dsim_set_pll(struct sams= ung_dsim *dsi, u16 m; u32 reg; =20 - if (dsi->pll_clk) + if (dsi->pll_clk) { + /* + * Ensure that the reference clock is generated with a power of + * two divider from its parent, but close to the PLLs upper + * limit of the valid range of 2 MHz to 30 MHz. + */ + fin =3D clk_get_rate(clk_get_parent(dsi->pll_clk)); + while (fin > 30 * MHZ) + fin =3D fin / 2; + clk_set_rate(dsi->pll_clk, fin); + fin =3D clk_get_rate(dsi->pll_clk); - else + } else { fin =3D dsi->pll_clk_rate; + } dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin); =20 fout =3D samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); --=20 2.39.2