From nobody Fri Sep 20 11:55:08 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BC98C2FC27 for ; Thu, 17 Aug 2023 06:27:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348241AbjHQG05 (ORCPT ); Thu, 17 Aug 2023 02:26:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348206AbjHQG0j (ORCPT ); Thu, 17 Aug 2023 02:26:39 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E287F2700; Wed, 16 Aug 2023 23:26:37 -0700 (PDT) X-UUID: fed34de23cc611eeb20a276fd37b9834-20230817 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VDprCoZcO7oM1ZDNMMHOchmK+k9rb2fBKtIAYWRqCHw=; b=TEG3Lsk408PmJdN37jHHP6boUAjMhGSHoyqS78OQxuNcaOHpRuGgFJYFDTUmnCGPPK+lEiS/dMf9wU3sWCYh8+1Qkv567Fgc+oxem8d14f7XTpvzYAct6zDUJujOsNmuIzj94megQyznSzejHNIC4r0U+AzrtolgFTPhsovTVI0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:6715ed90-c62d-4874-9a63-c6cfddb6a588,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:0ad78a4,CLOUDID:2d1a6e1f-33fd-4aaa-bb43-d3fd68d9d5ae,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: fed34de23cc611eeb20a276fd37b9834-20230817 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1996567347; Thu, 17 Aug 2023 14:26:27 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 17 Aug 2023 14:26:25 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 17 Aug 2023 14:26:25 +0800 From: Shuijing Li To: , , , , , , , , , CC: , , , , , , Shuijing Li Subject: [PATCH v5,3/4] drm/mediatek: dp: Add the audio divider to mtk_dp_data struct Date: Thu, 17 Aug 2023 14:26:34 +0800 Message-ID: <20230817062635.8786-4-shuijing.li@mediatek.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230817062635.8786-1-shuijing.li@mediatek.com> References: <20230817062635.8786-1-shuijing.li@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Due to the difference of HW, different dividers need to be set. Signed-off-by: Shuijing Li --- Changes in v4: list all configuration for MT8188 and MT8195. per suggestion from the previous thread: https://lore.kernel.org/all/a9d1b9b7ef4780f51574d0bbbe28f6dd109a6ab8.camel@= mediatek.com/ Changes in v3: Separate these two things into two different patches. per suggestion from the previous thread: https://lore.kernel.org/lkml/e2ad22bcba31797f38a12a488d4246a01bf0cb2e.camel= @mediatek.com/ Changes in v2: - change the variables' name to be more descriptive - add a comment that describes the function of mtk_dp_audio_sample_arrange - reduce indentation by doing the inverse check - add a definition of some bits - add support for mediatek, mt8188-edp-tx per suggestion from the previous thread: https://lore.kernel.org/lkml/ac0fcec9-a2fe-06cc-c727-189ef7babe9c@collabora= .com/ --- drivers/gpu/drm/mediatek/mtk_dp.c | 6 +++++- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 18 ++++++++++++------ 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c index be557b6f5854..fb110374ad1f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -140,6 +140,7 @@ struct mtk_dp_data { const struct mtk_dp_efuse_fmt *efuse_fmt; bool audio_supported; bool audio_pkt_in_hblank_area; + u16 audio_m_div2_bit; }; =20 static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = =3D { @@ -648,7 +649,7 @@ static void mtk_dp_audio_sdp_asp_set_channels(struct mt= k_dp *mtk_dp, static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp) { mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, - AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, + mtk_dp->data->audio_m_div2_bit, AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK); } =20 @@ -2623,6 +2624,7 @@ static const struct mtk_dp_data mt8188_dp_data =3D { .efuse_fmt =3D mt8195_dp_efuse_fmt, .audio_supported =3D true, .audio_pkt_in_hblank_area =3D true, + .audio_m_div2_bit =3D MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; =20 static const struct mtk_dp_data mt8195_edp_data =3D { @@ -2630,6 +2632,7 @@ static const struct mtk_dp_data mt8195_edp_data =3D { .smc_cmd =3D MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, .efuse_fmt =3D mt8195_edp_efuse_fmt, .audio_supported =3D false, + .audio_m_div2_bit =3D MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; =20 static const struct mtk_dp_data mt8195_dp_data =3D { @@ -2637,6 +2640,7 @@ static const struct mtk_dp_data mt8195_dp_data =3D { .smc_cmd =3D MTK_DP_SIP_ATF_VIDEO_UNMUTE, .efuse_fmt =3D mt8195_dp_efuse_fmt, .audio_supported =3D true, + .audio_m_div2_bit =3D MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; =20 static const struct of_device_id mtk_dp_of_match[] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediat= ek/mtk_dp_reg.h index f38d6ff12afe..709b79480693 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -159,12 +159,18 @@ #define MTK_DP_ENC0_P0_30BC 0x30bc #define ISRC_CONT_DP_ENC0_P0 BIT(0) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8) -#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8) +#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << 8) +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (5 << 8) +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) #define MTK_DP_ENC0_P0_30D8 0x30d8 #define MTK_DP_ENC0_P0_312C 0x312c #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0) --=20 2.40.1