From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98E50C41513 for ; Wed, 16 Aug 2023 13:20:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245456AbjHPNUI (ORCPT ); Wed, 16 Aug 2023 09:20:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245451AbjHPNTi (ORCPT ); Wed, 16 Aug 2023 09:19:38 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF67C2128 for ; Wed, 16 Aug 2023 06:19:36 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-589f986ab8aso56154117b3.1 for ; Wed, 16 Aug 2023 06:19:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692191976; x=1692796776; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=blfAIhNPC21dqoqqHt/pC7TfIgl1c3ScRB7dutErSxQ=; b=RbjKYyQvpx3SrP19fkp9tDec+vO77AhSw/KcJgSybEhdbBALWEOfA4Ax3TR0aZFyNN K/0K+RW66Wfq0imFBtwZTCQ5tjgLjh+MOaLjBY0GRFCK6+o0WoQgLChRF0CQgoau1uaV qCaFeNrlL9aCqNb95R/sPAhQM6icOBA139ixaOVui8CMBcbJRCzfIUUTXerrnJbuypzx sZV/0j8fA138G0iU+ArQSnKHRCZh20y2VpuTH9wCRBO5D2tAsohYX/9x4jBd7rT7xTDz 4K7C8fBVBQ4NpK0dEpfGptPbNoZXM1eyQcDfNzOPT8N2V7fNE1n+i6PjkkWdolNPCxXd miJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692191976; x=1692796776; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=blfAIhNPC21dqoqqHt/pC7TfIgl1c3ScRB7dutErSxQ=; b=SZK3PcFUgHZf7Za7ufkRZwIfE4rQPWd+eTVf5kr1j4dKkzZ8DeMEkxnaZV3zpAV3NQ WvfW248eTZ1ZQx9jhdsU1mgi5dyI5oH2Yjm263/QUdLQznHf0tLQ7j6w3lur0eP6cs6P GgYKPB5AYw+wWsoU8+H1adVNfLUBvNvyH24SeuBe8/HSrj4H3c7tsNkic/vBNrhDoj3O 5E5oXcguLEUJ3g0JIbxd9Hy4lOk57j+SUs3Hukg4yngNwxdixiUm3CyoQNs6TJP568XD FddjAjNOEvEW63VmlLZaDNeNL9rGwzmb3NjxaVIesT0X5dVHO2DHGefrUhIxbqFntaRu 3wYQ== X-Gm-Message-State: AOJu0Yzmc8l764hOKCjk64yB5AEeay8Css4oNxzQtHJy4ch7ixZYISVO XpHL8o3gYRGqSJD7KKDKHgu8cWAtP98H X-Google-Smtp-Source: AGHT+IHNfTfHV6qRomUbezTh0v0c094p6aZC0Bc8r/7Wd/sNXyyewUqyb5lsrfqqH2xTqdZcMaF3K+7+nAa3 X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:ae98:2006:2abd:3434]) (user=mshavit job=sendgmr) by 2002:a81:4414:0:b0:589:a3d6:2e02 with SMTP id r20-20020a814414000000b00589a3d62e02mr39627ywa.3.1692191976313; Wed, 16 Aug 2023 06:19:36 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:41 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.1.I67ab103c18d882aedc8a08985af1fba70bca084e@changeid> Subject: [PATCH v6 01/10] iommu/arm-smmu-v3: Move ctx_desc out of s1_cfg From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" s1_cfg describes the CD table that is inserted into an SMMU's STEs. It's weird for s1_cfg to also own ctx_desc which describes a CD that is inserted into that table. It is more appropriate for arm_smmu_domain to own ctx_desc. Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Michael Shavit Tested-by: Nicolin Chen --- (no changes since v2) Changes in v2: - Undo over-reaching column alignment change .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 ++++++++++--------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 +++-- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index a5a63b1c947eb..968559d625c40 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -62,7 +62,7 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) return cd; } =20 - smmu_domain =3D container_of(cd, struct arm_smmu_domain, s1_cfg.cd); + smmu_domain =3D container_of(cd, struct arm_smmu_domain, cd); smmu =3D smmu_domain->smmu; =20 ret =3D xa_alloc(&arm_smmu_asid_xa, &new_asid, cd, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9b0dc35056019..bb277ff86f65f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1869,7 +1869,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) * careful, 007. */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); + arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); } else { cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; @@ -1957,7 +1957,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid =3D smmu_domain->s1_cfg.cd.asid; + cmd.tlbi.asid =3D smmu_domain->cd.asid; } else { cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; @@ -2088,7 +2088,7 @@ static void arm_smmu_domain_free(struct iommu_domain = *domain) mutex_lock(&arm_smmu_asid_lock); if (cfg->cdcfg.cdtab) arm_smmu_free_cd_tables(smmu_domain); - arm_smmu_free_asid(&cfg->cd); + arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); } else { struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; @@ -2107,13 +2107,14 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, u32 asid; struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_c= fg.tcr; =20 - refcount_set(&cfg->cd.refs, 1); + refcount_set(&cd->refs, 1); =20 /* Prevent SVA from modifying the ASID until it is written to the CD */ mutex_lock(&arm_smmu_asid_lock); - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, &cfg->cd, + ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, cd, XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); if (ret) goto out_unlock; @@ -2126,23 +2127,23 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, if (ret) goto out_free_asid; =20 - cfg->cd.asid =3D (u16)asid; - cfg->cd.ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; - cfg->cd.tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | + cd->asid =3D (u16)asid; + cd->ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; + cd->tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; - cfg->cd.mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; + cd->mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; =20 /* * Note that this will end up calling arm_smmu_sync_cd() before * the master has been added to the devices list for this domain. * This isn't an issue because the STE hasn't been installed yet. */ - ret =3D arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd); + ret =3D arm_smmu_write_ctx_desc(smmu_domain, 0, cd); if (ret) goto out_free_cd_tables; =20 @@ -2152,7 +2153,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, out_free_cd_tables: arm_smmu_free_cd_tables(smmu_domain); out_free_asid: - arm_smmu_free_asid(&cfg->cd); + arm_smmu_free_asid(cd); out_unlock: mutex_unlock(&arm_smmu_asid_lock); return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index dcab85698a4e2..f841383a55a35 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -599,7 +599,6 @@ struct arm_smmu_ctx_desc_cfg { =20 struct arm_smmu_s1_cfg { struct arm_smmu_ctx_desc_cfg cdcfg; - struct arm_smmu_ctx_desc cd; u8 s1fmt; u8 s1cdmax; }; @@ -724,7 +723,10 @@ struct arm_smmu_domain { =20 enum arm_smmu_domain_stage stage; union { - struct arm_smmu_s1_cfg s1_cfg; + struct { + struct arm_smmu_ctx_desc cd; + struct arm_smmu_s1_cfg s1_cfg; + }; struct arm_smmu_s2_cfg s2_cfg; }; =20 --=20 2.41.0.694.ge786442a9b-goog From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8A4CC04A6A for ; Wed, 16 Aug 2023 13:20:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245463AbjHPNUK (ORCPT ); Wed, 16 Aug 2023 09:20:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245462AbjHPNTn (ORCPT ); Wed, 16 Aug 2023 09:19:43 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CFF32710 for ; Wed, 16 Aug 2023 06:19:41 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-589f7d66f22so32596147b3.3 for ; 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Wed, 16 Aug 2023 06:19:40 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:42 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.2.I1ef1ed19d7786c8176a0d05820c869e650c8d68f@changeid> Subject: [PATCH v6 02/10] iommu/arm-smmu-v3: Replace s1_cfg with cdtab_cfg From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove struct arm_smmu_s1_cfg. This is really just a CD table with a bit of extra information. Move other attributes of the CD table that were held there into the existing CD table structure, struct arm_smmu_ctx_desc_cfg, and replace all usages of arm_smmu_s1_cfg with arm_smmu_ctx_desc_cfg. For clarity, use the name "cd_table" for the variables pointing to arm_smmu_ctx_desc_cfg in the new code instead of cdcfg. A later patch will make this fully consistent. Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Michael Shavit Tested-by: Nicolin Chen --- Changes in v6: - Undo removal of s1fmt and renaming of s1cdmax Changes in v3: - Updated commit messages again - Replace more usages of cdcfg with cdtable (lines that were already touched by this commit anyways). Changes in v2: - Updated commit message drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 41 ++++++++++----------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +--- 2 files changed, 22 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index bb277ff86f65f..5d1977027d2c4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1033,9 +1033,9 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_do= main *smmu_domain, unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->s1_cfg.cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 - if (smmu_domain->s1_cfg.s1fmt =3D=3D STRTAB_STE_0_S1FMT_LINEAR) + if (cdcfg->s1fmt =3D=3D STRTAB_STE_0_S1FMT_LINEAR) return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; =20 idx =3D ssid >> CTXDESC_SPLIT; @@ -1071,7 +1071,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *s= mmu_domain, int ssid, bool cd_live; __le64 *cdptr; =20 - if (WARN_ON(ssid >=3D (1 << smmu_domain->s1_cfg.s1cdmax))) + if (WARN_ON(ssid >=3D (1 << smmu_domain->cd_table.s1cdmax))) return -E2BIG; =20 cdptr =3D arm_smmu_get_cd_ptr(smmu_domain, ssid); @@ -1138,19 +1138,18 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu= _domain *smmu_domain) size_t l1size; size_t max_contexts; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &cfg->cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 - max_contexts =3D 1 << cfg->s1cdmax; + max_contexts =3D 1 << cdcfg->s1cdmax; =20 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || max_contexts <=3D CTXDESC_L2_ENTRIES) { - cfg->s1fmt =3D STRTAB_STE_0_S1FMT_LINEAR; + cdcfg->s1fmt =3D STRTAB_STE_0_S1FMT_LINEAR; cdcfg->num_l1_ents =3D max_contexts; =20 l1size =3D max_contexts * (CTXDESC_CD_DWORDS << 3); } else { - cfg->s1fmt =3D STRTAB_STE_0_S1FMT_64K_L2; + cdcfg->s1fmt =3D STRTAB_STE_0_S1FMT_64K_L2; cdcfg->num_l1_ents =3D DIV_ROUND_UP(max_contexts, CTXDESC_L2_ENTRIES); =20 @@ -1186,7 +1185,7 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_d= omain *smmu_domain) int i; size_t size, l1size; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->s1_cfg.cdcfg; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 if (cdcfg->l1_desc) { size =3D CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); @@ -1276,7 +1275,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, u64 val =3D le64_to_cpu(dst[0]); bool ste_live =3D false; struct arm_smmu_device *smmu =3D NULL; - struct arm_smmu_s1_cfg *s1_cfg =3D NULL; + struct arm_smmu_ctx_desc_cfg *cd_table =3D NULL; struct arm_smmu_s2_cfg *s2_cfg =3D NULL; struct arm_smmu_domain *smmu_domain =3D NULL; struct arm_smmu_cmdq_ent prefetch_cmd =3D { @@ -1294,7 +1293,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, if (smmu_domain) { switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: - s1_cfg =3D &smmu_domain->s1_cfg; + cd_table =3D &smmu_domain->cd_table; break; case ARM_SMMU_DOMAIN_S2: case ARM_SMMU_DOMAIN_NESTED: @@ -1325,7 +1324,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, val =3D STRTAB_STE_0_V; =20 /* Bypass/fault */ - if (!smmu_domain || !(s1_cfg || s2_cfg)) { + if (!smmu_domain || !(cd_table || s2_cfg)) { if (!smmu_domain && disable_bypass) val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else @@ -1344,7 +1343,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, return; } =20 - if (s1_cfg) { + if (cd_table) { u64 strw =3D smmu->features & ARM_SMMU_FEAT_E2H ? STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1; =20 @@ -1360,10 +1359,10 @@ static void arm_smmu_write_strtab_ent(struct arm_sm= mu_master *master, u32 sid, !master->stall_enabled) dst[1] |=3D cpu_to_le64(STRTAB_STE_1_S1STALLD); =20 - val |=3D (s1_cfg->cdcfg.cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | + val |=3D (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | - FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | - FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); + FIELD_PREP(STRTAB_STE_0_S1CDMAX, cd_table->s1cdmax) | + FIELD_PREP(STRTAB_STE_0_S1FMT, cd_table->s1fmt); } =20 if (s2_cfg) { @@ -2082,11 +2081,11 @@ static void arm_smmu_domain_free(struct iommu_domai= n *domain) =20 /* Free the CD and ASID, if we allocated them */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc_cfg *cd_table =3D &smmu_domain->cd_table; =20 /* Prevent SVA from touching the CD while we're freeing it */ mutex_lock(&arm_smmu_asid_lock); - if (cfg->cdcfg.cdtab) + if (cd_table->cdtab) arm_smmu_free_cd_tables(smmu_domain); arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); @@ -2106,7 +2105,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, int ret; u32 asid; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_s1_cfg *cfg =3D &smmu_domain->s1_cfg; + struct arm_smmu_ctx_desc_cfg *cd_table =3D &smmu_domain->cd_table; struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_c= fg.tcr; =20 @@ -2119,7 +2118,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, if (ret) goto out_unlock; =20 - cfg->s1cdmax =3D master->ssid_bits; + cd_table->s1cdmax =3D master->ssid_bits; =20 smmu_domain->stall_enabled =3D master->stall_enabled; =20 @@ -2457,7 +2456,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) ret =3D -EINVAL; goto out_unlock; } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && - master->ssid_bits !=3D smmu_domain->s1_cfg.s1cdmax) { + master->ssid_bits !=3D smmu_domain->cd_table.s1cdmax) { ret =3D -EINVAL; goto out_unlock; } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index f841383a55a35..5f0e7468db5f3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -595,11 +595,8 @@ struct arm_smmu_ctx_desc_cfg { dma_addr_t cdtab_dma; struct arm_smmu_l1_ctx_desc *l1_desc; unsigned int num_l1_ents; -}; - -struct arm_smmu_s1_cfg { - struct arm_smmu_ctx_desc_cfg cdcfg; u8 s1fmt; + /* log2 of the maximum number of CDs supported by this table */ u8 s1cdmax; }; =20 @@ -725,7 +722,7 @@ struct arm_smmu_domain { union { struct { struct arm_smmu_ctx_desc cd; - struct arm_smmu_s1_cfg s1_cfg; + struct arm_smmu_ctx_desc_cfg cd_table; }; struct arm_smmu_s2_cfg s2_cfg; }; --=20 2.41.0.694.ge786442a9b-goog From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8EEEC04FE0 for ; Wed, 16 Aug 2023 13:20:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245474AbjHPNUM (ORCPT ); Wed, 16 Aug 2023 09:20:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245473AbjHPNTs (ORCPT ); Wed, 16 Aug 2023 09:19:48 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F9D126BA for ; Wed, 16 Aug 2023 06:19:46 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-58c4d30c349so29229537b3.2 for ; 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Wed, 16 Aug 2023 06:19:45 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:43 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.3.I875254464d044a8ce8b3a2ad6beb655a4a006456@changeid> Subject: [PATCH v6 03/10] iommu/arm-smmu-v3: Encapsulate ctx_desc_cfg init in alloc_cd_tables From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is slighlty cleaner: arm_smmu_ctx_desc_cfg is initialized in a single function instead of having pieces set ahead-of time by its caller. Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Michael Shavit Tested-by: Nicolin Chen --- (no changes since v1) drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5d1977027d2c4..5bb13fadb41ad 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1132,7 +1132,8 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *s= mmu_domain, int ssid, return 0; } =20 -static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain) +static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_master *master) { int ret; size_t l1size; @@ -1140,6 +1141,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_d= omain *smmu_domain) struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 + cdcfg->s1cdmax =3D master->ssid_bits; max_contexts =3D 1 << cdcfg->s1cdmax; =20 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || @@ -2105,7 +2107,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, int ret; u32 asid; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cd_table =3D &smmu_domain->cd_table; struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_c= fg.tcr; =20 @@ -2118,11 +2119,9 @@ static int arm_smmu_domain_finalise_s1(struct arm_sm= mu_domain *smmu_domain, if (ret) goto out_unlock; =20 - cd_table->s1cdmax =3D master->ssid_bits; - smmu_domain->stall_enabled =3D master->stall_enabled; =20 - ret =3D arm_smmu_alloc_cd_tables(smmu_domain); + ret =3D arm_smmu_alloc_cd_tables(smmu_domain, master); if (ret) goto out_free_asid; =20 --=20 2.41.0.694.ge786442a9b-goog From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCCE0C04FE2 for ; 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Wed, 16 Aug 2023 06:19:50 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:44 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.4.I5aa89c849228794a64146cfe86df21fb71629384@changeid> Subject: [PATCH v6 04/10] iommu/arm-smmu-v3: move stall_enabled to the cd table From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A domain can be attached to multiple masters with different master->stall_enabled values. The stall bit of a CD entry should follow master->stall_enabled and has an inverse relationship with the STE.S1STALLD bit. The stall_enabled bit does not depend on any property of the domain, so move it out of the arm_smmu_domain struct. Move it to the CD table struct so that it can fully describe how CD entries should be written to it. Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Michael Shavit Tested-by: Nicolin Chen --- (no changes since v5) Changes in v5: - Reword commit Changes in v2: - Use a bitfield instead of a bool for stall_enabled drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5bb13fadb41ad..44df7c0926802 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1114,7 +1114,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *s= mmu_domain, int ssid, FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | CTXDESC_CD_0_V; =20 - if (smmu_domain->stall_enabled) + if (smmu_domain->cd_table.stall_enabled) val |=3D CTXDESC_CD_0_S; } =20 @@ -1141,6 +1141,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_d= omain *smmu_domain, struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 + cdcfg->stall_enabled =3D master->stall_enabled; cdcfg->s1cdmax =3D master->ssid_bits; max_contexts =3D 1 << cdcfg->s1cdmax; =20 @@ -2119,8 +2120,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, if (ret) goto out_unlock; =20 - smmu_domain->stall_enabled =3D master->stall_enabled; - ret =3D arm_smmu_alloc_cd_tables(smmu_domain, master); if (ret) goto out_free_asid; @@ -2459,7 +2458,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) ret =3D -EINVAL; goto out_unlock; } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && - smmu_domain->stall_enabled !=3D master->stall_enabled) { + smmu_domain->cd_table.stall_enabled !=3D + master->stall_enabled) { ret =3D -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 5f0e7468db5f3..007758df57610 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -598,6 +598,8 @@ struct arm_smmu_ctx_desc_cfg { u8 s1fmt; /* log2 of the maximum number of CDs supported by this table */ u8 s1cdmax; + /* Whether CD entries in this table have the stall bit set. */ + u8 stall_enabled:1; }; =20 struct arm_smmu_s2_cfg { @@ -715,7 +717,6 @@ struct arm_smmu_domain { struct mutex init_mutex; /* Protects smmu pointer */ =20 struct io_pgtable_ops *pgtbl_ops; - bool stall_enabled; atomic_t nr_ats_masters; =20 enum arm_smmu_domain_stage stage; --=20 2.41.0.694.ge786442a9b-goog From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECEACC04FE1 for ; Wed, 16 Aug 2023 13:20:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245508AbjHPNUO (ORCPT ); Wed, 16 Aug 2023 09:20:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245497AbjHPNT7 (ORCPT ); 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Wed, 16 Aug 2023 06:19:54 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:45 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.5.I219054a6cf538df5bb22f4ada2d9933155d6058c@changeid> Subject: [PATCH v6 05/10] iommu/arm-smmu-v3: Refactor write_ctx_desc From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update arm_smmu_write_ctx_desc and downstream functions to operate on a master instead of an smmu domain. We expect arm_smmu_write_ctx_desc() to only be called to write a CD entry into a CD table owned by the master. Under the hood, arm_smmu_write_ctx_desc still fetches the CD table from the domain that is attached to the master, but a subsequent commit will move that table's ownership to the master. Note that this change isn't a nop refactor since SVA will call arm_smmu_write_ctx_desc in a loop for every master the domain is attached to despite the fact that they all share the same CD table. This loop may look weird but becomes necessary when the CD table becomes per-master in a subsequent commit. Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Michael Shavit Tested-by: Nicolin Chen --- Changes in v6: - Unwind the loop in amr_smmu_write_ctx_desc_devices to NULL out the CD entries we succesfully wrote on failure. - Add a comment clarifying the different usages of amr_smmu_write_ctx_desc_devices Changes in v3: - Add a helper to write a CD to all masters that a domain is attached to. - Fixed an issue where an arm_smmu_write_ctx_desc error return wasn't correctly handled by its caller. Changes in v2: - minor style fixes Changes in v1: - arm_smmu_write_ctx_desc now get's the CD table to write to from the master parameter instead of a distinct parameter. This works well because the CD table being written to should always be owned by the master by the end of this series. This version no longer allows master to be NULL. .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 38 ++++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 51 +++++++------------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- 3 files changed, 54 insertions(+), 37 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 968559d625c40..238ede8368d10 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -37,6 +37,35 @@ struct arm_smmu_bond { =20 static DEFINE_MUTEX(sva_lock); =20 +/* + * Write the CD to the CD tables for all masters that this domain is attac= hed + * to. Note that this is used to update the non-pasid CD entry when SVA ta= kes + * over an existing ASID, as well as to write new pasid CD entries when + * attaching an SVA domain (although the domain passed as the parameter is= the + * RID domain that this domain is mapped to). + */ +static int arm_smmu_write_ctx_desc_devices(struct arm_smmu_domain *smmu_do= main, + int ssid, + struct arm_smmu_ctx_desc *cd) +{ + struct arm_smmu_master *master; + unsigned long flags; + int ret; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + ret =3D arm_smmu_write_ctx_desc(master, ssid, cd); + if (ret) { + list_for_each_entry_from_reverse(master, &smmu_domain->devices, domain_= head) + arm_smmu_write_ctx_desc(master, ssid, NULL); + break; + } + } + + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + return ret; +} + /* * Check if the CPU ASID is available on the SMMU side. If a private conte= xt * descriptor is using it, try to replace it. @@ -80,7 +109,7 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) * be some overlap between use of both ASIDs, until we invalidate the * TLB. */ - arm_smmu_write_ctx_desc(smmu_domain, 0, cd); + arm_smmu_write_ctx_desc_devices(smmu_domain, 0, cd); =20 /* Invalidate TLB entries previously associated with that context */ arm_smmu_tlb_inv_asid(smmu, asid); @@ -222,7 +251,7 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) * DMA may still be running. Keep the cd valid to avoid C_BAD_CD events, * but disable translation. */ - arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, &quiet_cd); + arm_smmu_write_ctx_desc_devices(smmu_domain, mm->pasid, &quiet_cd); =20 arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_mn->cd->asid); arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, 0, 0); @@ -279,7 +308,7 @@ arm_smmu_mmu_notifier_get(struct arm_smmu_domain *smmu_= domain, goto err_free_cd; } =20 - ret =3D arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, cd); + ret =3D arm_smmu_write_ctx_desc_devices(smmu_domain, mm->pasid, cd); if (ret) goto err_put_notifier; =20 @@ -304,7 +333,8 @@ static void arm_smmu_mmu_notifier_put(struct arm_smmu_m= mu_notifier *smmu_mn) return; =20 list_del(&smmu_mn->list); - arm_smmu_write_ctx_desc(smmu_domain, mm->pasid, NULL); + + arm_smmu_write_ctx_desc_devices(smmu_domain, mm->pasid, NULL); =20 /* * If we went through clear(), we've already invalidated, and no diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 44df7c0926802..64c1ec557dbc1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -971,14 +971,12 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *sm= mu, u16 asid) arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); } =20 -static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, +static void arm_smmu_sync_cd(struct arm_smmu_master *master, int ssid, bool leaf) { size_t i; - unsigned long flags; - struct arm_smmu_master *master; struct arm_smmu_cmdq_batch cmds; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct arm_smmu_device *smmu =3D master->smmu; struct arm_smmu_cmdq_ent cmd =3D { .opcode =3D CMDQ_OP_CFGI_CD, .cfgi =3D { @@ -988,15 +986,10 @@ static void arm_smmu_sync_cd(struct arm_smmu_domain *= smmu_domain, }; =20 cmds.num =3D 0; - - spin_lock_irqsave(&smmu_domain->devices_lock, flags); - list_for_each_entry(master, &smmu_domain->devices, domain_head) { - for (i =3D 0; i < master->num_streams; i++) { - cmd.cfgi.sid =3D master->streams[i].id; - arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); - } + for (i =3D 0; i < master->num_streams; i++) { + cmd.cfgi.sid =3D master->streams[i].id; + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); } - spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 arm_smmu_cmdq_batch_submit(smmu, &cmds); } @@ -1026,14 +1019,13 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, WRITE_ONCE(*dst, cpu_to_le64(val)); } =20 -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_domain *smmu_domain, - u32 ssid) +static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssi= d) { __le64 *l1ptr; unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; + struct arm_smmu_device *smmu =3D master->smmu; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->domain->cd_table; =20 if (cdcfg->s1fmt =3D=3D STRTAB_STE_0_S1FMT_LINEAR) return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; @@ -1047,13 +1039,13 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_= domain *smmu_domain, l1ptr =3D cdcfg->cdtab + idx * CTXDESC_L1_DESC_DWORDS; arm_smmu_write_cd_l1_desc(l1ptr, l1_desc); /* An invalid L1CD can be cached */ - arm_smmu_sync_cd(smmu_domain, ssid, false); + arm_smmu_sync_cd(master, ssid, false); } idx =3D ssid & (CTXDESC_L2_ENTRIES - 1); return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS; } =20 -int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, +int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, struct arm_smmu_ctx_desc *cd) { /* @@ -1070,11 +1062,12 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain = *smmu_domain, int ssid, u64 val; bool cd_live; __le64 *cdptr; + struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->domain->cd_table; =20 - if (WARN_ON(ssid >=3D (1 << smmu_domain->cd_table.s1cdmax))) + if (WARN_ON(ssid >=3D (1 << cd_table->s1cdmax))) return -E2BIG; =20 - cdptr =3D arm_smmu_get_cd_ptr(smmu_domain, ssid); + cdptr =3D arm_smmu_get_cd_ptr(master, ssid); if (!cdptr) return -ENOMEM; =20 @@ -1102,7 +1095,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *s= mmu_domain, int ssid, * order. Ensure that it observes valid values before reading * V=3D1. */ - arm_smmu_sync_cd(smmu_domain, ssid, true); + arm_smmu_sync_cd(master, ssid, true); =20 val =3D cd->tcr | #ifdef __BIG_ENDIAN @@ -1114,7 +1107,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *s= mmu_domain, int ssid, FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | CTXDESC_CD_0_V; =20 - if (smmu_domain->cd_table.stall_enabled) + if (cd_table->stall_enabled) val |=3D CTXDESC_CD_0_S; } =20 @@ -1128,7 +1121,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *s= mmu_domain, int ssid, * without first making the structure invalid. */ WRITE_ONCE(cdptr[0], cpu_to_le64(val)); - arm_smmu_sync_cd(smmu_domain, ssid, true); + arm_smmu_sync_cd(master, ssid, true); return 0; } =20 @@ -1138,7 +1131,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_d= omain *smmu_domain, int ret; size_t l1size; size_t max_contexts; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct arm_smmu_device *smmu =3D master->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; =20 cdcfg->stall_enabled =3D master->stall_enabled; @@ -2135,12 +2128,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_sm= mu_domain *smmu_domain, CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; cd->mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; =20 - /* - * Note that this will end up calling arm_smmu_sync_cd() before - * the master has been added to the devices list for this domain. - * This isn't an issue because the STE hasn't been installed yet. - */ - ret =3D arm_smmu_write_ctx_desc(smmu_domain, 0, cd); + ret =3D arm_smmu_write_ctx_desc(master, 0, cd); if (ret) goto out_free_cd_tables; =20 @@ -2458,8 +2446,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) ret =3D -EINVAL; goto out_unlock; } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && - smmu_domain->cd_table.stall_enabled !=3D - master->stall_enabled) { + smmu_domain->cd_table.stall_enabled !=3D master->stall_enabled) { ret =3D -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 007758df57610..00f8e6388848e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -745,7 +745,7 @@ extern struct xarray arm_smmu_asid_xa; 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Wed, 16 Aug 2023 06:19:59 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:46 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.6.Ice063dcf87d1b777a72e008d9e3406d2bcf6d876@changeid> Subject: [PATCH v6 06/10] iommu/arm-smmu-v3: Move CD table to arm_smmu_master From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With this change, each master will now own its own CD table instead of sharing one with other masters attached to the same domain. Attaching a stage 1 domain installs CD entries into the master's CD table. SVA writes its CD entries into each master's CD table if the domain is shared across masters. Also add the device to the devices list before writing the CD to the table so that SVA is always aware of all the CD tables that need re-writing when it updates a CD. Reviewed-by: Jason Gunthorpe Signed-off-by: Michael Shavit Tested-by: Nicolin Chen --- Changes in v6: - Grab the asid lock while writing the RID CD to prevent a race with SVA. - Add the device to the devices list before writing the CD to the table and installing the CD table. - Undo arm_smmu_finalise_s1 rename - Minor comment fix - Consistently check cdtab pointer instead of cdtab_dma Changes in v5: - Clear the 0th CD entry when the domain is detached. Not clearing it caused a bug in arm_smmu_write_ctx_desc which doesn't expect the entry to already be set. Changes in v4: - Added comment about the cd_table's dependency on the iommu core's group mutex. - Narrowed the range of code for which the domain's init_mutex is held on attach since it now only protects the arm_smmu_domain_finalise call. Changes in v2: - Allocate CD table when it's first needed instead of on probe. Changes in v1: - The master's CD table allocation was previously split to a different commit. This change now atomically allocates the new CD table, uses it, and removes the old one. drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 100 +++++++++++--------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +- 2 files changed, 60 insertions(+), 47 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 64c1ec557dbc1..8c5e5fcd55713 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1025,7 +1025,7 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_ma= ster *master, u32 ssid) unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; struct arm_smmu_device *smmu =3D master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; =20 if (cdcfg->s1fmt =3D=3D STRTAB_STE_0_S1FMT_LINEAR) return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; @@ -1062,7 +1062,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *m= aster, int ssid, u64 val; bool cd_live; __le64 *cdptr; - struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->cd_table; =20 if (WARN_ON(ssid >=3D (1 << cd_table->s1cdmax))) return -E2BIG; @@ -1125,14 +1125,13 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master = *master, int ssid, return 0; } =20 -static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master *master) +static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master) { int ret; size_t l1size; size_t max_contexts; struct arm_smmu_device *smmu =3D master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; =20 cdcfg->stall_enabled =3D master->stall_enabled; cdcfg->s1cdmax =3D master->ssid_bits; @@ -1176,12 +1175,12 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu= _domain *smmu_domain, return ret; } =20 -static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) +static void arm_smmu_free_cd_tables(struct arm_smmu_master *master) { int i; size_t size, l1size; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; + struct arm_smmu_device *smmu =3D master->smmu; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; =20 if (cdcfg->l1_desc) { size =3D CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); @@ -1289,7 +1288,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, if (smmu_domain) { switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: - cd_table =3D &smmu_domain->cd_table; + cd_table =3D &master->cd_table; break; case ARM_SMMU_DOMAIN_S2: case ARM_SMMU_DOMAIN_NESTED: @@ -2075,14 +2074,10 @@ static void arm_smmu_domain_free(struct iommu_domai= n *domain) =20 free_io_pgtable_ops(smmu_domain->pgtbl_ops); =20 - /* Free the CD and ASID, if we allocated them */ + /* Free the ASID or VMID */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - struct arm_smmu_ctx_desc_cfg *cd_table =3D &smmu_domain->cd_table; - /* Prevent SVA from touching the CD while we're freeing it */ mutex_lock(&arm_smmu_asid_lock); - if (cd_table->cdtab) - arm_smmu_free_cd_tables(smmu_domain); arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); } else { @@ -2113,10 +2108,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_sm= mu_domain *smmu_domain, if (ret) goto out_unlock; =20 - ret =3D arm_smmu_alloc_cd_tables(smmu_domain, master); - if (ret) - goto out_free_asid; - cd->asid =3D (u16)asid; cd->ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; cd->tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | @@ -2128,17 +2119,9 @@ static int arm_smmu_domain_finalise_s1(struct arm_sm= mu_domain *smmu_domain, CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; cd->mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; =20 - ret =3D arm_smmu_write_ctx_desc(master, 0, cd); - if (ret) - goto out_free_cd_tables; - mutex_unlock(&arm_smmu_asid_lock); return 0; =20 -out_free_cd_tables: - arm_smmu_free_cd_tables(smmu_domain); -out_free_asid: - arm_smmu_free_asid(cd); out_unlock: mutex_unlock(&arm_smmu_asid_lock); return ret; @@ -2400,6 +2383,16 @@ static void arm_smmu_detach_dev(struct arm_smmu_mast= er *master) master->domain =3D NULL; master->ats_enabled =3D false; arm_smmu_install_ste_for_dev(master); + /* + * The table is uninstalled before clearing the CD to prevent an + * unnecessary sync in arm_smmu_write_ctx_desc. Although clearing the + * CD entry isn't strictly required to detach the domain since the + * table is uninstalled anyway, it helps avoid confusion in the call to + * arm_smmu_write_ctx_desc on the next attach (which expects the entry + * to be empty). + */ + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && master->cd_table.cdta= b) + arm_smmu_write_ctx_desc(master, 0, NULL); } =20 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device = *dev) @@ -2434,22 +2427,14 @@ static int arm_smmu_attach_dev(struct iommu_domain = *domain, struct device *dev) if (!smmu_domain->smmu) { smmu_domain->smmu =3D smmu; ret =3D arm_smmu_domain_finalise(domain, master); - if (ret) { + if (ret) smmu_domain->smmu =3D NULL; - goto out_unlock; - } - } else if (smmu_domain->smmu !=3D smmu) { - ret =3D -EINVAL; - goto out_unlock; - } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && - master->ssid_bits !=3D smmu_domain->cd_table.s1cdmax) { + } else if (smmu_domain->smmu !=3D smmu) ret =3D -EINVAL; - goto out_unlock; - } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && - smmu_domain->cd_table.stall_enabled !=3D master->stall_enabled) { - ret =3D -EINVAL; - goto out_unlock; - } + + mutex_unlock(&smmu_domain->init_mutex); + if (ret) + return ret; =20 master->domain =3D smmu_domain; =20 @@ -2463,16 +2448,43 @@ static int arm_smmu_attach_dev(struct iommu_domain = *domain, struct device *dev) if (smmu_domain->stage !=3D ARM_SMMU_DOMAIN_BYPASS) master->ats_enabled =3D arm_smmu_ats_supported(master); =20 - arm_smmu_install_ste_for_dev(master); =20 spin_lock_irqsave(&smmu_domain->devices_lock, flags); list_add(&master->domain_head, &smmu_domain->devices); spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { + if (!master->cd_table.cdtab) { + ret =3D arm_smmu_alloc_cd_tables(master); + if (ret) { + master->domain =3D NULL; + goto out_list_del; + } + } + + /* + * Prevent SVA from concurrently modifying the CD or writing to + * the CD entry + */ + mutex_lock(&arm_smmu_asid_lock); + ret =3D arm_smmu_write_ctx_desc(master, 0, &smmu_domain->cd); + mutex_unlock(&arm_smmu_asid_lock); + if (ret) { + master->domain =3D NULL; + goto out_list_del; + } + } + + arm_smmu_install_ste_for_dev(master); + arm_smmu_enable_ats(master); + return 0; + +out_list_del: + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_del(&master->domain_head); + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 -out_unlock: - mutex_unlock(&smmu_domain->init_mutex); return ret; } =20 @@ -2717,6 +2729,8 @@ static void arm_smmu_release_device(struct device *de= v) arm_smmu_detach_dev(master); arm_smmu_disable_pasid(master); arm_smmu_remove_master(master); + if (master->cd_table.cdtab) + arm_smmu_free_cd_tables(master); kfree(master); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 00f8e6388848e..2f4b832e0deb4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -695,6 +695,8 @@ struct arm_smmu_master { struct arm_smmu_domain *domain; struct list_head domain_head; struct arm_smmu_stream *streams; + /* Locked by the iommu core using the group mutex */ + struct arm_smmu_ctx_desc_cfg cd_table; unsigned int num_streams; bool ats_enabled; bool stall_enabled; @@ -721,11 +723,8 @@ struct arm_smmu_domain { =20 enum arm_smmu_domain_stage stage; union { - struct { struct arm_smmu_ctx_desc cd; - struct arm_smmu_ctx_desc_cfg cd_table; - }; - struct arm_smmu_s2_cfg s2_cfg; + struct arm_smmu_s2_cfg s2_cfg; }; =20 struct iommu_domain domain; --=20 2.41.0.694.ge786442a9b-goog From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 090B2C001E0 for ; Wed, 16 Aug 2023 13:21:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245323AbjHPNUj (ORCPT ); Wed, 16 Aug 2023 09:20:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245503AbjHPNUF (ORCPT ); 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Wed, 16 Aug 2023 06:20:04 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:47 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.7.Iff18df41564b9df82bf40b3ec7af26b87f08ef6e@changeid> Subject: [PATCH v6 07/10] iommu/arm-smmu-v3: Cleanup arm_smmu_domain_finalise From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove unused master parameter now that the CD table is allocated elsewhere. Reviewed-by: Jason Gunthorpe Signed-off-by: Michael Shavit Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen --- (no changes since v5) Changes in v5: - New commit drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8c5e5fcd55713..de87150cd0242 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2090,7 +2090,6 @@ static void arm_smmu_domain_free(struct iommu_domain = *domain) } =20 static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master *master, struct io_pgtable_cfg *pgtbl_cfg) { int ret; @@ -2128,7 +2127,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smm= u_domain *smmu_domain, } =20 static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master *master, struct io_pgtable_cfg *pgtbl_cfg) { int vmid; @@ -2153,8 +2151,7 @@ static int arm_smmu_domain_finalise_s2(struct arm_smm= u_domain *smmu_domain, return 0; } =20 -static int arm_smmu_domain_finalise(struct iommu_domain *domain, - struct arm_smmu_master *master) +static int arm_smmu_domain_finalise(struct iommu_domain *domain) { int ret; unsigned long ias, oas; @@ -2162,7 +2159,6 @@ static int arm_smmu_domain_finalise(struct iommu_doma= in *domain, struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; int (*finalise_stage_fn)(struct arm_smmu_domain *, - struct arm_smmu_master *, struct io_pgtable_cfg *); struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); struct arm_smmu_device *smmu =3D smmu_domain->smmu; @@ -2214,7 +2210,7 @@ static int arm_smmu_domain_finalise(struct iommu_doma= in *domain, domain->geometry.aperture_end =3D (1UL << pgtbl_cfg.ias) - 1; domain->geometry.force_aperture =3D true; =20 - ret =3D finalise_stage_fn(smmu_domain, master, &pgtbl_cfg); + ret =3D finalise_stage_fn(smmu_domain, &pgtbl_cfg); if (ret < 0) { free_io_pgtable_ops(pgtbl_ops); return ret; @@ -2426,7 +2422,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) =20 if (!smmu_domain->smmu) { smmu_domain->smmu =3D smmu; - ret =3D arm_smmu_domain_finalise(domain, master); + ret =3D arm_smmu_domain_finalise(domain); if (ret) smmu_domain->smmu =3D NULL; } else if (smmu_domain->smmu !=3D smmu) --=20 2.41.0.694.ge786442a9b-goog From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E510C04A6A for ; Wed, 16 Aug 2023 13:21:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245480AbjHPNUk (ORCPT ); Wed, 16 Aug 2023 09:20:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245465AbjHPNUK (ORCPT ); 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Wed, 16 Aug 2023 06:20:08 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:48 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.8.I7a8beb615e2520ad395d96df94b9ab9708ee0d9c@changeid> Subject: [PATCH v6 08/10] iommu/arm-smmu-v3: Update comment about STE liveness From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the comment to reflect the fact that the STE is not always installed. arm_smmu_domain_finalise_s1 intentionnaly calls arm_smmu_write_ctx_desc while the STE is not installed. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen --- Changes in v6: - New commit drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index de87150cd0242..3c8bfeca89d5c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1091,7 +1091,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *m= aster, int ssid, cdptr[3] =3D cpu_to_le64(cd->mair); =20 /* - * STE is live, and the SMMU might read dwords of this CD in any + * STE may be live, and the SMMU might read dwords of this CD in any * order. Ensure that it observes valid values before reading * V=3D1. */ --=20 2.41.0.694.ge786442a9b-goog From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F12FC04FDF for ; Wed, 16 Aug 2023 13:21:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245499AbjHPNUn (ORCPT ); Wed, 16 Aug 2023 09:20:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245514AbjHPNUP (ORCPT ); Wed, 16 Aug 2023 09:20:15 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40C3E2711 for ; Wed, 16 Aug 2023 06:20:14 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-d1c693a29a0so7552551276.1 for ; Wed, 16 Aug 2023 06:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692192013; x=1692796813; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Wahm0+n9syTK68V4+8/kXjO64+N5fjxBx7U2bn3Amxs=; b=5X6G7uiEUz25+dwfPfk290Fi7oAijcXS8dxWAYPl3C0idvCWhFxffS/uKyZe16ZlzU erdGHRmPDZES2vTp/CoPIS/5n9kmJTz9XA9vgsEkAKgM+pMlk9BGYAFWkDZEh17yg7xO HLS8lQlUROOod87aQrZnmG9YhQwf24640kNEsuetuYzzw3DPIQx8OBAsQf01fJ/jzgfT OYBd556Y6KMbTcWHGdpMcGODJT3Up26h6QaIdBp6N/nrsaRM3Omj2ueJ9uPWQNAi0ALK t9i/hvQ9M8iRrgxDmB83NzQGytZIDC+bKfU8KELKwBQxYOZH8DaCk8npKwWJ3grgSbuW ib9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692192013; x=1692796813; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Wahm0+n9syTK68V4+8/kXjO64+N5fjxBx7U2bn3Amxs=; b=lDV9TFLfqanBoXFsoDabCZH/6QIwGCe0bP/z6bAJ2LUQ3oG+YD1+nrLNYeKdWHIKmU +xuPPONwTXAEM1cO+YubHq7PsVUHHELP/mjBR8ZmaQ7JvNBkFqpwnKKXVWpCZpjHpp/m aLLSCebgv3btyJhOf6qW5R7ZxjjTulJOv8MPedEADKWD+UMXKHLOb9chNFWVlkavjCYt DWkXPktl7ob15+bSNG928Wj+cNVn4+i4mdOA9omDxR8qLAa7m2MnhtIycP79wcswpbsM 6403WUGTJ06/KLYhE+LDAAH6jcdDD3aJAz9mCjJ+QafwwNBTa2dWrlSyN6GYaBsszkFB GcFw== X-Gm-Message-State: AOJu0Yy0uSDhDurQGhjuEhZc+JSM/Ifrct7lAxo3Ke1T93b8hn1HpNyG xAlJQxqtLiUaevgRl42UkwwOhWoZ8Hnw X-Google-Smtp-Source: AGHT+IGfrAEWxCBxWzZSyOwYafJU+OJBdmpgGQY9CJWSDxC54cz937JgjBYjmMiDVRGJsEgo8GrKs2p0hY4Z X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:ae98:2006:2abd:3434]) (user=mshavit job=sendgmr) by 2002:a25:df07:0:b0:c78:c530:6345 with SMTP id w7-20020a25df07000000b00c78c5306345mr25973ybg.7.1692192013420; Wed, 16 Aug 2023 06:20:13 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:49 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.9.Idedc0f496231e2faab3df057219c5e2d937bbfe4@changeid> Subject: [PATCH v6 09/10] iommu/arm-smmu-v3: Skip cd sync if CD table isn't active From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This commit explicitly keeps track of whether a CD table is installed in an STE so that arm_smmu_sync_cd can skip the sync when unnecessary. This was previously achieved through the domain->devices list, but we are moving to a model where arm_smmu_sync_cd directly operates on a master and the master's CD table instead of a domain. Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Michael Shavit Tested-by: Nicolin Chen --- Happy to drop this commit if we don't think it's useful. (no changes since v5) Changes in v5: - Fix an issue where cd_table.installed wasn't correctly updated. Changes in v3: - Flip the cd_table.installed bit back off when table is detached - re-order the commit later in the series since flipping the installed bit to off isn't obvious when the cd_table is still shared by multiple masters. Changes in v2: - Store field as a bit instead of a bool. Fix comment about STE being live before the sync in write_ctx_desc(). drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 3c8bfeca89d5c..104b8d6ea5972 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -985,6 +985,9 @@ static void arm_smmu_sync_cd(struct arm_smmu_master *ma= ster, }, }; =20 + if (!master->cd_table.installed) + return; + cmds.num =3D 0; for (i =3D 0; i < master->num_streams; i++) { cmd.cfgi.sid =3D master->streams[i].id; @@ -1335,6 +1338,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, */ if (smmu) arm_smmu_sync_ste_for_sid(smmu, sid); + master->cd_table.installed =3D false; return; } =20 @@ -1358,6 +1362,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | FIELD_PREP(STRTAB_STE_0_S1CDMAX, cd_table->s1cdmax) | FIELD_PREP(STRTAB_STE_0_S1FMT, cd_table->s1fmt); + cd_table->installed =3D true; + } else { + master->cd_table.installed =3D false; } =20 if (s2_cfg) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 2f4b832e0deb4..b7a91c8e9b523 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -600,6 +600,8 @@ struct arm_smmu_ctx_desc_cfg { u8 s1cdmax; /* Whether CD entries in this table have the stall bit set. */ u8 stall_enabled:1; + /* Whether this CD table is installed in any STE */ + u8 installed:1; }; =20 struct arm_smmu_s2_cfg { --=20 2.41.0.694.ge786442a9b-goog From nobody Wed Dec 17 21:13:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F769C04E69 for ; Wed, 16 Aug 2023 13:21:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245524AbjHPNUp (ORCPT ); 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Wed, 16 Aug 2023 06:20:17 -0700 (PDT) Date: Wed, 16 Aug 2023 21:18:50 +0800 In-Reply-To: <20230816131925.2521220-1-mshavit@google.com> Mime-Version: 1.0 References: <20230816131925.2521220-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230816211849.v6.10.I5ee79793b444ddb933e8bc1eb7b77e728d7f8350@changeid> Subject: [PATCH v6 10/10] iommu/arm-smmu-v3: Rename cdcfg to cd_table From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cdcfg is a confusing name, especially given other variables with the cfg suffix in this driver. cd_table more clearly describes what is being operated on. Reviewed-by: Jason Gunthorpe Reviewed-by: Nicolin Chen Signed-off-by: Michael Shavit Tested-by: Nicolin Chen --- (no changes since v3) Changes in v3: - Commit message update Changes in v2: - New commit drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 70 ++++++++++----------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 104b8d6ea5972..b27011b2bec9b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1028,18 +1028,18 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_= master *master, u32 ssid) unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; struct arm_smmu_device *smmu =3D master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->cd_table; =20 - if (cdcfg->s1fmt =3D=3D STRTAB_STE_0_S1FMT_LINEAR) - return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; + if (cd_table->s1fmt =3D=3D STRTAB_STE_0_S1FMT_LINEAR) + return cd_table->cdtab + ssid * CTXDESC_CD_DWORDS; =20 idx =3D ssid >> CTXDESC_SPLIT; - l1_desc =3D &cdcfg->l1_desc[idx]; + l1_desc =3D &cd_table->l1_desc[idx]; if (!l1_desc->l2ptr) { if (arm_smmu_alloc_cd_leaf_table(smmu, l1_desc)) return NULL; =20 - l1ptr =3D cdcfg->cdtab + idx * CTXDESC_L1_DESC_DWORDS; + l1ptr =3D cd_table->cdtab + idx * CTXDESC_L1_DESC_DWORDS; arm_smmu_write_cd_l1_desc(l1ptr, l1_desc); /* An invalid L1CD can be cached */ arm_smmu_sync_cd(master, ssid, false); @@ -1134,35 +1134,35 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu= _master *master) size_t l1size; size_t max_contexts; struct arm_smmu_device *smmu =3D master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->cd_table; =20 - cdcfg->stall_enabled =3D master->stall_enabled; - cdcfg->s1cdmax =3D master->ssid_bits; - max_contexts =3D 1 << cdcfg->s1cdmax; + cd_table->stall_enabled =3D master->stall_enabled; + cd_table->s1cdmax =3D master->ssid_bits; + max_contexts =3D 1 << cd_table->s1cdmax; =20 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || max_contexts <=3D CTXDESC_L2_ENTRIES) { - cdcfg->s1fmt =3D STRTAB_STE_0_S1FMT_LINEAR; - cdcfg->num_l1_ents =3D max_contexts; + cd_table->s1fmt =3D STRTAB_STE_0_S1FMT_LINEAR; + cd_table->num_l1_ents =3D max_contexts; =20 l1size =3D max_contexts * (CTXDESC_CD_DWORDS << 3); } else { - cdcfg->s1fmt =3D STRTAB_STE_0_S1FMT_64K_L2; - cdcfg->num_l1_ents =3D DIV_ROUND_UP(max_contexts, + cd_table->s1fmt =3D STRTAB_STE_0_S1FMT_64K_L2; + cd_table->num_l1_ents =3D DIV_ROUND_UP(max_contexts, CTXDESC_L2_ENTRIES); =20 - cdcfg->l1_desc =3D devm_kcalloc(smmu->dev, cdcfg->num_l1_ents, - sizeof(*cdcfg->l1_desc), + cd_table->l1_desc =3D devm_kcalloc(smmu->dev, cd_table->num_l1_ents, + sizeof(*cd_table->l1_desc), GFP_KERNEL); - if (!cdcfg->l1_desc) + if (!cd_table->l1_desc) return -ENOMEM; =20 - l1size =3D cdcfg->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); + l1size =3D cd_table->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); } =20 - cdcfg->cdtab =3D dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma, + cd_table->cdtab =3D dmam_alloc_coherent(smmu->dev, l1size, &cd_table->cdt= ab_dma, GFP_KERNEL); - if (!cdcfg->cdtab) { + if (!cd_table->cdtab) { dev_warn(smmu->dev, "failed to allocate context descriptor\n"); ret =3D -ENOMEM; goto err_free_l1; @@ -1171,9 +1171,9 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_m= aster *master) return 0; =20 err_free_l1: - if (cdcfg->l1_desc) { - devm_kfree(smmu->dev, cdcfg->l1_desc); - cdcfg->l1_desc =3D NULL; + if (cd_table->l1_desc) { + devm_kfree(smmu->dev, cd_table->l1_desc); + cd_table->l1_desc =3D NULL; } return ret; } @@ -1183,30 +1183,30 @@ static void arm_smmu_free_cd_tables(struct arm_smmu= _master *master) int i; size_t size, l1size; struct arm_smmu_device *smmu =3D master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->cd_table; =20 - if (cdcfg->l1_desc) { + if (cd_table->l1_desc) { size =3D CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); =20 - for (i =3D 0; i < cdcfg->num_l1_ents; i++) { - if (!cdcfg->l1_desc[i].l2ptr) + for (i =3D 0; i < cd_table->num_l1_ents; i++) { + if (!cd_table->l1_desc[i].l2ptr) continue; =20 dmam_free_coherent(smmu->dev, size, - cdcfg->l1_desc[i].l2ptr, - cdcfg->l1_desc[i].l2ptr_dma); + cd_table->l1_desc[i].l2ptr, + cd_table->l1_desc[i].l2ptr_dma); } - devm_kfree(smmu->dev, cdcfg->l1_desc); - cdcfg->l1_desc =3D NULL; + devm_kfree(smmu->dev, cd_table->l1_desc); + cd_table->l1_desc =3D NULL; =20 - l1size =3D cdcfg->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); + l1size =3D cd_table->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); } else { - l1size =3D cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3); + l1size =3D cd_table->num_l1_ents * (CTXDESC_CD_DWORDS << 3); } =20 - dmam_free_coherent(smmu->dev, l1size, cdcfg->cdtab, cdcfg->cdtab_dma); - cdcfg->cdtab_dma =3D 0; - cdcfg->cdtab =3D NULL; + dmam_free_coherent(smmu->dev, l1size, cd_table->cdtab, cd_table->cdtab_dm= a); + cd_table->cdtab_dma =3D 0; + cd_table->cdtab =3D NULL; } =20 bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd) --=20 2.41.0.694.ge786442a9b-goog