From nobody Wed Dec 17 23:28:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D224C41513 for ; Wed, 16 Aug 2023 11:26:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244536AbjHPL01 (ORCPT ); Wed, 16 Aug 2023 07:26:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244504AbjHPLZz (ORCPT ); Wed, 16 Aug 2023 07:25:55 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EE0D212B for ; Wed, 16 Aug 2023 04:25:52 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 8960F2FB2; Wed, 16 Aug 2023 13:24:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1692185078; bh=WCGNIXcGcdl4nJn+dx6lcBvQUFqQ55HfWTEz54MJwVw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Pobx7GREq+jxP2D5S9cwrkgVYulAKHsDT35rrBRDgNucTIoQu9HbsG842iTqIO1A4 t/3TLHbRgRNmJMsYgQyI1R8cskIOXJfPTmBkvBk2Lr/IkJe5wqRw1j3TFoCieG5Ivb PQb6UIuNTYahbl42b3FioXAarBVPiy6RVlfhzb1I= From: Tomi Valkeinen Date: Wed, 16 Aug 2023 14:25:08 +0300 Subject: [PATCH v2 05/12] drm/bridge: tc358768: Use struct videomode MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230816-tc358768-v2-5-242b9d5f703a@ideasonboard.com> References: <20230816-tc358768-v2-0-242b9d5f703a@ideasonboard.com> In-Reply-To: <20230816-tc358768-v2-0-242b9d5f703a@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4738; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=WCGNIXcGcdl4nJn+dx6lcBvQUFqQ55HfWTEz54MJwVw=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk3LI1cyiU52QNWyrMoqwKywZcdpedX3eMKPmwu 4irGh3r+BqJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZNyyNQAKCRD6PaqMvJYe 9URSD/9d/CWhuuFgasgn/wBnjZOa9QJezas5p4Mq+uKptu+IRpybFzC6w1Sf8TQJG2XZ5bC1AGO wK1P2zL4Tyrm2RI6Ky+FNwbkRt0YjaQaFrX1cw7blftTmvmlgCfOQZszCKX/wVOQ9+rZnICQrTS Kof4rXhlPL3D02EikOOo60SFIzbzckq5tFWt4F7I6x2LEFDDph5iRQtc1bnIJlVRsZ7//0xipqH phgbpxWPopwUua5wFnogl+H9YXxZIrp3DZCVVGC//RudSCqDWZbPvtMkBNmkaigpQr2HX5ZlmON xo5o3WYuWpVxUNvPW6NBlKKBKRaOVwAnX0qYmDF37UGKLgCRGGToNLY0LMFeGXn0+BwJ3HDL7zq +aWTqZfigv+wGMcBsCvkE4XIm7zkVR+WzR4yfKRzwCjaVggbeppkLRI1em1+mKTNNFBosF7ayOQ jx96eZX8qbAATzsQ+mN2py3gboMC7Z9Rqwz+/b9M44JktRU6+WeCqlrkAAfrjvSDL9zmFqcrLuV SbNE93YWe3lAowDTHsQKgx9ql31Lck7ca5V3mFh/8iNZlUnKvHF9jd0KwDqJjo8OqHSiehD6WMB EdofYdnyQ5zysa9FRuvG+3R0BfLsgyEvFkj9C7xXTp31yt+s4ZOyIxbjlyXErdDGfbNfkqvRE/I pMfkbVgY4kaW12w== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The TC358768 documentation uses HFP, HBP, etc. values to deal with the video mode, while the driver currently uses the DRM display mode (htotal, hsync_start, etc). Change the driver to convert the DRM display mode to struct videomode, which then allows us to use the same units the documentation uses. This makes it much easier to work on the code when using the TC358768 documentation as a reference. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 45 +++++++++++++++++++++--------------= ---- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index d5831a1236e9..9b633038af33 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -650,6 +650,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) u32 dsiclk, dsibclk, video_start; const u32 internal_delay =3D 40; int ret, i; + struct videomode vm; =20 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling bac= k to continuous\n"); @@ -673,6 +674,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) return; } =20 + drm_display_mode_to_videomode(mode, &vm); + dsiclk =3D priv->dsiclk; dsibclk =3D dsiclk / 4; =20 @@ -681,28 +684,28 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) switch (dsi_dev->format) { case MIPI_DSI_FMT_RGB888: val |=3D (0x3 << 4); - hact =3D mode->hdisplay * 3; - video_start =3D (mode->htotal - mode->hsync_start) * 3; + hact =3D vm.hactive * 3; + video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: val |=3D (0x4 << 4); - hact =3D mode->hdisplay * 3; - video_start =3D (mode->htotal - mode->hsync_start) * 3; + hact =3D vm.hactive * 3; + video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; break; =20 case MIPI_DSI_FMT_RGB666_PACKED: val |=3D (0x4 << 4) | BIT(3); - hact =3D mode->hdisplay * 18 / 8; - video_start =3D (mode->htotal - mode->hsync_start) * 18 / 8; + hact =3D vm.hactive * 18 / 8; + video_start =3D (vm.hsync_len + vm.hback_porch) * 18 / 8; data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; =20 case MIPI_DSI_FMT_RGB565: val |=3D (0x5 << 4); - hact =3D mode->hdisplay * 2; - video_start =3D (mode->htotal - mode->hsync_start) * 2; + hact =3D vm.hactive * 2; + video_start =3D (vm.hsync_len + vm.hback_porch) * 2; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: @@ -814,43 +817,43 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_DSI_EVENT, 0); =20 /* vact */ - tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); + tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); =20 /* vsw */ - tc358768_write(priv, TC358768_DSI_VSW, - mode->vsync_end - mode->vsync_start); + tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len); + /* vbp */ - tc358768_write(priv, TC358768_DSI_VBPR, - mode->vtotal - mode->vsync_end); + tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); =20 /* hsw * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->hsync_end - mode->hsync_start) * + val =3D (u32)div_u64(vm.hsync_len * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 /* hbp * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->htotal - mode->hsync_end) * + val =3D (u32)div_u64(vm.hback_porch * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HBPR, val); } else { /* Set event mode */ tc358768_write(priv, TC358768_DSI_EVENT, 1); =20 /* vact */ - tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); + tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); =20 /* vsw (+ vbp) */ tc358768_write(priv, TC358768_DSI_VSW, - mode->vtotal - mode->vsync_start); + vm.vsync_len + vm.vback_porch); + /* vbp (not used in event mode) */ tc358768_write(priv, TC358768_DSI_VBPR, 0); =20 /* (hsw + hbp) * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->htotal - mode->hsync_start) * + val =3D (u32)div_u64((vm.hsync_len + vm.hback_porch) * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 /* hbp (not used in event mode) */ --=20 2.34.1