From nobody Tue Dec 16 19:58:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7164C001DE for ; Tue, 15 Aug 2023 06:13:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234894AbjHOGMs (ORCPT ); Tue, 15 Aug 2023 02:12:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234879AbjHOGLz (ORCPT ); Tue, 15 Aug 2023 02:11:55 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57BCE1BDA; Mon, 14 Aug 2023 23:11:52 -0700 (PDT) Received: from kwepemm600007.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RQ1666zywztRv2; Tue, 15 Aug 2023 14:08:14 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemm600007.china.huawei.com (7.193.23.208) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 15 Aug 2023 14:11:49 +0800 From: Jijie Shao To: , , , , , CC: , , , , , Subject: [PATCH net-next 3/4] net: hns3: Support tlv in regs data for HNS3 VF driver Date: Tue, 15 Aug 2023 14:06:40 +0800 Message-ID: <20230815060641.3551665-4-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20230815060641.3551665-1-shaojijie@huawei.com> References: <20230815060641.3551665-1-shaojijie@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemm600007.china.huawei.com (7.193.23.208) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The dump register function is being refactored. The third step in refactoring is to support tlv info in regs data for HNS3 PF driver. Currently, if we use "ethtool -d" to dump regs value, the output is as follows: offset1: 00 01 02 03 04 05 ... offset2=EF=BC=9A10 11 12 13 14 15 ... ...... We can't get the value of a register directly. This patch deletes the original separator information and add tag_len_value information in regs data. ethtool can parse register data in key-value format by -d command. a patch will be added to the ethtool to parse regs data in the following format: reg1 : value2 reg2 : value2 ...... Signed-off-by: Jijie Shao Reviewed-by: Leon Romanovsky --- .../hisilicon/hns3/hns3vf/hclgevf_regs.c | 85 +++++++++++++------ 1 file changed, 61 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c b/dr= ivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c index 197ab733306b..65b9dcd38137 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c @@ -57,23 +57,67 @@ static const u32 tqp_intr_reg_addr_list[] =3D {HCLGEVF_= TQP_INTR_CTRL_REG, HCLGEVF_TQP_INTR_GL2_REG, HCLGEVF_TQP_INTR_RL_REG}; =20 -#define MAX_SEPARATE_NUM 4 -#define SEPARATOR_VALUE 0xFDFCFBFA -#define REG_NUM_PER_LINE 4 -#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) +enum hclgevf_reg_tag { + HCLGEVF_REG_TAG_CMDQ =3D 0, + HCLGEVF_REG_TAG_COMMON, + HCLGEVF_REG_TAG_RING, + HCLGEVF_REG_TAG_TQP_INTR, +}; + +#pragma pack(4) +struct hclgevf_reg_tlv { + u16 tag; + u16 len; +}; + +struct hclgevf_reg_header { + u64 magic_number; + u8 is_vf; + u8 rsv[7]; +}; + +#pragma pack() + +#define HCLGEVF_REG_TLV_SIZE sizeof(struct hclgevf_reg_tlv) +#define HCLGEVF_REG_HEADER_SIZE sizeof(struct hclgevf_reg_header) +#define HCLGEVF_REG_TLV_SPACE (sizeof(struct hclgevf_reg_tlv) / sizeof(u3= 2)) +#define HCLGEVF_REG_HEADER_SPACE (sizeof(struct hclgevf_reg_header) / size= of(u32)) +#define HCLGEVF_REG_MAGIC_NUMBER 0x686e733372656773 /* meaning is hns3regs= */ + +static u32 hclgevf_reg_get_header(void *data) +{ + struct hclgevf_reg_header *header =3D data; + + header->magic_number =3D HCLGEVF_REG_MAGIC_NUMBER; + header->is_vf =3D 0x1; + + return HCLGEVF_REG_HEADER_SPACE; +} + +static u32 hclgevf_reg_get_tlv(u32 tag, u32 regs_num, void *data) +{ + struct hclgevf_reg_tlv *tlv =3D data; + + tlv->tag =3D tag; + tlv->len =3D regs_num * sizeof(u32) + HCLGEVF_REG_TLV_SIZE; + + return HCLGEVF_REG_TLV_SPACE; +} =20 int hclgevf_get_regs_len(struct hnae3_handle *handle) { - int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; struct hclgevf_dev *hdev =3D hclgevf_ae_get_hdev(handle); + int cmdq_len, common_len, ring_len, tqp_intr_len; =20 - cmdq_lines =3D sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1; - common_lines =3D sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1; - ring_lines =3D sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1; - tqp_intr_lines =3D sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1; + cmdq_len =3D HCLGEVF_REG_TLV_SIZE + sizeof(cmdq_reg_addr_list); + common_len =3D HCLGEVF_REG_TLV_SIZE + sizeof(common_reg_addr_list); + ring_len =3D HCLGEVF_REG_TLV_SIZE + sizeof(ring_reg_addr_list); + tqp_intr_len =3D HCLGEVF_REG_TLV_SIZE + sizeof(tqp_intr_reg_addr_list); =20 - return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps + - tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE; + /* return the total length of all register values */ + return HCLGEVF_REG_HEADER_SIZE + cmdq_len + common_len + + tqp_intr_len * (hdev->num_msi_used - 1) + + ring_len * hdev->num_tqps; } =20 void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, @@ -83,45 +127,38 @@ void hclgevf_get_regs(struct hnae3_handle *handle, u32= *version, #define HCLGEVF_RING_INT_REG_OFFSET 0x4 =20 struct hclgevf_dev *hdev =3D hclgevf_ae_get_hdev(handle); - int i, j, reg_um, separator_num; + int i, j, reg_um; u32 *reg =3D data; =20 *version =3D hdev->fw_version; + reg +=3D hclgevf_reg_get_header(reg); =20 /* fetching per-VF registers values from VF PCIe register space */ reg_um =3D sizeof(cmdq_reg_addr_list) / sizeof(u32); - separator_num =3D MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; + reg +=3D hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_CMDQ, reg_um, reg); for (i =3D 0; i < reg_um; i++) *reg++ =3D hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; =20 reg_um =3D sizeof(common_reg_addr_list) / sizeof(u32); - separator_num =3D MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; + reg +=3D hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_COMMON, reg_um, reg); for (i =3D 0; i < reg_um; i++) *reg++ =3D hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; =20 reg_um =3D sizeof(ring_reg_addr_list) / sizeof(u32); - separator_num =3D MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; for (j =3D 0; j < hdev->num_tqps; j++) { + reg +=3D hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_um, reg); for (i =3D 0; i < reg_um; i++) *reg++ =3D hclgevf_read_dev(&hdev->hw, ring_reg_addr_list[i] + HCLGEVF_RING_REG_OFFSET * j); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; } =20 reg_um =3D sizeof(tqp_intr_reg_addr_list) / sizeof(u32); - separator_num =3D MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE; for (j =3D 0; j < hdev->num_msi_used - 1; j++) { + reg +=3D hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_TQP_INTR, reg_um, reg); for (i =3D 0; i < reg_um; i++) *reg++ =3D hclgevf_read_dev(&hdev->hw, tqp_intr_reg_addr_list[i] + HCLGEVF_RING_INT_REG_OFFSET * j); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; } } --=20 2.30.0