From nobody Tue Dec 16 19:58:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12BC9C41513 for ; Tue, 15 Aug 2023 06:13:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234955AbjHOGNB (ORCPT ); Tue, 15 Aug 2023 02:13:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235024AbjHOGLz (ORCPT ); Tue, 15 Aug 2023 02:11:55 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57EE71BE1; Mon, 14 Aug 2023 23:11:51 -0700 (PDT) Received: from kwepemm600007.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RQ18k3QyJzrSD0; Tue, 15 Aug 2023 14:10:30 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemm600007.china.huawei.com (7.193.23.208) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 15 Aug 2023 14:11:49 +0800 From: Jijie Shao To: , , , , , CC: , , , , , Subject: [PATCH net-next 2/4] net: hns3: Support tlv in regs data for HNS3 PF driver Date: Tue, 15 Aug 2023 14:06:39 +0800 Message-ID: <20230815060641.3551665-3-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20230815060641.3551665-1-shaojijie@huawei.com> References: <20230815060641.3551665-1-shaojijie@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemm600007.china.huawei.com (7.193.23.208) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The dump register function is being refactored. The second step in refactoring is to support tlv info in regs data for HNS3 PF driver. Currently, if we use "ethtool -d" to dump regs value, the output is as follows: offset1: 00 01 02 03 04 05 ... offset2=EF=BC=9A10 11 12 13 14 15 ... ...... We can't get the value of a register directly. This patch deletes the original separator information and add tag_len_value information in regs data. ethtool can parse register data in key-value format by -d command. a patch will be added to the ethtool to parse regs data in the following format: reg1 : value2 reg2 : value2 ...... Signed-off-by: Jijie Shao Reviewed-by: Leon Romanovsky --- .../hisilicon/hns3/hns3pf/hclge_regs.c | 167 +++++++++++------- 1 file changed, 102 insertions(+), 65 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c b/driv= ers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c index e56644394875..734e5f757b9c 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c @@ -106,12 +106,66 @@ static const enum hclge_opcode_type hclge_dfx_reg_opc= ode_list[] =3D { HCLGE_OPC_DFX_SSU_REG_2 }; =20 -#define MAX_SEPARATE_NUM 4 -#define SEPARATOR_VALUE 0xFDFCFBFA -#define REG_NUM_PER_LINE 4 -#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) -#define REG_SEPARATOR_LINE 1 -#define REG_NUM_REMAIN_MASK 3 +enum hclge_reg_tag { + HCLGE_REG_TAG_CMDQ =3D 0, + HCLGE_REG_TAG_COMMON, + HCLGE_REG_TAG_RING, + HCLGE_REG_TAG_TQP_INTR, + HCLGE_REG_TAG_QUERY_32_BIT, + HCLGE_REG_TAG_QUERY_64_BIT, + HCLGE_REG_TAG_DFX_BIOS_COMMON, + HCLGE_REG_TAG_DFX_SSU_0, + HCLGE_REG_TAG_DFX_SSU_1, + HCLGE_REG_TAG_DFX_IGU_EGU, + HCLGE_REG_TAG_DFX_RPU_0, + HCLGE_REG_TAG_DFX_RPU_1, + HCLGE_REG_TAG_DFX_NCSI, + HCLGE_REG_TAG_DFX_RTC, + HCLGE_REG_TAG_DFX_PPP, + HCLGE_REG_TAG_DFX_RCB, + HCLGE_REG_TAG_DFX_TQP, + HCLGE_REG_TAG_DFX_SSU_2, +}; + +#pragma pack(4) +struct hclge_reg_tlv { + u16 tag; + u16 len; +}; + +struct hclge_reg_header { + u64 magic_number; + u8 is_vf; + u8 rsv[7]; +}; + +#pragma pack() + +#define HCLGE_REG_TLV_SIZE sizeof(struct hclge_reg_tlv) +#define HCLGE_REG_HEADER_SIZE sizeof(struct hclge_reg_header) +#define HCLGE_REG_TLV_SPACE (sizeof(struct hclge_reg_tlv) / sizeof(u32)) +#define HCLGE_REG_HEADER_SPACE (sizeof(struct hclge_reg_header) / sizeof(u= 32)) +#define HCLGE_REG_MAGIC_NUMBER 0x686e733372656773 /* meaning is hns3regs */ + +static u32 hclge_reg_get_header(void *data) +{ + struct hclge_reg_header *header =3D data; + + header->magic_number =3D HCLGE_REG_MAGIC_NUMBER; + header->is_vf =3D 0x0; + + return HCLGE_REG_HEADER_SPACE; +} + +static u32 hclge_reg_get_tlv(u32 tag, u32 regs_num, void *data) +{ + struct hclge_reg_tlv *tlv =3D data; + + tlv->tag =3D tag; + tlv->len =3D regs_num * sizeof(u32) + HCLGE_REG_TLV_SIZE; + + return HCLGE_REG_TLV_SPACE; +} =20 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, void *data) @@ -291,31 +345,28 @@ static int hclge_dfx_reg_cmd_send(struct hclge_dev *h= dev, static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_nu= m, void *data) { - int entries_per_desc, reg_num, separator_num, desc_index, index, i; + int entries_per_desc, reg_num, desc_index, index, i; struct hclge_desc *desc =3D desc_src; u32 *reg =3D data; =20 entries_per_desc =3D ARRAY_SIZE(desc->data); reg_num =3D entries_per_desc * bd_num; - separator_num =3D REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK); for (i =3D 0; i < reg_num; i++) { index =3D i % entries_per_desc; desc_index =3D i / entries_per_desc; *reg++ =3D le32_to_cpu(desc[desc_index].data[index]); } - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; =20 - return reg_num + separator_num; + return reg_num; } =20 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len) { u32 dfx_reg_type_num =3D ARRAY_SIZE(hclge_dfx_bd_offset_list); - int data_len_per_desc, bd_num; + int data_len_per_desc; int *bd_num_list; - u32 data_len, i; int ret; + u32 i; =20 bd_num_list =3D kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); if (!bd_num_list) @@ -330,11 +381,8 @@ static int hclge_get_dfx_reg_len(struct hclge_dev *hde= v, int *len) =20 data_len_per_desc =3D sizeof_field(struct hclge_desc, data); *len =3D 0; - for (i =3D 0; i < dfx_reg_type_num; i++) { - bd_num =3D bd_num_list[i]; - data_len =3D data_len_per_desc * bd_num; - *len +=3D (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE; - } + for (i =3D 0; i < dfx_reg_type_num; i++) + *len +=3D bd_num_list[i] * data_len_per_desc + HCLGE_REG_TLV_SIZE; =20 out: kfree(bd_num_list); @@ -383,6 +431,9 @@ static int hclge_get_dfx_reg(struct hclge_dev *hdev, vo= id *data) break; } =20 + reg +=3D hclge_reg_get_tlv(HCLGE_REG_TAG_DFX_BIOS_COMMON + i, + ARRAY_SIZE(desc_src->data) * bd_num, + reg); reg +=3D hclge_dfx_reg_fetch_data(desc_src, bd_num, reg); } =20 @@ -398,50 +449,43 @@ static int hclge_fetch_pf_reg(struct hclge_dev *hdev,= void *data, #define HCLGE_RING_REG_OFFSET 0x200 #define HCLGE_RING_INT_REG_OFFSET 0x4 =20 - int i, j, reg_num, separator_num; + int i, j, reg_num; int data_num_sum; u32 *reg =3D data; =20 /* fetching per-PF registers valus from PF PCIe register space */ reg_num =3D ARRAY_SIZE(cmdq_reg_addr_list); - separator_num =3D MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); + reg +=3D hclge_reg_get_tlv(HCLGE_REG_TAG_CMDQ, reg_num, reg); for (i =3D 0; i < reg_num; i++) *reg++ =3D hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; - data_num_sum =3D reg_num + separator_num; + data_num_sum =3D reg_num + HCLGE_REG_TLV_SPACE; =20 reg_num =3D ARRAY_SIZE(common_reg_addr_list); - separator_num =3D MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); + reg +=3D hclge_reg_get_tlv(HCLGE_REG_TAG_COMMON, reg_num, reg); for (i =3D 0; i < reg_num; i++) *reg++ =3D hclge_read_dev(&hdev->hw, common_reg_addr_list[i]); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; - data_num_sum +=3D reg_num + separator_num; + data_num_sum +=3D reg_num + HCLGE_REG_TLV_SPACE; =20 reg_num =3D ARRAY_SIZE(ring_reg_addr_list); - separator_num =3D MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); for (j =3D 0; j < kinfo->num_tqps; j++) { + reg +=3D hclge_reg_get_tlv(HCLGE_REG_TAG_RING, reg_num, reg); for (i =3D 0; i < reg_num; i++) *reg++ =3D hclge_read_dev(&hdev->hw, ring_reg_addr_list[i] + HCLGE_RING_REG_OFFSET * j); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; } - data_num_sum +=3D (reg_num + separator_num) * kinfo->num_tqps; + data_num_sum +=3D (reg_num + HCLGE_REG_TLV_SPACE) * kinfo->num_tqps; =20 reg_num =3D ARRAY_SIZE(tqp_intr_reg_addr_list); - separator_num =3D MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); for (j =3D 0; j < hdev->num_msi_used - 1; j++) { + reg +=3D hclge_reg_get_tlv(HCLGE_REG_TAG_TQP_INTR, reg_num, reg); for (i =3D 0; i < reg_num; i++) *reg++ =3D hclge_read_dev(&hdev->hw, tqp_intr_reg_addr_list[i] + HCLGE_RING_INT_REG_OFFSET * j); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; } - data_num_sum +=3D (reg_num + separator_num) * (hdev->num_msi_used - 1); + data_num_sum +=3D (reg_num + HCLGE_REG_TLV_SPACE) * + (hdev->num_msi_used - 1); =20 return data_num_sum; } @@ -473,12 +517,12 @@ static int hclge_get_regs_num(struct hclge_dev *hdev,= u32 *regs_num_32_bit, =20 int hclge_get_regs_len(struct hnae3_handle *handle) { - int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; struct hnae3_knic_private_info *kinfo =3D &handle->kinfo; struct hclge_vport *vport =3D hclge_get_vport(handle); - struct hclge_dev *hdev =3D vport->back; int regs_num_32_bit, regs_num_64_bit, dfx_regs_len; - int regs_lines_32_bit, regs_lines_64_bit; + int cmdq_len, common_len, ring_len, tqp_intr_len; + int regs_len_32_bit, regs_len_64_bit; + struct hclge_dev *hdev =3D vport->back; int ret; =20 ret =3D hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); @@ -495,22 +539,17 @@ int hclge_get_regs_len(struct hnae3_handle *handle) return ret; } =20 - cmdq_lines =3D sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + - REG_SEPARATOR_LINE; - common_lines =3D sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + - REG_SEPARATOR_LINE; - ring_lines =3D sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + - REG_SEPARATOR_LINE; - tqp_intr_lines =3D sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + - REG_SEPARATOR_LINE; - regs_lines_32_bit =3D regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE + - REG_SEPARATOR_LINE; - regs_lines_64_bit =3D regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE + - REG_SEPARATOR_LINE; - - return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps + - tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit + - regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len; + cmdq_len =3D HCLGE_REG_TLV_SIZE + sizeof(cmdq_reg_addr_list); + common_len =3D HCLGE_REG_TLV_SIZE + sizeof(common_reg_addr_list); + ring_len =3D HCLGE_REG_TLV_SIZE + sizeof(ring_reg_addr_list); + tqp_intr_len =3D HCLGE_REG_TLV_SIZE + sizeof(tqp_intr_reg_addr_list); + regs_len_32_bit =3D HCLGE_REG_TLV_SIZE + regs_num_32_bit * sizeof(u32); + regs_len_64_bit =3D HCLGE_REG_TLV_SIZE + regs_num_64_bit * sizeof(u64); + + /* return the total length of all register values */ + return HCLGE_REG_HEADER_SIZE + cmdq_len + common_len + ring_len * + kinfo->num_tqps + tqp_intr_len * (hdev->num_msi_used - 1) + + regs_len_32_bit + regs_len_64_bit + dfx_regs_len; } =20 void hclge_get_regs(struct hnae3_handle *handle, u32 *version, @@ -522,8 +561,8 @@ void hclge_get_regs(struct hnae3_handle *handle, u32 *v= ersion, struct hclge_vport *vport =3D hclge_get_vport(handle); struct hclge_dev *hdev =3D vport->back; u32 regs_num_32_bit, regs_num_64_bit; - int i, reg_num, separator_num, ret; u32 *reg =3D data; + int ret; =20 *version =3D hdev->fw_version; =20 @@ -534,31 +573,29 @@ void hclge_get_regs(struct hnae3_handle *handle, u32 = *version, return; } =20 + reg +=3D hclge_reg_get_header(reg); reg +=3D hclge_fetch_pf_reg(hdev, reg, kinfo); =20 + reg +=3D hclge_reg_get_tlv(HCLGE_REG_TAG_QUERY_32_BIT, + regs_num_32_bit, reg); ret =3D hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg); if (ret) { dev_err(&hdev->pdev->dev, "Get 32 bit register failed, ret =3D %d.\n", ret); return; } - reg_num =3D regs_num_32_bit; - reg +=3D reg_num; - separator_num =3D MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; + reg +=3D regs_num_32_bit; =20 + reg +=3D hclge_reg_get_tlv(HCLGE_REG_TAG_QUERY_64_BIT, + regs_num_64_bit * + HCLGE_REG_64_BIT_SPACE_MULTIPLE, reg); ret =3D hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg); if (ret) { dev_err(&hdev->pdev->dev, "Get 64 bit register failed, ret =3D %d.\n", ret); return; } - reg_num =3D regs_num_64_bit * HCLGE_REG_64_BIT_SPACE_MULTIPLE; - reg +=3D reg_num; - separator_num =3D MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); - for (i =3D 0; i < separator_num; i++) - *reg++ =3D SEPARATOR_VALUE; + reg +=3D regs_num_64_bit * HCLGE_REG_64_BIT_SPACE_MULTIPLE; =20 ret =3D hclge_get_dfx_reg(hdev, reg); if (ret) --=20 2.30.0