From nobody Thu Dec 18 18:57:12 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A046C07E8A for ; Tue, 15 Aug 2023 00:48:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233768AbjHOAsi (ORCPT ); Mon, 14 Aug 2023 20:48:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233539AbjHOAsY (ORCPT ); Mon, 14 Aug 2023 20:48:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73AB71710 for ; Mon, 14 Aug 2023 17:48:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0EAD463FE9 for ; Tue, 15 Aug 2023 00:48:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 342FFC433C7; Tue, 15 Aug 2023 00:48:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692060500; bh=+ggOxNlO23GQYPQs86USV0qxaHwyNkCE70FT4o/Cdb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PKlrCQUi2gLF06LPw1KAAhsC7djngjGIZumeC4G0AwhKlZg203W0347Gn35YnCCQR qXwHdo28JesYiJr5sCG3gbqSJjGDMzzZcnDwlsPdRcg5Dkp55cTz8IQD0oM1OC7sEJ z8wJ6ejLtv3g+wXxA1enTbngLf2nHMPGmpb1tVQO3KvSps1t4da7ID0SkeC154IAyP a/DnOVco/FdawyA8DEjkMUcQ/WIbBi3L176Up7c7BsUiEyZqve5dOaLNzReyRfb6AE eBSwqvotPTwYxjKk9pB3gy4BvuCW3UrrDSUlEtV5ke2ZM2geBlcEENovrkGx9lxAmF mz2RbJTVXcb3w== From: Vineet Gupta To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Shahab Vahedi , Alexey Brodkin , Vineet Gupta Subject: [PATCH 05/20] ARC: boot log: eliminate struct cpuinfo_arc #1: mm Date: Mon, 14 Aug 2023 17:47:58 -0700 Message-Id: <20230815004813.555115-6-vgupta@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230815004813.555115-1-vgupta@kernel.org> References: <20230815004813.555115-1-vgupta@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is first step in eliminating struct cpuinfo_arc[NR_CPUS] Back when we had just ARCompact ISA, the idea was to read/bit-fiddle the BCRs once and and cache decoded information in a global struct ready to use. With ARCv2 it was modified to contained abstract / ISA agnostic information. However with ARCv3 there 's too much disparity to abstract in common structures. So drop the entire decode once and store paradigm. Afterall there's only 2 users of this machinery anyways: boot printing and cat /proc/cpuinfo. None is performance critical to warrant locking away resident memory per cpu. This patch is first step in that direction - decouples struct cpuinfo_arc_mmu from global struct cpuinfo_arc - mmu code still has a trimmed down static version of struct cpuinfo_arc_mmu to cache information needed in performance critical code such as tlb flush routines - folds read_decode_mmu_bcr() into arc_mmu_mumbojumbo() - setup_processor() directly calls arc_mmu_init() and not via arc_cpu_init() Signed-off-by: Vineet Gupta --- arch/arc/include/asm/arcregs.h | 27 +++++++--- arch/arc/include/asm/setup.h | 1 - arch/arc/kernel/setup.c | 4 +- arch/arc/mm/tlb.c | 92 +++++++++++++--------------------- 4 files changed, 57 insertions(+), 67 deletions(-) diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 2162023195c5..af00cbe9b850 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -185,6 +185,27 @@ struct bcr_uarch_build_arcv2 { #endif }; =20 +struct bcr_mmu_3 { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4, + u_itlb:4, u_dtlb:4; +#else + unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4, + ways:4, ver:8; +#endif +}; + +struct bcr_mmu_4 { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, + n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; +#else + /* DTLB ITLB JES JE JA */ + unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, + pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; +#endif +}; + struct bcr_mpy { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; @@ -307,11 +328,6 @@ struct bcr_generic { * Generic structures to hold build configuration used at runtime */ =20 -struct cpuinfo_arc_mmu { - unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1; - unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8; -}; - struct cpuinfo_arc_cache { unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4; }; @@ -326,7 +342,6 @@ struct cpuinfo_arc_ccm { =20 struct cpuinfo_arc { struct cpuinfo_arc_cache icache, dcache, slc; - struct cpuinfo_arc_mmu mmu; struct cpuinfo_arc_bpu bpu; struct bcr_identity core; struct bcr_isa_arcv2 isa; diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h index 374138832c5a..76443f198778 100644 --- a/arch/arc/include/asm/setup.h +++ b/arch/arc/include/asm/setup.h @@ -36,7 +36,6 @@ long __init arc_get_mem_sz(void); =20 extern void arc_mmu_init(void); extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len); -extern void read_decode_mmu_bcr(void); =20 extern void arc_cache_init(void); extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len); diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 41f07b3e594e..094461540f8a 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -186,7 +186,6 @@ static void read_arc_build_cfg_regs(void) /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ read_decode_ccm_bcr(cpu); =20 - read_decode_mmu_bcr(); read_decode_cache_bcr(); =20 if (is_isa_arcompact()) { @@ -256,7 +255,7 @@ static void read_arc_build_cfg_regs(void) cpu->isa.be =3D IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); =20 /* there's no direct way to distinguish 750 vs. 770 */ - if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3)) + if (unlikely(cpu->core.family < 0x34)) cpu->name =3D "ARC750"; } else { cpu->isa =3D isa; @@ -463,6 +462,7 @@ void setup_processor(void) arc_init_IRQ(); =20 pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); + pr_info("%s", arc_mmu_mumbojumbo(cpu_id, str, sizeof(str))); =20 arc_mmu_init(); arc_cache_init(); diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 2a3105a682c3..17e32c707367 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -18,7 +18,9 @@ /* A copy of the ASID from the PID reg is kept in asid_cache */ DEFINE_PER_CPU(unsigned int, asid_cache) =3D MM_CTXT_FIRST_CYCLE; =20 -static int __read_mostly pae_exists; +static struct cpuinfo_arc_mmu { + unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; +} mmuinfo; =20 /* * Utility Routine to erase a J-TLB entry @@ -131,7 +133,7 @@ static void tlb_entry_insert(unsigned int pd0, phys_add= r_t pd1) =20 noinline void local_flush_tlb_all(void) { - struct cpuinfo_arc_mmu *mmu =3D &cpuinfo_arc700[smp_processor_id()].mmu; + struct cpuinfo_arc_mmu *mmu =3D &mmuinfo; unsigned long flags; unsigned int entry; int num_tlb =3D mmu->sets * mmu->ways; @@ -560,89 +562,63 @@ void local_flush_pmd_tlb_range(struct vm_area_struct = *vma, unsigned long start, * the cpuinfo structure for later use. * No Validation is done here, simply read/convert the BCRs */ -void read_decode_mmu_bcr(void) +char *arc_mmu_mumbojumbo(int c, char *buf, int len) { - struct cpuinfo_arc_mmu *mmu =3D &cpuinfo_arc700[smp_processor_id()].mmu; - unsigned int tmp; - struct bcr_mmu_3 { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4, - u_itlb:4, u_dtlb:4; -#else - unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4, - ways:4, ver:8; -#endif - } *mmu3; - - struct bcr_mmu_4 { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, - n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; -#else - /* DTLB ITLB JES JE JA */ - unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, - pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; -#endif - } *mmu4; + struct cpuinfo_arc_mmu *mmu =3D &mmuinfo; + unsigned int bcr, u_dtlb, u_itlb, sasid; + struct bcr_mmu_3 *mmu3; + struct bcr_mmu_4 *mmu4; + char super_pg[64] =3D ""; + int n =3D 0; =20 - tmp =3D read_aux_reg(ARC_REG_MMU_BCR); - mmu->ver =3D (tmp >> 24); + bcr =3D read_aux_reg(ARC_REG_MMU_BCR); + mmu->ver =3D (bcr >> 24); =20 if (is_isa_arcompact() && mmu->ver =3D=3D 3) { - mmu3 =3D (struct bcr_mmu_3 *)&tmp; + mmu3 =3D (struct bcr_mmu_3 *)&bcr; mmu->pg_sz_k =3D 1 << (mmu3->pg_sz - 1); mmu->sets =3D 1 << mmu3->sets; mmu->ways =3D 1 << mmu3->ways; - mmu->u_dtlb =3D mmu3->u_dtlb; - mmu->u_itlb =3D mmu3->u_itlb; - mmu->sasid =3D mmu3->sasid; + u_dtlb =3D mmu3->u_dtlb; + u_itlb =3D mmu3->u_itlb; + sasid =3D mmu3->sasid; } else { - mmu4 =3D (struct bcr_mmu_4 *)&tmp; + mmu4 =3D (struct bcr_mmu_4 *)&bcr; mmu->pg_sz_k =3D 1 << (mmu4->sz0 - 1); mmu->s_pg_sz_m =3D 1 << (mmu4->sz1 - 11); mmu->sets =3D 64 << mmu4->n_entry; mmu->ways =3D mmu4->n_ways * 2; - mmu->u_dtlb =3D mmu4->u_dtlb * 4; - mmu->u_itlb =3D mmu4->u_itlb * 4; - mmu->sasid =3D mmu4->sasid; - pae_exists =3D mmu->pae =3D mmu4->pae; + u_dtlb =3D mmu4->u_dtlb * 4; + u_itlb =3D mmu4->u_itlb * 4; + sasid =3D mmu4->sasid; + mmu->pae =3D mmu4->pae; } -} =20 -char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len) -{ - int n =3D 0; - struct cpuinfo_arc_mmu *p_mmu =3D &cpuinfo_arc700[cpu_id].mmu; - char super_pg[64] =3D ""; - - if (p_mmu->s_pg_sz_m) - scnprintf(super_pg, 64, "%dM Super Page %s", - p_mmu->s_pg_sz_m, - IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE)); + if (mmu->s_pg_sz_m) + scnprintf(super_pg, 64, "/%dM%s", + mmu->s_pg_sz_m, + IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE) ? " (THP enabled)":""); =20 n +=3D scnprintf(buf + n, len - n, - "MMU [v%x]\t: %dk PAGE, %s, swalk %d lvl, JTLB %d (%dx%d), uDTLB %= d, uITLB %d%s%s\n", - p_mmu->ver, p_mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS, - p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways, - p_mmu->u_dtlb, p_mmu->u_itlb, - IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40)); + "MMU [v%x]\t: %dk%s, swalk %d lvl, JTLB %dx%d, uDTLB %d, uITLB %d%= s%s\n", + mmu->ver, mmu->pg_sz_k, super_pg, CONFIG_PGTABLE_LEVELS, + mmu->sets, mmu->ways, + u_dtlb, u_itlb, + IS_AVAIL2(mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40)); =20 return buf; } =20 int pae40_exist_but_not_enab(void) { - return pae_exists && !is_pae40_enabled(); + return mmuinfo.pae && !is_pae40_enabled(); } =20 void arc_mmu_init(void) { - struct cpuinfo_arc_mmu *mmu =3D &cpuinfo_arc700[smp_processor_id()].mmu; - char str[256]; + struct cpuinfo_arc_mmu *mmu =3D &mmuinfo; int compat =3D 0; =20 - pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str))); - /* * Can't be done in processor.h due to header include dependencies */ @@ -719,7 +695,7 @@ volatile int dup_pd_silent; /* Be silent abt it or comp= lain (default) */ void do_tlb_overlap_fault(unsigned long cause, unsigned long address, struct pt_regs *regs) { - struct cpuinfo_arc_mmu *mmu =3D &cpuinfo_arc700[smp_processor_id()].mmu; + struct cpuinfo_arc_mmu *mmu =3D &mmuinfo; unsigned long flags; int set, n_ways =3D mmu->ways; =20 --=20 2.34.1