From nobody Thu Dec 18 18:24:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A780C04A94 for ; Mon, 14 Aug 2023 14:07:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231569AbjHNOG7 (ORCPT ); Mon, 14 Aug 2023 10:06:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230347AbjHNOGy (ORCPT ); Mon, 14 Aug 2023 10:06:54 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2743610D0; Mon, 14 Aug 2023 07:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692022014; x=1723558014; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JvC5ybwWd2s2QwBOcdZZsCQYPiTGu+dFmBHjemTdC1g=; b=M6FHPeC9e3gvWlpNInga+dGn/SCDGRA8YeHaqY+hTjVYbECB5XcJJXp1 5Y7Ie+a7KNCV8CZDax8dQ46mvSD6cZn4xekT2SiLpcDfM15iKVsvmWtor 80nPgS//Tlx2hMYrR4eJ2CqDfECyuxe82Mz2ABlSYy+sVkNWwZshKjDPH oqp02rmIcCB28FswO6I68FnerjiTq8J0DBQOldqQpczTaVBCBzdZZ3TqG d9V39pZoQKL+4qSTBRaxo/2jlEucYYfeLOL7Sa6A4nOL1k20ldRr50TYM IPDWrydKhgPGZ9u6MfrQarWi89kyvrVgcx+wvTJSnpCCafPpJDsSFUp3s g==; X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="438377203" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="438377203" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 07:06:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="683317911" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="683317911" Received: from pglc00067.png.intel.com ([10.221.207.87]) by orsmga003.jf.intel.com with ESMTP; 14 Aug 2023 07:06:48 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next v3 1/2] dt-bindings: net: snps,dwmac: Tx queues with coe Date: Mon, 14 Aug 2023 22:06:36 +0800 Message-Id: <20230814140637.27629-2-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20230814140637.27629-1-rohan.g.thomas@intel.com> References: <20230814140637.27629-1-rohan.g.thomas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt-bindings for the number of tx queues with coe support. Some dwmac IPs support tx queues only for a few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas Acked-by: Conor Dooley --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index ddf9522a5dc2..0c6431c10cf9 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -313,6 +313,9 @@ properties: snps,tx-queues-to-use: $ref: /schemas/types.yaml#/definitions/uint32 description: number of TX queues to be used in the driver + snps,tx-queues-with-coe: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of TX queues that support TX checksum offloadi= ng snps,tx-sched-wrr: type: boolean description: Weighted Round Robin --=20 2.19.0 From nobody Thu Dec 18 18:24:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C308C41513 for ; Mon, 14 Aug 2023 14:08:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231643AbjHNOHa (ORCPT ); Mon, 14 Aug 2023 10:07:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231166AbjHNOHI (ORCPT ); Mon, 14 Aug 2023 10:07:08 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85479E3; Mon, 14 Aug 2023 07:07:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692022027; x=1723558027; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=St4U/wuWh0OAhYdmVt6mYPM5qL5I3ElRVCMLo6R0/uk=; b=e2GY0SJ0regnvK7WBn6XKdm5hbr/7bom1ee8ncahJcFiKE2HAMrkPVRn jeIip4l/ew8MTU2AOjc6a1HV9nLR4JD+jazbGg5QnnUsUJh2ScliPGIUo 1Vgq/Vp2IIx3LzoOmoloFziPXvE7+A06fiXKkOYyY7axoR/OYhBIwu9z0 QKOg9RNqjr2m8auWtGTsI/fXZ+suO387TUeFsSyvXFQ4psUbibE1LdxTo SBgtAcpSvzJ1FbXPSRI1Srco9i13xB7Kj7MkbE3SVnyqyVh1xiGGgrO2q Aghkxxiw6JMz9xic4HWQRhrle0wRvjyWu+PiQlR5IpOhZloVcZJQPgL+9 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="438377265" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="438377265" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2023 07:07:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10802"; a="683317948" X-IronPort-AV: E=Sophos;i="6.01,172,1684825200"; d="scan'208";a="683317948" Received: from pglc00067.png.intel.com ([10.221.207.87]) by orsmga003.jf.intel.com with ESMTP; 14 Aug 2023 07:06:57 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next v3 2/2] net: stmmac: Tx coe sw fallback Date: Mon, 14 Aug 2023 22:06:37 +0800 Message-Id: <20230814140637.27629-3-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20230814140637.27629-1-rohan.g.thomas@intel.com> References: <20230814140637.27629-1-rohan.g.thomas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add sw fallback of tx checksum calculation for those tx queues that don't support tx checksum offloading. Because, some DWMAC IPs support tx checksum offloading only for a few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 19 +++++++++++++++++++ .../ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++++ include/linux/stmmac.h | 1 + 4 files changed, 26 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/eth= ernet/stmicro/stmmac/stmmac.h index 3401e888a9f6..f526bcaaaf64 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -219,6 +219,8 @@ struct stmmac_priv { int hwts_tx_en; bool tx_path_in_lpi_mode; bool tso; + bool tx_q_coe_lmt; + u32 tx_q_with_coe; int sph; int sph_cap; u32 sarc_type; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index 733b5e900817..555d40bcc089 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4409,6 +4409,17 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, = struct net_device *dev) WARN_ON(tx_q->tx_skbuff[first_entry]); =20 csum_insertion =3D (skb->ip_summed =3D=3D CHECKSUM_PARTIAL); + /* Some DWMAC IPs support tx coe only for a few initial tx queues, + * starting from tx queue 0. So checksum offloading for those queues + * that don't support tx coe needs to fallback to software checksum + * calculation. + */ + if (csum_insertion && priv->tx_q_coe_lmt && + queue >=3D priv->tx_q_with_coe) { + if (unlikely(skb_checksum_help(skb))) + goto dma_map_err; + csum_insertion =3D !csum_insertion; + } =20 if (likely(priv->extend_desc)) desc =3D (struct dma_desc *)(tx_q->dma_etx + entry); @@ -7401,6 +7412,14 @@ int stmmac_dvr_probe(struct device *device, dev_info(priv->device, "SPH feature enabled\n"); } =20 + if (priv->plat->tx_coe && + priv->plat->tx_queues_with_coe < priv->plat->tx_queues_to_use) { + priv->tx_q_coe_lmt =3D true; + priv->tx_q_with_coe =3D priv->plat->tx_queues_with_coe; + dev_info(priv->device, "TX COE limited to %u tx queues\n", + priv->tx_q_with_coe); + } + /* Ideally our host DMA address width is the same as for the * device. However, it may differ and then we have to use our * host DMA width for allocation and the device DMA width for diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/driver= s/net/ethernet/stmicro/stmmac/stmmac_platform.c index be8e79c7aa34..0138b7c9c7ab 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -225,6 +225,10 @@ static int stmmac_mtl_setup(struct platform_device *pd= ev, &plat->tx_queues_to_use)) plat->tx_queues_to_use =3D 1; =20 + if (of_property_read_u32(tx_node, "snps,tx-queues-with-coe", + &plat->tx_queues_with_coe)) + plat->tx_queues_with_coe =3D plat->tx_queues_to_use; + if (of_property_read_bool(tx_node, "snps,tx-sched-wrr")) plat->tx_sched_algorithm =3D MTL_TX_ALGORITHM_WRR; else if (of_property_read_bool(tx_node, "snps,tx-sched-wfq")) diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 784277d666eb..cb508164eaea 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -252,6 +252,7 @@ struct plat_stmmacenet_data { u32 host_dma_width; u32 rx_queues_to_use; u32 tx_queues_to_use; + u32 tx_queues_with_coe; u8 rx_sched_algorithm; u8 tx_sched_algorithm; struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; --=20 2.19.0