From nobody Thu Sep 11 12:46:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4695C001DB for ; Mon, 14 Aug 2023 08:56:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235168AbjHNI4N (ORCPT ); Mon, 14 Aug 2023 04:56:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235220AbjHNIy3 (ORCPT ); Mon, 14 Aug 2023 04:54:29 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05FC11707 for ; Mon, 14 Aug 2023 01:54:23 -0700 (PDT) Message-ID: <20230814085113.824492521@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003261; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JiFKuPBKlN24KG+PjTPN55A/Pkj3ndmSBHCiS+xUuSU=; b=xav5fB4zqAEMosg01b1Qggjktak3dpXA1vDlL09AvNnekos3wpSlLgJb+xePdlMKU1xs3X FdpkZet4BwIrYs9MGhSe0ZVYCbKM5rtoI9VOc/dH5QawP1V8XXsvAiKvzKwFVfW4hUwmwk imcNv1QyuW4/p2+9t5R/GOu0brcExg0v5x0hpixO0JUKmJ1DrDbbGZhn2JLWwTjN6NyKNr a6/SC0XD+7csnQlR3QIqLbNVm26qyvc0b4tuuH5xlG3K4jIsPVvZUep9kQF3RXRGYgRuZ4 ed/8stKqqlHl3e/6s8qUFhN0ROq+Hgt4QpjbEF06FjtNnxK5ZEOJImhSX0AwBw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003261; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JiFKuPBKlN24KG+PjTPN55A/Pkj3ndmSBHCiS+xUuSU=; b=SNrQaEHqgH7tnoytfQale5M4s/WoAeR/PGNcUM1DuoQo1+2HmKmFf2+g+3AF/hXuQ5nVnO +E4KepEejRbVe9AQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 30/41] x86/cpu/amd: Provide a separate accessor for Node ID References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:21 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD (ab)uses topology_die_id() to store the Node ID information and topology_max_dies_per_pkg to store the number of nodes per package. This collides with the proper processor die level enumeration which is coming on AMD with CPUID 8000_0026, unless there is a correlation between the two. There is zero documentation about that. So provide new storage and new accessors which for now still access die_id and topology_max_dies_per_pkg. Will be mopped up after AMD and HYGON are converted over. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley --- arch/x86/events/amd/core.c | 2 +- arch/x86/include/asm/processor.h | 3 +++ arch/x86/include/asm/topology.h | 8 ++++++++ arch/x86/kernel/amd_nb.c | 4 ++-- arch/x86/kernel/cpu/cacheinfo.c | 2 +- arch/x86/kernel/cpu/mce/amd.c | 4 ++-- arch/x86/kernel/cpu/mce/inject.c | 4 ++-- drivers/edac/amd64_edac.c | 4 ++-- drivers/edac/mce_amd.c | 4 ++-- 9 files changed, 23 insertions(+), 12 deletions(-) --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -574,7 +574,7 @@ static void amd_pmu_cpu_starting(int cpu if (!x86_pmu.amd_nb_constraints) return; =20 - nb_id =3D topology_die_id(cpu); + nb_id =3D topology_amd_node_id(cpu); WARN_ON_ONCE(nb_id =3D=3D BAD_APICID); =20 for_each_online_cpu(i) { --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -99,6 +99,9 @@ struct cpuinfo_topology { u32 logical_pkg_id; u32 logical_die_id; =20 + // AMD Node ID and Nodes per Package info + u32 amd_node_id; + // Cache level topology IDs u32 llc_id; u32 l2c_id; --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -131,6 +131,8 @@ extern const struct cpumask *cpu_cluster #define topology_core_id(cpu) (cpu_data(cpu).topo.core_id) #define topology_ppin(cpu) (cpu_data(cpu).ppin) =20 +#define topology_amd_node_id(cpu) (cpu_data(cpu).topo.die_id) + extern unsigned int __max_die_per_package; =20 #ifdef CONFIG_SMP @@ -160,6 +162,11 @@ int topology_update_die_map(unsigned int int topology_phys_to_logical_pkg(unsigned int pkg); bool topology_smt_supported(void); =20 +static inline unsigned int topology_amd_nodes_per_pkg(void) +{ + return __max_die_per_package; +} + extern struct cpumask __cpu_primary_thread_mask; #define cpu_primary_thread_mask ((const struct cpumask *)&__cpu_primary_th= read_mask) =20 @@ -182,6 +189,7 @@ static inline int topology_max_die_per_p static inline int topology_max_smt_threads(void) { return 1; } static inline bool topology_is_primary_thread(unsigned int cpu) { return t= rue; } static inline bool topology_smt_supported(void) { return false; } +static inline unsigned int topology_amd_nodes_per_pkg(void) { return 0; }; #endif /* !CONFIG_SMP */ =20 static inline void arch_fix_phys_package_id(int num, u32 slot) --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -370,7 +370,7 @@ struct resource *amd_get_mmconfig_range( =20 int amd_get_subcaches(int cpu) { - struct pci_dev *link =3D node_to_amd_nb(topology_die_id(cpu))->link; + struct pci_dev *link =3D node_to_amd_nb(topology_amd_node_id(cpu))->link; unsigned int mask; =20 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) @@ -384,7 +384,7 @@ int amd_get_subcaches(int cpu) int amd_set_subcaches(int cpu, unsigned long mask) { static unsigned int reset, ban; - struct amd_northbridge *nb =3D node_to_amd_nb(topology_die_id(cpu)); + struct amd_northbridge *nb =3D node_to_amd_nb(topology_amd_node_id(cpu)); unsigned int reg; int cuid; =20 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -595,7 +595,7 @@ static void amd_init_l3_cache(struct _cp if (index < 3) return; =20 - node =3D topology_die_id(smp_processor_id()); + node =3D topology_amd_node_id(smp_processor_id()); this_leaf->nb =3D node_to_amd_nb(node); if (this_leaf->nb && !this_leaf->nb->l3_cache.indices) amd_calc_l3_indices(this_leaf->nb); --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -1181,7 +1181,7 @@ static int threshold_create_bank(struct return -ENODEV; =20 if (is_shared_bank(bank)) { - nb =3D node_to_amd_nb(topology_die_id(cpu)); + nb =3D node_to_amd_nb(topology_amd_node_id(cpu)); =20 /* threshold descriptor already initialized on this node? */ if (nb && nb->bank4) { @@ -1285,7 +1285,7 @@ static void threshold_remove_bank(struct * The last CPU on this node using the shared bank is going * away, remove that bank now. */ - nb =3D node_to_amd_nb(topology_die_id(smp_processor_id())); + nb =3D node_to_amd_nb(topology_amd_node_id(smp_processor_id())); nb->bank4 =3D NULL; } =20 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -543,8 +543,8 @@ static void do_inject(void) if (boot_cpu_has(X86_FEATURE_AMD_DCM) && b =3D=3D 4 && boot_cpu_data.x86 < 0x17) { - toggle_nb_mca_mst_cpu(topology_die_id(cpu)); - cpu =3D get_nbc_for_node(topology_die_id(cpu)); + toggle_nb_mca_mst_cpu(topology_amd_node_id(cpu)); + cpu =3D get_nbc_for_node(topology_amd_node_id(cpu)); } =20 cpus_read_lock(); --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1907,7 +1907,7 @@ static void dct_determine_memory_type(st /* On F10h and later ErrAddr is MC4_ADDR[47:1] */ static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) { - u16 mce_nid =3D topology_die_id(m->extcpu); + u16 mce_nid =3D topology_amd_node_id(m->extcpu); struct mem_ctl_info *mci; u8 start_bit =3D 1; u8 end_bit =3D 47; @@ -3438,7 +3438,7 @@ static void get_cpus_on_this_dct_cpumask int cpu; =20 for_each_online_cpu(cpu) - if (topology_die_id(cpu) =3D=3D nid) + if (topology_amd_node_id(cpu) =3D=3D nid) cpumask_set_cpu(cpu, mask); } =20 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1060,7 +1060,7 @@ static void decode_mc3_mce(struct mce *m static void decode_mc4_mce(struct mce *m) { unsigned int fam =3D x86_family(m->cpuid); - int node_id =3D topology_die_id(m->extcpu); + int node_id =3D topology_amd_node_id(m->extcpu); u16 ec =3D EC(m->status); u8 xec =3D XEC(m->status, 0x1f); u8 offset =3D 0; @@ -1188,7 +1188,7 @@ static void decode_smca_error(struct mce =20 if ((bank_type =3D=3D SMCA_UMC || bank_type =3D=3D SMCA_UMC_V2) && xec =3D=3D 0 && decode_dram_ecc) - decode_dram_ecc(topology_die_id(m->extcpu), m); + decode_dram_ecc(topology_amd_node_id(m->extcpu), m); } =20 static inline void amd_decode_err_code(u16 ec)