From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0046C001B0 for ; Mon, 14 Aug 2023 08:54:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233951AbjHNIxk (ORCPT ); Mon, 14 Aug 2023 04:53:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234362AbjHNIxi (ORCPT ); Mon, 14 Aug 2023 04:53:38 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6132E10C; Mon, 14 Aug 2023 01:53:37 -0700 (PDT) Message-ID: <20230814085112.089607918@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003216; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Y9F9yeUeXRQvv+8dtwJvn71MCeSGQXeJdooQjtDdUX4=; b=2AtO09Ke4+/nJKkcI0sgENvQf5F3G5miUPawzn/yBKF1usSUeX/9HNxrs0fT4wjG6GzMC2 88T8A1mecbgdFIx6RE4NAd63+lSNjO5ETjDogddz6pDkKtNjaElv/yqD0L3gCg0f8b7eXg pFlozKVgV/3zRpwzOCZmxhkhur6QHq59D2A/zW01OGqQKy/4w3el7qSEnV8fwPEtqOjIH9 u5/1ZNHIPI20cWNDBTWV7ko+ZKzkK/26D9f1F8XDCH5dpuiKLuumGal9v9CxugOuJCTNQd 5EoUHzHdJvi+9C9PGYCYsFUcPhyJpAeB7Zf4P8m5EhBpp0t6/RKxEiPRySJXzg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003216; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Y9F9yeUeXRQvv+8dtwJvn71MCeSGQXeJdooQjtDdUX4=; b=50DmVM3PmmqCp5//BMBetP3zy9RVpPF/qLqA4C19BsIfm0xgcn6HZEoiqjj8SlPHsI+5Zv VKE8dzw5OjnPpRBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Subject: [patch V4 01/41] x86/cpu/hygon: Fix the CPU topology evaluation for real References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:35 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Pu Wen Hygon updated processors have CPUID leaf 0xB correctly populated and don't need the fixed package ID shift workaround. The fixup is also incorrect when running in a guest. Fixes: e0ceeae708ce ("x86/CPU/hygon: Fix phys_proc_id calculation logic for= multi-die processors") Signed-off-by: Pu Wen Signed-off-by: Thomas Gleixner Cc: Link: https://lore.kernel.org/r/tencent_594804A808BD93A4EBF50A994F228E3A7F0= 7@qq.com Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/kernel/cpu/hygon.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -87,8 +87,12 @@ static void hygon_get_topology(struct cp if (!err) c->x86_coreid_bits =3D get_count_order(c->x86_max_cores); =20 - /* Socket ID is ApicId[6] for these processors. */ - c->phys_proc_id =3D c->apicid >> APICID_SOCKET_ID_BIT; + /* + * Socket ID is ApicId[6] for the processors with model <=3D 0x3 + * when running on host. + */ + if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && c->x86_model <=3D 0x3) + c->phys_proc_id =3D c->apicid >> APICID_SOCKET_ID_BIT; =20 cacheinfo_hygon_init_llc_id(c, cpu); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5893C04A94 for ; Mon, 14 Aug 2023 08:54:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232573AbjHNIyQ (ORCPT ); Mon, 14 Aug 2023 04:54:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233903AbjHNIxk (ORCPT ); Mon, 14 Aug 2023 04:53:40 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02B9510B for ; Mon, 14 Aug 2023 01:53:39 -0700 (PDT) Message-ID: <20230814085112.149440843@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003217; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6UGrI6Ud/CP8ZpSU60c+UMBZEwkl8meNMyIq7OTHrBs=; b=yTHN50q6gw0TeW2JhLr5EqrwCsNqHtUNcjNCaChaRFf3868X+WpFzyrj1ntNrkbMdrM1Sx fCAI60MXnkNEZDVFIY2cHwlVrEtfK0WsBjKG3u5xEpNTnXT8pa0AxwpHguEjhKxl4iE90E MuJ/TYLaY7CJa47VAI/9yX5MmPG9oLoxfQ/W4l4PBhPuVo1i6JwX7MN61ywcs8pDq5BNT3 rvHC3oJhqYp5/x0esPaG5Zz/UZZgMB0FrFAEKEqfrVD6bboaKAWyuEGBLe6bkzqMGoN3nk sJBJ/pjAMdR800oeL68LJ5T3jnoHLHvMrTH/DpxypgJFvotRUWtFw+cTveWV8A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003217; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6UGrI6Ud/CP8ZpSU60c+UMBZEwkl8meNMyIq7OTHrBs=; b=CSra9bkYm4iOU76EFCNZ2F5vFF1p77f0ata+h48tURjAYnnZbLVh0imDi0EQlK4DTIn6ke nqDkgp2R0Roda+Dg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 02/41] cpu/SMT: Make SMT control more robust against enumeration failures References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:37 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SMT control mechanism got added as speculation attack vector mitigation. The implemented logic relies on the primary thread mask to be set up properly. This turns out to be an issue with XEN/PV guests because their CPU hotplug mechanics do not enumerate APICs and therefore the mask is never correctly populated. This went unnoticed so far because by chance XEN/PV ends up with smp_num_siblings =3D=3D 2. So smt_hotplug_control stays at its default value CPU_SMT_ENABLED and the primary thread mask is never evaluated in the context of CPU hotplug. This stopped "working" with the upcoming overhaul of the topology evaluation which legitimately provides a fake topology for XEN/PV. That sets smp_num_siblings to 1, which causes the core CPU hot-plug core to refuse to bring up the APs. This happens because smt_hotplug_control is set to CPU_SMT_NOT_SUPPORTED which causes cpu_smt_allowed() to evaluate the unpopulated primary thread mask with the conclusion that all non-boot CPUs are not valid to be plugged. Make cpu_smt_allowed() more robust and take CPU_SMT_NOT_SUPPORTED and CPU_SMT_NOT_IMPLEMENTED into account. Rename it to cpu_bootable() while at it as that makes it more clear what the function is about. The primary mask issue on x86 XEN/PV needs to be addressed separately as there are users outside of the CPU hotplug code too. Fixes: 05736e4ac13c ("cpu/hotplug: Provide knobs to control SMT") Reported-by: Juergen Gross Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V2: Rename cpu_smt_allowed() - Borislav --- kernel/cpu.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -625,11 +625,17 @@ static int __init smt_cmdline_disable(ch } early_param("nosmt", smt_cmdline_disable); =20 -static inline bool cpu_smt_allowed(unsigned int cpu) +static inline bool cpu_bootable(unsigned int cpu) { if (cpu_smt_control =3D=3D CPU_SMT_ENABLED) return true; =20 + if (cpu_smt_control =3D=3D CPU_SMT_NOT_SUPPORTED) + return true; + + if (cpu_smt_control =3D=3D CPU_SMT_NOT_IMPLEMENTED) + return true; + if (topology_is_primary_thread(cpu)) return true; =20 @@ -660,7 +666,7 @@ static inline const struct cpumask *cpuh return cpu_primary_thread_mask; } #else -static inline bool cpu_smt_allowed(unsigned int cpu) { return true; } +static inline bool cpu_bootable(unsigned int cpu) { return true; } static inline bool cpuhp_smt_aware(void) { return false; } static inline const struct cpumask *cpuhp_get_primary_thread_mask(void) { @@ -768,10 +774,10 @@ static int bringup_wait_for_ap_online(un * SMT soft disabling on X86 requires to bring the CPU out of the * BIOS 'wait for SIPI' state in order to set the CR4.MCE bit. The * CPU marked itself as booted_once in notify_cpu_starting() so the - * cpu_smt_allowed() check will now return false if this is not the + * cpu_bootable() check will now return false if this is not the * primary sibling. */ - if (!cpu_smt_allowed(cpu)) + if (!cpu_bootable(cpu)) return -ECANCELED; return 0; } @@ -1699,7 +1705,7 @@ static int cpu_up(unsigned int cpu, enum err =3D -EBUSY; goto out; } - if (!cpu_smt_allowed(cpu)) { + if (!cpu_bootable(cpu)) { err =3D -EPERM; goto out; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01242C04FDF for ; Mon, 14 Aug 2023 08:54:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235061AbjHNIyS (ORCPT ); Mon, 14 Aug 2023 04:54:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234152AbjHNIxl (ORCPT ); Mon, 14 Aug 2023 04:53:41 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D6F791 for ; Mon, 14 Aug 2023 01:53:40 -0700 (PDT) Message-ID: <20230814085112.210011520@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003219; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nD+LWCUPb/nY7KWkB0c0EJXdbBh6K+dG9PjIdqnGrPA=; b=fwo2FxuOhXijXLvaxBnbfpYmO0XxJ7IcIxOP4BSUjxKhdOLTmT7Hvbr83tk+xjmxpvbvja AM9fLIyk2jEQm83V1S8l3R+HnAp0S44GSy96xPgTI3vtiKC+aw2qo0JRXzJAM8wvnzfJOS A8twcLryRivqwqhGmM3ylvhb6WEDcC2aAXXQb9FbuW63Zu18J4Czv0u/0qAXK6iJc/78jr KlbJl69SPZXkUmmlxGjDu50K6p6wY5EqFVHaqAL0aLzWH9fALWF65uvzPb8KLP0hTbdtvf S6mqW9w6iDTjaqrCNHTfSoDpGliO8KTKQ+vterldyDyF7pzUMSh40yf5ye7cMg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003219; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nD+LWCUPb/nY7KWkB0c0EJXdbBh6K+dG9PjIdqnGrPA=; b=t8JymdvPNdMVI2B8H+PMItAhyODMNSdTb+Djmm04FJALZMrOw7aker1SCA2kr2MwYXYm6h MBXX/2urs0a6GbDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 03/41] x86/apic: Fake primary thread mask for XEN/PV References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:38 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SMT control mechanism got added as speculation attack vector mitigation. The implemented logic relies on the primary thread mask to be set up properly. This turns out to be an issue with XEN/PV guests because their CPU hotplug mechanics do not enumerate APICs and therefore the mask is never correctly populated. This went unnoticed so far because by chance XEN/PV ends up with smp_num_siblings =3D=3D 2. So cpu_smt_control stays at its default value CPU_SMT_ENABLED and the primary thread mask is never evaluated in the context of CPU hotplug. This stopped "working" with the upcoming overhaul of the topology evaluation which legitimately provides a fake topology for XEN/PV. That sets smp_num_siblings to 1, which causes the core CPU hot-plug core to refuse to bring up the APs. This happens because cpu_smt_control is set to CPU_SMT_NOT_SUPPORTED which causes cpu_bootable() to evaluate the unpopulated primary thread mask with the conclusion that all non-boot CPUs are not valid to be plugged. The core code has already been made more robust against this kind of fail, but the primary thread mask really wants to be populated to avoid other issues all over the place. Just fake the mask by pretending that all XEN/PV vCPUs are primary threads, which is consistent because all of XEN/PVs topology is fake or non-existent. Fixes: 6a4d2657e048 ("x86/smp: Provide topology_is_primary_thread()") Fixes: f54d4434c281 ("x86/apic: Provide cpu_primary_thread mask") Reported-by: Juergen Gross Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V2: Fixup changelog - Borislav --- arch/x86/kernel/apic/apic.c | 11 +++++++++++ 1 file changed, 11 insertions(+) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -36,6 +36,8 @@ #include #include =20 +#include + #include #include #include @@ -2344,6 +2346,15 @@ static int __init smp_init_primary_threa { unsigned int cpu; =20 + /* + * XEN/PV provides either none or useless topology information. + * Pretend that all vCPUs are primary threads. + */ + if (xen_pv_domain()) { + cpumask_copy(&__cpu_primary_thread_mask, cpu_possible_mask); + return 0; + } + for (cpu =3D 0; cpu < nr_logical_cpuids; cpu++) cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); return 0; From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F460C04FE1 for ; Mon, 14 Aug 2023 08:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235119AbjHNIyV (ORCPT ); Mon, 14 Aug 2023 04:54:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234564AbjHNIxo (ORCPT ); Mon, 14 Aug 2023 04:53:44 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45F5E10C for ; Mon, 14 Aug 2023 01:53:42 -0700 (PDT) Message-ID: <20230814085112.269787744@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003220; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=W82tRZcvcFCwxRqnqnDeebqt3Rc8yM7ALtYKokTASAw=; b=e6d3p1pJ0d0ZANK4tUDdkc5h317CSRDohk4rOm3IQu5RUgwlojGGid10ELbXFjBgV40Ib3 edzO7T9WN/3c8skF+lDg2SpxKQvxJ6MHm/adxFgONGfxxfTJ5WyKR42Bm6ZgtVJtbwgdt7 rMApuW8I+E7rNH9QBQj2KTIBYhPMEJZubypMMIkAiZ4YrL7Q9ScmkrRS+F+bxy9+0/DDNX 8u3DwQ19kAmjnakrJ8jgYyTCJ9Dz8tFNxKaMuEH6ZR4a0mOFLrfAHCXDnTQWF4qFmsjAVY owaeH7hSviTNNjVXw2lSfKxZzDk6Nv87Y5b8abFXfcwBM4gyFR2K4U8vEV1e2Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003220; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=W82tRZcvcFCwxRqnqnDeebqt3Rc8yM7ALtYKokTASAw=; b=Gwo5rgJOgQLZbYmUtVWe30sWuIRp+1m8JLvULS5wPHnDwN0sC4/MYTPWXVz6MWh0X5KbiL nrMN4WlakWdwPuAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 04/41] x86/cpu: Encapsulate topology information in cpuinfo_x86 References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:40 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The topology related information is randomly scattered across cpuinfo_x86. Create a new structure cpuinfo_topo and move in a first step initial_apicid and apicid into it. Aside of being better readable this is in preparation for replacing the horribly fragile CPU topology evaluation code further down the road. Consolidate APIC ID fields to u32 as that represents the hardware type. No functional change. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/processor.h | 14 +++++++++----- arch/x86/kernel/cpu/amd.c | 10 +++++----- arch/x86/kernel/cpu/cacheinfo.c | 20 ++++++++++---------- arch/x86/kernel/cpu/common.c | 18 +++++++++--------- arch/x86/kernel/cpu/hygon.c | 12 ++++++------ arch/x86/kernel/cpu/mce/apei.c | 2 +- arch/x86/kernel/cpu/mce/core.c | 2 +- arch/x86/kernel/cpu/proc.c | 4 ++-- arch/x86/kernel/cpu/topology.c | 12 ++++++------ arch/x86/xen/apic.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- drivers/virt/acrn/hsm.c | 2 +- 12 files changed, 52 insertions(+), 48 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -74,11 +74,16 @@ extern u16 __read_mostly tlb_lld_4m[NR_I extern u16 __read_mostly tlb_lld_1g[NR_INFO]; =20 /* - * CPU type and hardware bug flags. Kept separately for each CPU. - * Members of this structure are referenced in head_32.S, so think twice - * before touching them. [mj] + * CPU type and hardware bug flags. Kept separately for each CPU. */ =20 +struct cpuinfo_topology { + // Real APIC ID read from the local APIC + u32 apicid; + // The initial APIC ID provided by CPUID + u32 initial_apicid; +}; + struct cpuinfo_x86 { __u8 x86; /* CPU family */ __u8 x86_vendor; /* CPU vendor */ @@ -111,6 +116,7 @@ struct cpuinfo_x86 { }; char x86_vendor_id[16]; char x86_model_id[64]; + struct cpuinfo_topology topo; /* in KB - valid for CPUS which support this call: */ unsigned int x86_cache_size; int x86_cache_alignment; /* In bytes */ @@ -124,8 +130,6 @@ struct cpuinfo_x86 { u64 ppin; /* cpuid returned max cores value: */ u16 x86_max_cores; - u16 apicid; - u16 initial_apicid; u16 x86_clflush_size; /* number of cores as seen by the OS: */ u16 booted_cores; --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -454,9 +454,9 @@ static void amd_detect_cmp(struct cpuinf =20 bits =3D c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ - c->cpu_core_id =3D c->initial_apicid & ((1 << bits)-1); + c->cpu_core_id =3D c->topo.initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ - c->phys_proc_id =3D c->initial_apicid >> bits; + c->phys_proc_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->phys_proc_id; } @@ -472,7 +472,7 @@ static void srat_detect_node(struct cpui #ifdef CONFIG_NUMA int cpu =3D smp_processor_id(); int node; - unsigned apicid =3D c->apicid; + unsigned apicid =3D c->topo.apicid; =20 node =3D numa_cpu_node(cpu); if (node =3D=3D NUMA_NO_NODE) @@ -506,7 +506,7 @@ static void srat_detect_node(struct cpui * through CPU mapping may alter the outcome, directly * access __apicid_to_node[]. */ - int ht_nodeid =3D c->initial_apicid; + int ht_nodeid =3D c->topo.initial_apicid; =20 if (__apicid_to_node[ht_nodeid] !=3D NUMA_NO_NODE) node =3D __apicid_to_node[ht_nodeid]; @@ -1042,7 +1042,7 @@ static void init_amd(struct cpuinfo_x86 set_cpu_cap(c, X86_FEATURE_FSRS); =20 /* get apicid instead of initial apic id from cpuid */ - c->apicid =3D read_apic_id(); + c->topo.apicid =3D read_apic_id(); =20 /* K6s reports MCEs but don't actually have all the MSRs */ if (c->x86 < 6) --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -678,7 +678,7 @@ void cacheinfo_amd_init_llc_id(struct cp * LLC is at the core complex level. * Core complex ID is ApicId[3] for these processors. */ - per_cpu(cpu_llc_id, cpu) =3D c->apicid >> 3; + per_cpu(cpu_llc_id, cpu) =3D c->topo.apicid >> 3; } else { /* * LLC ID is calculated from the number of threads sharing the @@ -694,7 +694,7 @@ void cacheinfo_amd_init_llc_id(struct cp if (num_sharing_cache) { int bits =3D get_count_order(num_sharing_cache); =20 - per_cpu(cpu_llc_id, cpu) =3D c->apicid >> bits; + per_cpu(cpu_llc_id, cpu) =3D c->topo.apicid >> bits; } } } @@ -712,7 +712,7 @@ void cacheinfo_hygon_init_llc_id(struct * LLC is at the core complex level. * Core complex ID is ApicId[3] for these processors. */ - per_cpu(cpu_llc_id, cpu) =3D c->apicid >> 3; + per_cpu(cpu_llc_id, cpu) =3D c->topo.apicid >> 3; } =20 void init_amd_cacheinfo(struct cpuinfo_x86 *c) @@ -776,13 +776,13 @@ void init_intel_cacheinfo(struct cpuinfo new_l2 =3D this_leaf.size/1024; num_threads_sharing =3D 1 + this_leaf.eax.split.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); - l2_id =3D c->apicid & ~((1 << index_msb) - 1); + l2_id =3D c->topo.apicid & ~((1 << index_msb) - 1); break; case 3: new_l3 =3D this_leaf.size/1024; num_threads_sharing =3D 1 + this_leaf.eax.split.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); - l3_id =3D c->apicid & ~((1 << index_msb) - 1); + l3_id =3D c->topo.apicid & ~((1 << index_msb) - 1); break; default: break; @@ -915,7 +915,7 @@ static int __cache_amd_cpumap_setup(unsi unsigned int apicid, nshared, first, last; =20 nshared =3D base->eax.split.num_threads_sharing + 1; - apicid =3D cpu_data(cpu).apicid; + apicid =3D cpu_data(cpu).topo.apicid; first =3D apicid - (apicid % nshared); last =3D first + nshared - 1; =20 @@ -924,14 +924,14 @@ static int __cache_amd_cpumap_setup(unsi if (!this_cpu_ci->info_list) continue; =20 - apicid =3D cpu_data(i).apicid; + apicid =3D cpu_data(i).topo.apicid; if ((apicid < first) || (apicid > last)) continue; =20 this_leaf =3D this_cpu_ci->info_list + index; =20 for_each_online_cpu(sibling) { - apicid =3D cpu_data(sibling).apicid; + apicid =3D cpu_data(sibling).topo.apicid; if ((apicid < first) || (apicid > last)) continue; cpumask_set_cpu(sibling, @@ -969,7 +969,7 @@ static void __cache_cpumap_setup(unsigne index_msb =3D get_count_order(num_threads_sharing); =20 for_each_online_cpu(i) - if (cpu_data(i).apicid >> index_msb =3D=3D c->apicid >> index_msb) { + if (cpu_data(i).topo.apicid >> index_msb =3D=3D c->topo.apicid >> index_= msb) { struct cpu_cacheinfo *sib_cpu_ci =3D get_cpu_cacheinfo(i); =20 if (i =3D=3D cpu || !sib_cpu_ci->info_list) @@ -1024,7 +1024,7 @@ static void get_cache_id(int cpu, struct =20 num_threads_sharing =3D 1 + id4_regs->eax.split.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); - id4_regs->id =3D c->apicid >> index_msb; + id4_regs->id =3D c->topo.apicid >> index_msb; } =20 int populate_cache_leaves(unsigned int cpu) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -899,7 +899,7 @@ void detect_ht(struct cpuinfo_x86 *c) return; =20 index_msb =3D get_count_order(smp_num_siblings); - c->phys_proc_id =3D apic->phys_pkg_id(c->initial_apicid, index_msb); + c->phys_proc_id =3D apic->phys_pkg_id(c->topo.initial_apicid, index_msb); =20 smp_num_siblings =3D smp_num_siblings / c->x86_max_cores; =20 @@ -907,7 +907,7 @@ void detect_ht(struct cpuinfo_x86 *c) =20 core_bits =3D get_count_order(c->x86_max_cores); =20 - c->cpu_core_id =3D apic->phys_pkg_id(c->initial_apicid, index_msb) & + c->cpu_core_id =3D apic->phys_pkg_id(c->topo.initial_apicid, index_msb) & ((1 << core_bits) - 1); #endif } @@ -1721,15 +1721,15 @@ static void generic_identify(struct cpui get_cpu_address_sizes(c); =20 if (c->cpuid_level >=3D 0x00000001) { - c->initial_apicid =3D (cpuid_ebx(1) >> 24) & 0xFF; + c->topo.initial_apicid =3D (cpuid_ebx(1) >> 24) & 0xFF; #ifdef CONFIG_X86_32 # ifdef CONFIG_SMP - c->apicid =3D apic->phys_pkg_id(c->initial_apicid, 0); + c->topo.apicid =3D apic->phys_pkg_id(c->topo.initial_apicid, 0); # else - c->apicid =3D c->initial_apicid; + c->topo.apicid =3D c->topo.initial_apicid; # endif #endif - c->phys_proc_id =3D c->initial_apicid; + c->phys_proc_id =3D c->topo.initial_apicid; } =20 get_model_name(c); /* Default name */ @@ -1763,9 +1763,9 @@ static void validate_apic_and_package_id =20 apicid =3D apic->cpu_present_to_apicid(cpu); =20 - if (apicid !=3D c->apicid) { + if (apicid !=3D c->topo.apicid) { pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", - cpu, apicid, c->initial_apicid); + cpu, apicid, c->topo.initial_apicid); } BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); @@ -1815,7 +1815,7 @@ static void identify_cpu(struct cpuinfo_ apply_forced_caps(c); =20 #ifdef CONFIG_X86_64 - c->apicid =3D apic->phys_pkg_id(c->initial_apicid, 0); + c->topo.apicid =3D apic->phys_pkg_id(c->topo.initial_apicid, 0); #endif =20 /* --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -92,7 +92,7 @@ static void hygon_get_topology(struct cp * when running on host. */ if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && c->x86_model <=3D 0x3) - c->phys_proc_id =3D c->apicid >> APICID_SOCKET_ID_BIT; + c->phys_proc_id =3D c->topo.apicid >> APICID_SOCKET_ID_BIT; =20 cacheinfo_hygon_init_llc_id(c, cpu); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { @@ -120,9 +120,9 @@ static void hygon_detect_cmp(struct cpui =20 bits =3D c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ - c->cpu_core_id =3D c->initial_apicid & ((1 << bits)-1); + c->cpu_core_id =3D c->topo.initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ - c->phys_proc_id =3D c->initial_apicid >> bits; + c->phys_proc_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->phys_proc_id; } @@ -132,7 +132,7 @@ static void srat_detect_node(struct cpui #ifdef CONFIG_NUMA int cpu =3D smp_processor_id(); int node; - unsigned int apicid =3D c->apicid; + unsigned int apicid =3D c->topo.apicid; =20 node =3D numa_cpu_node(cpu); if (node =3D=3D NUMA_NO_NODE) @@ -165,7 +165,7 @@ static void srat_detect_node(struct cpui * through CPU mapping may alter the outcome, directly * access __apicid_to_node[]. */ - int ht_nodeid =3D c->initial_apicid; + int ht_nodeid =3D c->topo.initial_apicid; =20 if (__apicid_to_node[ht_nodeid] !=3D NUMA_NO_NODE) node =3D __apicid_to_node[ht_nodeid]; @@ -305,7 +305,7 @@ static void init_hygon(struct cpuinfo_x8 set_cpu_cap(c, X86_FEATURE_REP_GOOD); =20 /* get apicid instead of initial apic id from cpuid */ - c->apicid =3D read_apic_id(); + c->topo.apicid =3D read_apic_id(); =20 /* * XXX someone from Hygon needs to confirm this DTRT --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -103,7 +103,7 @@ int apei_smca_report_x86_error(struct cp m.socketid =3D -1; =20 for_each_possible_cpu(cpu) { - if (cpu_data(cpu).initial_apicid =3D=3D lapic_id) { + if (cpu_data(cpu).topo.initial_apicid =3D=3D lapic_id) { m.extcpu =3D cpu; m.socketid =3D cpu_data(m.extcpu).phys_proc_id; break; --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -124,7 +124,7 @@ void mce_setup(struct mce *m) m->cpuvendor =3D boot_cpu_data.x86_vendor; m->cpuid =3D cpuid_eax(1); m->socketid =3D cpu_data(m->extcpu).phys_proc_id; - m->apicid =3D cpu_data(m->extcpu).initial_apicid; + m->apicid =3D cpu_data(m->extcpu).topo.initial_apicid; m->mcgcap =3D __rdmsr(MSR_IA32_MCG_CAP); m->ppin =3D cpu_data(m->extcpu).ppin; m->microcode =3D boot_cpu_data.microcode; --- a/arch/x86/kernel/cpu/proc.c +++ b/arch/x86/kernel/cpu/proc.c @@ -23,8 +23,8 @@ static void show_cpuinfo_core(struct seq cpumask_weight(topology_core_cpumask(cpu))); seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id); seq_printf(m, "cpu cores\t: %d\n", c->booted_cores); - seq_printf(m, "apicid\t\t: %d\n", c->apicid); - seq_printf(m, "initial apicid\t: %d\n", c->initial_apicid); + seq_printf(m, "apicid\t\t: %d\n", c->topo.apicid); + seq_printf(m, "initial apicid\t: %d\n", c->topo.initial_apicid); #endif } =20 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -78,7 +78,7 @@ int detect_extended_topology_early(struc /* * initial apic id, which also represents 32-bit extended x2apic id. */ - c->initial_apicid =3D edx; + c->topo.initial_apicid =3D edx; smp_num_siblings =3D max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)= ); #endif return 0; @@ -108,7 +108,7 @@ int detect_extended_topology(struct cpui * Populate HT related information from sub-leaf level 0. */ cpuid_count(leaf, SMT_LEVEL, &eax, &ebx, &ecx, &edx); - c->initial_apicid =3D edx; + c->topo.initial_apicid =3D edx; core_level_siblings =3D LEVEL_MAX_SIBLINGS(ebx); smp_num_siblings =3D max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)= ); core_plus_mask_width =3D ht_mask_width =3D BITS_SHIFT_NEXT_LEVEL(eax); @@ -146,20 +146,20 @@ int detect_extended_topology(struct cpui die_select_mask =3D (~(-1 << die_plus_mask_width)) >> core_plus_mask_width; =20 - c->cpu_core_id =3D apic->phys_pkg_id(c->initial_apicid, + c->cpu_core_id =3D apic->phys_pkg_id(c->topo.initial_apicid, ht_mask_width) & core_select_mask; =20 if (die_level_present) { - c->cpu_die_id =3D apic->phys_pkg_id(c->initial_apicid, + c->cpu_die_id =3D apic->phys_pkg_id(c->topo.initial_apicid, core_plus_mask_width) & die_select_mask; } =20 - c->phys_proc_id =3D apic->phys_pkg_id(c->initial_apicid, + c->phys_proc_id =3D apic->phys_pkg_id(c->topo.initial_apicid, pkg_mask_width); /* * Reinit the apicid, now that we have extended initial_apicid. */ - c->apicid =3D apic->phys_pkg_id(c->initial_apicid, 0); + c->topo.apicid =3D apic->phys_pkg_id(c->topo.initial_apicid, 0); =20 c->x86_max_cores =3D (core_level_siblings / smp_num_siblings); __max_die_per_package =3D (die_level_siblings / core_level_siblings); --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -118,7 +118,7 @@ static int xen_phys_pkg_id(int initial_a static int xen_cpu_present_to_apicid(int cpu) { if (cpu_present(cpu)) - return cpu_data(cpu).apicid; + return cpu_data(cpu).topo.apicid; else return BAD_APICID; } --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -2255,7 +2255,7 @@ static int kfd_cpumask_to_apic_id(const if (first_cpu_of_numa_node >=3D nr_cpu_ids) return -1; #ifdef CONFIG_X86_64 - return cpu_data(first_cpu_of_numa_node).apicid; + return cpu_data(first_cpu_of_numa_node).topo.apicid; #else return first_cpu_of_numa_node; #endif --- a/drivers/virt/acrn/hsm.c +++ b/drivers/virt/acrn/hsm.c @@ -447,7 +447,7 @@ static ssize_t remove_cpu_store(struct d if (cpu_online(cpu)) remove_cpu(cpu); =20 - lapicid =3D cpu_data(cpu).apicid; + lapicid =3D cpu_data(cpu).topo.apicid; dev_dbg(dev, "Try to remove cpu %lld with lapicid %lld\n", cpu, lapicid); ret =3D hcall_sos_remove_cpu(lapicid); if (ret < 0) { From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33437C05052 for ; Mon, 14 Aug 2023 08:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235191AbjHNIy1 (ORCPT ); Mon, 14 Aug 2023 04:54:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234576AbjHNIxp (ORCPT ); Mon, 14 Aug 2023 04:53:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABF9B91 for ; Mon, 14 Aug 2023 01:53:43 -0700 (PDT) Message-ID: <20230814085112.329006989@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003222; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=52X33TUdbJY3w3NYjSien2DrY3Pjfc5G/xtc8uHKfJ0=; b=YlVw/8t2zTLctmfjdGk/dvIL7ggX4OzF7SSbSrpWCWqknITm21UDpq2NIhie6ROQnVX57e zvc/iIzzwOGRPmM5cXV8wcN1Pwk1giiZwluFNVI397rquyhQvkxOFc7ZeBQpBhl/0Ud7uO hwPs4NcnjNS/JhX4tncEWvh3f+clUbSXaoFuPGzrjhaT8sGh73MFASiij0iZs5tZPluUkg EUpILDOG+Xa9oJRAWv287tCdNPskMXi2GdP6P/nvYOWCV99g/fkVGhea0rsqiFQupI6Sgz 9bBxnZpvbpM3TffurVpyCAyHav8UAObFYf/RNPiVQz/QWxUlTpmB1/OILf/GTA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003222; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=52X33TUdbJY3w3NYjSien2DrY3Pjfc5G/xtc8uHKfJ0=; b=dZIPJhRvvDbV/tXNsWnopDpKWyR2KbzIINFWy17fx35MlDn3HLs9VLYU/hkSebI7xtEWcK sTbJFPu2cDOPViBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 05/41] x86/cpu: Move phys_proc_id into topology info References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:41 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename it to pkg_id which is the terminology used in the kernel. No functional change. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- Documentation/arch/x86/topology.rst | 2 +- arch/x86/include/asm/processor.h | 5 +++-- arch/x86/include/asm/topology.h | 2 +- arch/x86/include/asm/x86_init.h | 2 +- arch/x86/kernel/apic/apic_numachip.c | 2 +- arch/x86/kernel/cpu/amd.c | 4 ++-- arch/x86/kernel/cpu/cacheinfo.c | 4 ++-- arch/x86/kernel/cpu/common.c | 6 +++--- arch/x86/kernel/cpu/hygon.c | 6 +++--- arch/x86/kernel/cpu/mce/apei.c | 2 +- arch/x86/kernel/cpu/mce/core.c | 2 +- arch/x86/kernel/cpu/proc.c | 2 +- arch/x86/kernel/cpu/topology.c | 3 +-- arch/x86/kernel/smpboot.c | 16 ++++++++-------- drivers/scsi/lpfc/lpfc_init.c | 6 +----- 15 files changed, 30 insertions(+), 34 deletions(-) --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -59,7 +59,7 @@ AMD nomenclature for package is 'Node'. =20 The physical ID of the die. This information is retrieved via CPUID. =20 - - cpuinfo_x86.phys_proc_id: + - cpuinfo_x86.topo.pkg_id: =20 The physical ID of the package. This information is retrieved via CPUID and deduced from the APIC IDs of the cores in the package. --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -82,6 +82,9 @@ struct cpuinfo_topology { u32 apicid; // The initial APIC ID provided by CPUID u32 initial_apicid; + + // Physical package ID + u32 pkg_id; }; =20 struct cpuinfo_x86 { @@ -133,8 +136,6 @@ struct cpuinfo_x86 { u16 x86_clflush_size; /* number of cores as seen by the OS: */ u16 booted_cores; - /* Physical processor id: */ - u16 phys_proc_id; /* Logical processor id: */ u16 logical_proc_id; /* Core id: */ --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -106,7 +106,7 @@ extern const struct cpumask *cpu_coregro extern const struct cpumask *cpu_clustergroup_mask(int cpu); =20 #define topology_logical_package_id(cpu) (cpu_data(cpu).logical_proc_id) -#define topology_physical_package_id(cpu) (cpu_data(cpu).phys_proc_id) +#define topology_physical_package_id(cpu) (cpu_data(cpu).topo.pkg_id) #define topology_logical_die_id(cpu) (cpu_data(cpu).logical_die_id) #define topology_die_id(cpu) (cpu_data(cpu).cpu_die_id) #define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id) --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -177,7 +177,7 @@ struct x86_init_ops { * struct x86_cpuinit_ops - platform specific cpu hotplug setups * @setup_percpu_clockev: set up the per cpu clock event device * @early_percpu_clock_init: early init of the per cpu clock event device - * @fixup_cpu_id: fixup function for cpuinfo_x86::phys_proc_id + * @fixup_cpu_id: fixup function for cpuinfo_x86::topo.pkg_id * @parallel_bringup: Parallel bringup control */ struct x86_cpuinit_ops { --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -169,7 +169,7 @@ static void fixup_cpu_id(struct cpuinfo_ nodes =3D ((val >> 3) & 7) + 1; } =20 - c->phys_proc_id =3D node / nodes; + c->topo.pkg_id =3D node / nodes; } =20 static int __init numachip_system_init(void) --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -456,9 +456,9 @@ static void amd_detect_cmp(struct cpuinf /* Low order bits define the core id (index of core in socket) */ c->cpu_core_id =3D c->topo.initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ - c->phys_proc_id =3D c->topo.initial_apicid >> bits; + c->topo.pkg_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ - per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->phys_proc_id; + per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->topo.pkg_id; } =20 u32 amd_get_nodes_per_socket(void) --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -875,10 +875,10 @@ void init_intel_cacheinfo(struct cpuinfo * turns means that the only possibility is SMT (as indicated in * cpuid1). Since cpuid2 doesn't specify shared caches, and we know * that SMT shares all caches, we can unconditionally set cpu_llc_id to - * c->phys_proc_id. + * c->topo.pkg_id. */ if (per_cpu(cpu_llc_id, cpu) =3D=3D BAD_APICID) - per_cpu(cpu_llc_id, cpu) =3D c->phys_proc_id; + per_cpu(cpu_llc_id, cpu) =3D c->topo.pkg_id; #endif =20 c->x86_cache_size =3D l3 ? l3 : (l2 ? l2 : (l1i+l1d)); --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -899,7 +899,7 @@ void detect_ht(struct cpuinfo_x86 *c) return; =20 index_msb =3D get_count_order(smp_num_siblings); - c->phys_proc_id =3D apic->phys_pkg_id(c->topo.initial_apicid, index_msb); + c->topo.pkg_id =3D apic->phys_pkg_id(c->topo.initial_apicid, index_msb); =20 smp_num_siblings =3D smp_num_siblings / c->x86_max_cores; =20 @@ -1729,7 +1729,7 @@ static void generic_identify(struct cpui c->topo.apicid =3D c->topo.initial_apicid; # endif #endif - c->phys_proc_id =3D c->topo.initial_apicid; + c->topo.pkg_id =3D c->topo.initial_apicid; } =20 get_model_name(c); /* Default name */ @@ -1767,7 +1767,7 @@ static void validate_apic_and_package_id pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", cpu, apicid, c->topo.initial_apicid); } - BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); + BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu)); BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); #else c->logical_proc_id =3D 0; --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -92,7 +92,7 @@ static void hygon_get_topology(struct cp * when running on host. */ if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && c->x86_model <=3D 0x3) - c->phys_proc_id =3D c->topo.apicid >> APICID_SOCKET_ID_BIT; + c->topo.pkg_id =3D c->topo.apicid >> APICID_SOCKET_ID_BIT; =20 cacheinfo_hygon_init_llc_id(c, cpu); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { @@ -122,9 +122,9 @@ static void hygon_detect_cmp(struct cpui /* Low order bits define the core id (index of core in socket) */ c->cpu_core_id =3D c->topo.initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ - c->phys_proc_id =3D c->topo.initial_apicid >> bits; + c->topo.pkg_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ - per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->phys_proc_id; + per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->topo.pkg_id; } =20 static void srat_detect_node(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -105,7 +105,7 @@ int apei_smca_report_x86_error(struct cp for_each_possible_cpu(cpu) { if (cpu_data(cpu).topo.initial_apicid =3D=3D lapic_id) { m.extcpu =3D cpu; - m.socketid =3D cpu_data(m.extcpu).phys_proc_id; + m.socketid =3D cpu_data(m.extcpu).topo.pkg_id; break; } } --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -123,7 +123,7 @@ void mce_setup(struct mce *m) m->time =3D __ktime_get_real_seconds(); m->cpuvendor =3D boot_cpu_data.x86_vendor; m->cpuid =3D cpuid_eax(1); - m->socketid =3D cpu_data(m->extcpu).phys_proc_id; + m->socketid =3D cpu_data(m->extcpu).topo.pkg_id; m->apicid =3D cpu_data(m->extcpu).topo.initial_apicid; m->mcgcap =3D __rdmsr(MSR_IA32_MCG_CAP); m->ppin =3D cpu_data(m->extcpu).ppin; --- a/arch/x86/kernel/cpu/proc.c +++ b/arch/x86/kernel/cpu/proc.c @@ -18,7 +18,7 @@ static void show_cpuinfo_core(struct seq unsigned int cpu) { #ifdef CONFIG_SMP - seq_printf(m, "physical id\t: %d\n", c->phys_proc_id); + seq_printf(m, "physical id\t: %d\n", c->topo.pkg_id); seq_printf(m, "siblings\t: %d\n", cpumask_weight(topology_core_cpumask(cpu))); seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id); --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -154,8 +154,7 @@ int detect_extended_topology(struct cpui core_plus_mask_width) & die_select_mask; } =20 - c->phys_proc_id =3D apic->phys_pkg_id(c->topo.initial_apicid, - pkg_mask_width); + c->topo.pkg_id =3D apic->phys_pkg_id(c->topo.initial_apicid, pkg_mask_wid= th); /* * Reinit the apicid, now that we have extended initial_apicid. */ --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -347,7 +347,7 @@ int topology_phys_to_logical_pkg(unsigne for_each_possible_cpu(cpu) { struct cpuinfo_x86 *c =3D &cpu_data(cpu); =20 - if (c->initialized && c->phys_proc_id =3D=3D phys_pkg) + if (c->initialized && c->topo.pkg_id =3D=3D phys_pkg) return c->logical_proc_id; } return -1; @@ -363,13 +363,13 @@ EXPORT_SYMBOL(topology_phys_to_logical_p */ static int topology_phys_to_logical_die(unsigned int die_id, unsigned int = cur_cpu) { - int cpu, proc_id =3D cpu_data(cur_cpu).phys_proc_id; + int cpu, proc_id =3D cpu_data(cur_cpu).topo.pkg_id; =20 for_each_possible_cpu(cpu) { struct cpuinfo_x86 *c =3D &cpu_data(cpu); =20 if (c->initialized && c->cpu_die_id =3D=3D die_id && - c->phys_proc_id =3D=3D proc_id) + c->topo.pkg_id =3D=3D proc_id) return c->logical_die_id; } return -1; @@ -429,7 +429,7 @@ void __init smp_store_boot_cpu_info(void =20 *c =3D boot_cpu_data; c->cpu_index =3D id; - topology_update_package_map(c->phys_proc_id, id); + topology_update_package_map(c->topo.pkg_id, id); topology_update_die_map(c->cpu_die_id, id); c->initialized =3D true; } @@ -484,7 +484,7 @@ static bool match_smt(struct cpuinfo_x86 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { int cpu1 =3D c->cpu_index, cpu2 =3D o->cpu_index; =20 - if (c->phys_proc_id =3D=3D o->phys_proc_id && + if (c->topo.pkg_id =3D=3D o->topo.pkg_id && c->cpu_die_id =3D=3D o->cpu_die_id && per_cpu(cpu_llc_id, cpu1) =3D=3D per_cpu(cpu_llc_id, cpu2)) { if (c->cpu_core_id =3D=3D o->cpu_core_id) @@ -496,7 +496,7 @@ static bool match_smt(struct cpuinfo_x86 return topology_sane(c, o, "smt"); } =20 - } else if (c->phys_proc_id =3D=3D o->phys_proc_id && + } else if (c->topo.pkg_id =3D=3D o->topo.pkg_id && c->cpu_die_id =3D=3D o->cpu_die_id && c->cpu_core_id =3D=3D o->cpu_core_id) { return topology_sane(c, o, "smt"); @@ -507,7 +507,7 @@ static bool match_smt(struct cpuinfo_x86 =20 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) { - if (c->phys_proc_id =3D=3D o->phys_proc_id && + if (c->topo.pkg_id =3D=3D o->topo.pkg_id && c->cpu_die_id =3D=3D o->cpu_die_id) return true; return false; @@ -535,7 +535,7 @@ static bool match_l2c(struct cpuinfo_x86 */ static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) { - if (c->phys_proc_id =3D=3D o->phys_proc_id) + if (c->topo.pkg_id =3D=3D o->topo.pkg_id) return true; return false; } --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -12428,9 +12428,6 @@ lpfc_cpu_affinity_check(struct lpfc_hba int max_core_id, min_core_id; struct lpfc_vector_map_info *cpup; struct lpfc_vector_map_info *new_cpup; -#ifdef CONFIG_X86 - struct cpuinfo_x86 *cpuinfo; -#endif #ifdef CONFIG_SCSI_LPFC_DEBUG_FS struct lpfc_hdwq_stat *c_stat; #endif @@ -12444,8 +12441,7 @@ lpfc_cpu_affinity_check(struct lpfc_hba for_each_present_cpu(cpu) { cpup =3D &phba->sli4_hba.cpu_map[cpu]; #ifdef CONFIG_X86 - cpuinfo =3D &cpu_data(cpu); - cpup->phys_id =3D cpuinfo->phys_proc_id; + cpup->phys_id =3D topology_physical_package_id(cpu); cpup->core_id =3D cpuinfo->cpu_core_id; if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id)) cpup->flag |=3D LPFC_CPU_MAP_HYPER; From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24A5EC04FE0 for ; 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No functional change. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- Documentation/arch/x86/topology.rst | 4 ++-- arch/x86/include/asm/processor.h | 4 +++- arch/x86/include/asm/topology.h | 2 +- arch/x86/kernel/cpu/amd.c | 8 ++++---- arch/x86/kernel/cpu/cacheinfo.c | 2 +- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/cpu/hygon.c | 8 ++++---- arch/x86/kernel/cpu/topology.c | 2 +- arch/x86/kernel/smpboot.c | 10 +++++----- 9 files changed, 22 insertions(+), 20 deletions(-) --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -55,7 +55,7 @@ AMD nomenclature for package is 'Node'. =20 The number of dies in a package. This information is retrieved via CPU= ID. =20 - - cpuinfo_x86.cpu_die_id: + - cpuinfo_x86.topo.die_id: =20 The physical ID of the die. This information is retrieved via CPUID. =20 @@ -65,7 +65,7 @@ AMD nomenclature for package is 'Node'. and deduced from the APIC IDs of the cores in the package. =20 Modern systems use this value for the socket. There may be multiple - packages within a socket. This value may differ from cpu_die_id. + packages within a socket. This value may differ from topo.die_id. =20 - cpuinfo_x86.logical_proc_id: =20 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -85,6 +85,9 @@ struct cpuinfo_topology { =20 // Physical package ID u32 pkg_id; + + // Physical die ID on AMD, Relative on Intel + u32 die_id; }; =20 struct cpuinfo_x86 { @@ -140,7 +143,6 @@ struct cpuinfo_x86 { u16 logical_proc_id; /* Core id: */ u16 cpu_core_id; - u16 cpu_die_id; u16 logical_die_id; /* Index into per_cpu list: */ u16 cpu_index; --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -108,7 +108,7 @@ extern const struct cpumask *cpu_cluster #define topology_logical_package_id(cpu) (cpu_data(cpu).logical_proc_id) #define topology_physical_package_id(cpu) (cpu_data(cpu).topo.pkg_id) #define topology_logical_die_id(cpu) (cpu_data(cpu).logical_die_id) -#define topology_die_id(cpu) (cpu_data(cpu).cpu_die_id) +#define topology_die_id(cpu) (cpu_data(cpu).topo.die_id) #define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id) #define topology_ppin(cpu) (cpu_data(cpu).ppin) =20 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -405,7 +405,7 @@ static void amd_get_topology(struct cpui =20 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); =20 - c->cpu_die_id =3D ecx & 0xff; + c->topo.die_id =3D ecx & 0xff; =20 if (c->x86 =3D=3D 0x15) c->cu_id =3D ebx & 0xff; @@ -431,9 +431,9 @@ static void amd_get_topology(struct cpui u64 value; =20 rdmsrl(MSR_FAM10H_NODE_ID, value); - c->cpu_die_id =3D value & 7; + c->topo.die_id =3D value & 7; =20 - per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id; + per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id; } else return; =20 @@ -458,7 +458,7 @@ static void amd_detect_cmp(struct cpuinf /* Convert the initial APIC ID into the socket ID */ c->topo.pkg_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ - per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->topo.pkg_id; + per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id =3D c->topo.pkg_id; } =20 u32 amd_get_nodes_per_socket(void) --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -672,7 +672,7 @@ void cacheinfo_amd_init_llc_id(struct cp =20 if (c->x86 < 0x17) { /* LLC is at the node level. */ - per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id; + per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id; } else if (c->x86 =3D=3D 0x17 && c->x86_model <=3D 0x1F) { /* * LLC is at the core complex level. --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1768,7 +1768,7 @@ static void validate_apic_and_package_id cpu, apicid, c->topo.initial_apicid); } BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu)); - BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); + BUG_ON(topology_update_die_map(c->topo.die_id, cpu)); #else c->logical_proc_id =3D 0; #endif --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -72,7 +72,7 @@ static void hygon_get_topology(struct cp =20 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); =20 - c->cpu_die_id =3D ecx & 0xff; + c->topo.die_id =3D ecx & 0xff; =20 c->cpu_core_id =3D ebx & 0xff; =20 @@ -95,9 +95,9 @@ static void hygon_get_topology(struct cp u64 value; =20 rdmsrl(MSR_FAM10H_NODE_ID, value); - c->cpu_die_id =3D value & 7; + c->topo.die_id =3D value & 7; =20 - per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id; + per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id; } else return; =20 @@ -120,7 +120,7 @@ static void hygon_detect_cmp(struct cpui /* Convert the initial APIC ID into the socket ID */ c->topo.pkg_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ - per_cpu(cpu_llc_id, cpu) =3D c->cpu_die_id =3D c->topo.pkg_id; + per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id =3D c->topo.pkg_id; } =20 static void srat_detect_node(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -150,7 +150,7 @@ int detect_extended_topology(struct cpui ht_mask_width) & core_select_mask; =20 if (die_level_present) { - c->cpu_die_id =3D apic->phys_pkg_id(c->topo.initial_apicid, + c->topo.die_id =3D apic->phys_pkg_id(c->topo.initial_apicid, core_plus_mask_width) & die_select_mask; } =20 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -368,7 +368,7 @@ static int topology_phys_to_logical_die( for_each_possible_cpu(cpu) { struct cpuinfo_x86 *c =3D &cpu_data(cpu); =20 - if (c->initialized && c->cpu_die_id =3D=3D die_id && + if (c->initialized && c->topo.die_id =3D=3D die_id && c->topo.pkg_id =3D=3D proc_id) return c->logical_die_id; } @@ -430,7 +430,7 @@ void __init smp_store_boot_cpu_info(void *c =3D boot_cpu_data; c->cpu_index =3D id; topology_update_package_map(c->topo.pkg_id, id); - topology_update_die_map(c->cpu_die_id, id); + topology_update_die_map(c->topo.die_id, id); c->initialized =3D true; } =20 @@ -485,7 +485,7 @@ static bool match_smt(struct cpuinfo_x86 int cpu1 =3D c->cpu_index, cpu2 =3D o->cpu_index; =20 if (c->topo.pkg_id =3D=3D o->topo.pkg_id && - c->cpu_die_id =3D=3D o->cpu_die_id && + c->topo.die_id =3D=3D o->topo.die_id && per_cpu(cpu_llc_id, cpu1) =3D=3D per_cpu(cpu_llc_id, cpu2)) { if (c->cpu_core_id =3D=3D o->cpu_core_id) return topology_sane(c, o, "smt"); @@ -497,7 +497,7 @@ static bool match_smt(struct cpuinfo_x86 } =20 } else if (c->topo.pkg_id =3D=3D o->topo.pkg_id && - c->cpu_die_id =3D=3D o->cpu_die_id && + c->topo.die_id =3D=3D o->topo.die_id && c->cpu_core_id =3D=3D o->cpu_core_id) { return topology_sane(c, o, "smt"); } @@ -508,7 +508,7 @@ static bool match_smt(struct cpuinfo_x86 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) { if (c->topo.pkg_id =3D=3D o->topo.pkg_id && - c->cpu_die_id =3D=3D o->cpu_die_id) + c->topo.die_id =3D=3D o->topo.die_id) return true; return false; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 419F9C04FE2 for ; Mon, 14 Aug 2023 08:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235224AbjHNIy3 (ORCPT ); Mon, 14 Aug 2023 04:54:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234610AbjHNIxr (ORCPT ); Mon, 14 Aug 2023 04:53:47 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD2CE91 for ; Mon, 14 Aug 2023 01:53:46 -0700 (PDT) Message-ID: <20230814085112.446856860@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003225; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=hQfYcdF7GQaITly9hGbfzZYC7LCrnAubPlWj7Dl2pNs=; b=a06S/CTtgTg7k5HXPKYcjhkOC7j8CkGJCLjd3yNTUf/sN5z7ru0X+R0oJejG1j71n45ivp Z+h5p8XPsnEPBwmihM7Or3jxjS+vujgWHkM0y3d2xH4FMHqKL2fHNZY2g97vQ8PMQ7RLoN xToev2bErj5+lR2EM1nxgyTjViN/WQaqB8oZ/2asvZByYTobSk0RRoOzOFi4kLxMi1iroa XhIuug3pGSBHtrPT6jwKgyNhq7NV+Xi/6mz4lYVspdurKWZ8z5HmIbcm5tP+x6kULPVewe Efvnvw8HbuSjAaGbhSrN84S1sKYpKJxS8KTwdoi/EdjUX+GjyywYcGNDJfjg5g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003225; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=hQfYcdF7GQaITly9hGbfzZYC7LCrnAubPlWj7Dl2pNs=; b=CHeAtbWEWvTSrsFCBOIlqm0BdEDeRkq6FgFnmiPLGp/r8LSwyL1JQ0y1GNpKF4fVvX0npg JCuOoE7kEVPc2WBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 07/41] scsi: lpfc: Use topology_core_id() References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:44 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the provided topology helper. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- drivers/scsi/lpfc/lpfc_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/scsi/lpfc/lpfc_init.c +++ b/drivers/scsi/lpfc/lpfc_init.c @@ -12442,7 +12442,7 @@ lpfc_cpu_affinity_check(struct lpfc_hba cpup =3D &phba->sli4_hba.cpu_map[cpu]; #ifdef CONFIG_X86 cpup->phys_id =3D topology_physical_package_id(cpu); - cpup->core_id =3D cpuinfo->cpu_core_id; + cpup->core_id =3D topology_core_id(cpu); if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id)) cpup->flag |=3D LPFC_CPU_MAP_HYPER; #else From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F12FC07E8A for ; Mon, 14 Aug 2023 08:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235243AbjHNIyb (ORCPT ); Mon, 14 Aug 2023 04:54:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234625AbjHNIxt (ORCPT ); Mon, 14 Aug 2023 04:53:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 540E591 for ; Mon, 14 Aug 2023 01:53:48 -0700 (PDT) Message-ID: <20230814085112.506988471@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003227; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8+6vOcIueVcOIj2konXv5XCSnSsK5weDJeCrayvpOfg=; b=fPzk2+J4fdut/Xv+4xRxKIHbg5QOGgBxAwmk+dsyGmjQ7b4HTZSWBG5ZTMnmBqgIXEZAPp bWPBnoXrjdSQUDs+WcusTiN7AFQUuR1NJIGogDsUfoM5bwSyo2GPtN8Q/rqpm6g/o6lTpZ fu/5OmGKqCKvzaf7jzICYs6puoAqb8ucUL/5bSSwAYrdLARUuDcflK47UMNJyEnLB13uUn oi+inRUOvwLEndabC5Lvv50XW5ewdWDH2vJeH4Y2UdqnsOzclcQfIqlk05H5cIFuomqrWH qNv8YR5xMMlM/lRuiA56PxJXA2cl7X34lXoMT+rk1w6RrEaS5dXN1tfkv7p4Rg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003227; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8+6vOcIueVcOIj2konXv5XCSnSsK5weDJeCrayvpOfg=; b=4oA3sMpg/OV8OMkmWdqy/4PuV2Mtdyv+g+ukz9FM2HO0WdJYqfg80p5wtnKtSQ6n1Joq8q 1b1fyLljTosEmzDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta , Guenter Roeck Subject: [patch V4 08/41] hwmon: (fam15h_power) Use topology_core_id() References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:46 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the provided topology helper function instead of fiddling in cpu_data. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Guenter Roeck Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- drivers/hwmon/fam15h_power.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) --- a/drivers/hwmon/fam15h_power.c +++ b/drivers/hwmon/fam15h_power.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include =20 @@ -134,15 +135,13 @@ static DEVICE_ATTR_RO(power1_crit); static void do_read_registers_on_cu(void *_data) { struct fam15h_power_data *data =3D _data; - int cpu, cu; - - cpu =3D smp_processor_id(); + int cu; =20 /* * With the new x86 topology modelling, cpu core id actually * is compute unit id. */ - cu =3D cpu_data(cpu).cpu_core_id; + cu =3D topology_core_id(smp_processor_id()); =20 rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]); rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81637C07E8C for ; Mon, 14 Aug 2023 08:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235293AbjHNIye (ORCPT ); Mon, 14 Aug 2023 04:54:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234663AbjHNIxv (ORCPT ); Mon, 14 Aug 2023 04:53:51 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3DE210B for ; Mon, 14 Aug 2023 01:53:49 -0700 (PDT) Message-ID: <20230814085112.566519388@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003228; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UWSNfisLrDq7vZIKxq2DYBQPw9DytxNCJqBpMt3RqRg=; b=OpX1jHTW2OvDEIOHyQjijQeHnGCTSNrhE9Nm3prSMSVb+lWaHrJ7q8ze6IXNFHbL7wV5Ms 7q6ZUN9CKeK09P8DCSkqsg295/rFCojCx1o2lG4rsTDC1Rr4Mt9XK5uayxYGu6pfMNABvA puFjz7M+1uSVtV4Hx4FljUeCuDC0m/bmADWLeNTQ2AkmlI6ADv10kdhY1o+Yx9++lwcqm6 X84mTK/ydcXQ/rfH5ddTwEcGb74+zzrx+Y3n6ekOEXx8Lzsxej5/pE3AJMm4p+mGNYoUb4 0RsVdxndjNvPSBM1OkYORbxOZnU3mm5xPN5F13W4L/3Pou2aAP6dKTFEPjo4HA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003228; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UWSNfisLrDq7vZIKxq2DYBQPw9DytxNCJqBpMt3RqRg=; b=/X0joLY9DZExcMV+vo52h6bWPFVcGXDqnEvCxGyZxhbQP0FAEpbCZeFFRU9sSxNQfshyer U9gXsIzsljO2ZeCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 09/41] x86/cpu: Move cpu_core_id into topology info References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:48 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename it to core_id and stick it to the other ID fields. No functional change. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/processor.h | 4 +++- arch/x86/include/asm/topology.h | 2 +- arch/x86/kernel/amd_nb.c | 4 ++-- arch/x86/kernel/cpu/amd.c | 8 ++++---- arch/x86/kernel/cpu/common.c | 4 ++-- arch/x86/kernel/cpu/hygon.c | 4 ++-- arch/x86/kernel/cpu/proc.c | 2 +- arch/x86/kernel/cpu/topology.c | 2 +- arch/x86/kernel/smpboot.c | 6 +++--- 9 files changed, 19 insertions(+), 17 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -88,6 +88,9 @@ struct cpuinfo_topology { =20 // Physical die ID on AMD, Relative on Intel u32 die_id; + + // Core ID relative to the package + u32 core_id; }; =20 struct cpuinfo_x86 { @@ -142,7 +145,6 @@ struct cpuinfo_x86 { /* Logical processor id: */ u16 logical_proc_id; /* Core id: */ - u16 cpu_core_id; u16 logical_die_id; /* Index into per_cpu list: */ u16 cpu_index; --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -109,7 +109,7 @@ extern const struct cpumask *cpu_cluster #define topology_physical_package_id(cpu) (cpu_data(cpu).topo.pkg_id) #define topology_logical_die_id(cpu) (cpu_data(cpu).logical_die_id) #define topology_die_id(cpu) (cpu_data(cpu).topo.die_id) -#define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id) +#define topology_core_id(cpu) (cpu_data(cpu).topo.core_id) #define topology_ppin(cpu) (cpu_data(cpu).ppin) =20 extern unsigned int __max_die_per_package; --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -378,7 +378,7 @@ int amd_get_subcaches(int cpu) =20 pci_read_config_dword(link, 0x1d4, &mask); =20 - return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf; + return (mask >> (4 * cpu_data(cpu).topo.core_id)) & 0xf; } =20 int amd_set_subcaches(int cpu, unsigned long mask) @@ -404,7 +404,7 @@ int amd_set_subcaches(int cpu, unsigned pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); } =20 - cuid =3D cpu_data(cpu).cpu_core_id; + cuid =3D cpu_data(cpu).topo.core_id; mask <<=3D 4 * cuid; mask |=3D (0xf ^ (1 << cuid)) << 26; =20 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -373,7 +373,7 @@ static int nearby_node(int apicid) #endif =20 /* - * Fix up cpu_core_id for pre-F17h systems to be in the + * Fix up topo::core_id for pre-F17h systems to be in the * [0 .. cores_per_node - 1] range. Not really needed but * kept so as not to break existing setups. */ @@ -385,7 +385,7 @@ static void legacy_fixup_core_id(struct return; =20 cus_per_node =3D c->x86_max_cores / nodes_per_socket; - c->cpu_core_id %=3D cus_per_node; + c->topo.core_id %=3D cus_per_node; } =20 /* @@ -411,7 +411,7 @@ static void amd_get_topology(struct cpui c->cu_id =3D ebx & 0xff; =20 if (c->x86 >=3D 0x17) { - c->cpu_core_id =3D ebx & 0xff; + c->topo.core_id =3D ebx & 0xff; =20 if (smp_num_siblings > 1) c->x86_max_cores /=3D smp_num_siblings; @@ -454,7 +454,7 @@ static void amd_detect_cmp(struct cpuinf =20 bits =3D c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ - c->cpu_core_id =3D c->topo.initial_apicid & ((1 << bits)-1); + c->topo.core_id =3D c->topo.initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ c->topo.pkg_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -907,8 +907,8 @@ void detect_ht(struct cpuinfo_x86 *c) =20 core_bits =3D get_count_order(c->x86_max_cores); =20 - c->cpu_core_id =3D apic->phys_pkg_id(c->topo.initial_apicid, index_msb) & - ((1 << core_bits) - 1); + c->topo.core_id =3D apic->phys_pkg_id(c->topo.initial_apicid, index_msb) & + ((1 << core_bits) - 1); #endif } =20 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -74,7 +74,7 @@ static void hygon_get_topology(struct cp =20 c->topo.die_id =3D ecx & 0xff; =20 - c->cpu_core_id =3D ebx & 0xff; + c->topo.core_id =3D ebx & 0xff; =20 if (smp_num_siblings > 1) c->x86_max_cores /=3D smp_num_siblings; @@ -116,7 +116,7 @@ static void hygon_detect_cmp(struct cpui =20 bits =3D c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ - c->cpu_core_id =3D c->topo.initial_apicid & ((1 << bits)-1); + c->topo.core_id =3D c->topo.initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ c->topo.pkg_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ --- a/arch/x86/kernel/cpu/proc.c +++ b/arch/x86/kernel/cpu/proc.c @@ -21,7 +21,7 @@ static void show_cpuinfo_core(struct seq seq_printf(m, "physical id\t: %d\n", c->topo.pkg_id); seq_printf(m, "siblings\t: %d\n", cpumask_weight(topology_core_cpumask(cpu))); - seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id); + seq_printf(m, "core id\t\t: %d\n", c->topo.core_id); seq_printf(m, "cpu cores\t: %d\n", c->booted_cores); seq_printf(m, "apicid\t\t: %d\n", c->topo.apicid); seq_printf(m, "initial apicid\t: %d\n", c->topo.initial_apicid); --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -146,7 +146,7 @@ int detect_extended_topology(struct cpui die_select_mask =3D (~(-1 << die_plus_mask_width)) >> core_plus_mask_width; =20 - c->cpu_core_id =3D apic->phys_pkg_id(c->topo.initial_apicid, + c->topo.core_id =3D apic->phys_pkg_id(c->topo.initial_apicid, ht_mask_width) & core_select_mask; =20 if (die_level_present) { --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -487,7 +487,7 @@ static bool match_smt(struct cpuinfo_x86 if (c->topo.pkg_id =3D=3D o->topo.pkg_id && c->topo.die_id =3D=3D o->topo.die_id && per_cpu(cpu_llc_id, cpu1) =3D=3D per_cpu(cpu_llc_id, cpu2)) { - if (c->cpu_core_id =3D=3D o->cpu_core_id) + if (c->topo.core_id =3D=3D o->topo.core_id) return topology_sane(c, o, "smt"); =20 if ((c->cu_id !=3D 0xff) && @@ -498,7 +498,7 @@ static bool match_smt(struct cpuinfo_x86 =20 } else if (c->topo.pkg_id =3D=3D o->topo.pkg_id && c->topo.die_id =3D=3D o->topo.die_id && - c->cpu_core_id =3D=3D o->cpu_core_id) { + c->topo.core_id =3D=3D o->topo.core_id) { return topology_sane(c, o, "smt"); } =20 @@ -1439,7 +1439,7 @@ static void remove_siblinginfo(int cpu) cpumask_clear(topology_sibling_cpumask(cpu)); cpumask_clear(topology_core_cpumask(cpu)); cpumask_clear(topology_die_cpumask(cpu)); - c->cpu_core_id =3D 0; + c->topo.core_id =3D 0; c->booted_cores =3D 0; cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); recompute_smt_state(); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D416C0729B for ; Mon, 14 Aug 2023 08:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235272AbjHNIyc (ORCPT ); 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003230; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yTUgg0W0G9jWjgIj3wVyaf91exB4JINYBe4Wj/AZErU=; b=TKRAtQVE4TiH9GewlTAyRvq2bs257mKlKvw0hKF3pIWQ2vKwTyJx+qknSr0bzgY+Qr8pBJ 3pHazl87UhVk2RAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 10/41] x86/cpu: Move cu_id into topology info References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:49 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No functional change. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/processor.h | 4 +++- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/smpboot.c | 6 +++--- 4 files changed, 8 insertions(+), 6 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -89,6 +89,9 @@ struct cpuinfo_topology { // Physical die ID on AMD, Relative on Intel u32 die_id; =20 + // Compute unit ID - AMD specific + u32 cu_id; + // Core ID relative to the package u32 core_id; }; @@ -109,7 +112,6 @@ struct cpuinfo_x86 { __u8 x86_phys_bits; /* CPUID returned core id bits: */ __u8 x86_coreid_bits; - __u8 cu_id; /* Max extended CPUID function supported: */ __u32 extended_cpuid_level; /* Maximum supported CPUID level, -1=3Dno CPUID: */ --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -408,7 +408,7 @@ static void amd_get_topology(struct cpui c->topo.die_id =3D ecx & 0xff; =20 if (c->x86 =3D=3D 0x15) - c->cu_id =3D ebx & 0xff; + c->topo.cu_id =3D ebx & 0xff; =20 if (c->x86 >=3D 0x17) { c->topo.core_id =3D ebx & 0xff; --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1789,7 +1789,7 @@ static void identify_cpu(struct cpuinfo_ c->x86_model_id[0] =3D '\0'; /* Unset */ c->x86_max_cores =3D 1; c->x86_coreid_bits =3D 0; - c->cu_id =3D 0xff; + c->topo.cu_id =3D 0xff; #ifdef CONFIG_X86_64 c->x86_clflush_size =3D 64; c->x86_phys_bits =3D 36; --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -490,9 +490,9 @@ static bool match_smt(struct cpuinfo_x86 if (c->topo.core_id =3D=3D o->topo.core_id) return topology_sane(c, o, "smt"); =20 - if ((c->cu_id !=3D 0xff) && - (o->cu_id !=3D 0xff) && - (c->cu_id =3D=3D o->cu_id)) + if ((c->topo.cu_id !=3D 0xff) && + (o->topo.cu_id !=3D 0xff) && + (c->topo.cu_id =3D=3D o->topo.cu_id)) return topology_sane(c, o, "smt"); } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F816C07E8B for ; Mon, 14 Aug 2023 08:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235338AbjHNIyh (ORCPT ); Mon, 14 Aug 2023 04:54:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234766AbjHNIxx (ORCPT ); Mon, 14 Aug 2023 04:53:53 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D3C891 for ; Mon, 14 Aug 2023 01:53:53 -0700 (PDT) Message-ID: <20230814085112.687588373@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003231; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pgQJfQpslITAglfzeFbwVD5u5BN9zZNZTRQkZDXXSN4=; b=IHFiWIGMKoHOuMcEZpQdp/I2x91VyrRpezp+ijjepqkWmBkzPY/WOB5lXWZjtequoKYUMJ ujZhHYq7Nw9IVwQmlrcD6BDGXDRAopzS1slfFIDBB4NZTbqEqjj0KZQYs7h2OjmjrOekUk Q3gNpfLZncesYfDl0BcIax4vdnImFeTa6iloRGUTMGWF5aUbsPumBH9q7ClzQGZr30aU2K WIw9TB048bgj0B36GQigD6CJoipcVzg/ACDy3v8y+py0yKvPrIAFhGoSd1PFsD/55IhB0G Cu9IcMfDiHTk+Ur1p8ONTV0wzRqqjWndE5uxm2NemDIP9i7IsB5osKW+4f3Utg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003231; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pgQJfQpslITAglfzeFbwVD5u5BN9zZNZTRQkZDXXSN4=; b=sgG4ENn41V9l2B1qOFIc6SzUzvL+GAW1hui83YUVc5wq3NPET6TGlVRa9cAdqi+6SsA/aW 0xV0hlCH7bkAZnBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 11/41] x86/cpu: Remove pointless evaluation of x86_coreid_bits References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:51 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cpuinfo_x86::x86_coreid_bits is only used by the AMD numa topology code. No point in evaluating it on non AMD systems. No functional change. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Reviewed-by: Arjan van de Ven Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/kernel/cpu/intel.c | 13 ------------- arch/x86/kernel/cpu/zhaoxin.c | 14 -------------- 2 files changed, 27 deletions(-) --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -488,19 +488,6 @@ static void early_init_intel(struct cpui setup_clear_cpu_cap(X86_FEATURE_PGE); } =20 - if (c->cpuid_level >=3D 0x00000001) { - u32 eax, ebx, ecx, edx; - - cpuid(0x00000001, &eax, &ebx, &ecx, &edx); - /* - * If HTT (EDX[28]) is set EBX[16:23] contain the number of - * apicids which are reserved per package. Store the resulting - * shift value for the package management code. - */ - if (edx & (1U << 28)) - c->x86_coreid_bits =3D get_count_order((ebx >> 16) & 0xff); - } - check_memory_type_self_snoop_errata(c); =20 /* --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -65,20 +65,6 @@ static void early_init_zhaoxin(struct cp set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); } - - if (c->cpuid_level >=3D 0x00000001) { - u32 eax, ebx, ecx, edx; - - cpuid(0x00000001, &eax, &ebx, &ecx, &edx); - /* - * If HTT (EDX[28]) is set EBX[16:23] contain the number of - * apicids which are reserved per package. Store the resulting - * shift value for the package management code. - */ - if (edx & (1U << 28)) - c->x86_coreid_bits =3D get_count_order((ebx >> 16) & 0xff); - } - } =20 static void init_zhaoxin(struct cpuinfo_x86 *c) From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A33E2C07E8D for ; Mon, 14 Aug 2023 08:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235362AbjHNIyj (ORCPT ); Mon, 14 Aug 2023 04:54:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234789AbjHNIxz (ORCPT ); Mon, 14 Aug 2023 04:53:55 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D16C010C for ; Mon, 14 Aug 2023 01:53:54 -0700 (PDT) Message-ID: <20230814085112.745139505@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003233; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5ebzz0txh4q26oEmhVdSaKtYdevMGFqxiQV9u7p6wPA=; b=lgjVDCICxK+urXw3E/IhocUIJnlWUhsEVFZVMUso5D+sB5fyziBubU/chetMoLmughHu9t yDj2yrUUHCIQ3HgVsehe13LHwrA/vAHnoQbDqbw46CxFvWEgitqYuMxpxcg+NayjIlCUdC E/NA07Bx4P2OLBT8/Culs5r03LYPxYCv8fRGu5YEOl+GRh69bxIqS3wEBgmMsWfpc4JUL8 ssUOmpcmth9cbkYVjes7xY8zegN9q+whFT+2RmkuSfdFNgvzR5HeGqax9bFQDhK1zrwwnx EyZd2OwUBlj5LFQyeCvoYtRmG9RQTv0V9N6EUrc5U2ns+QkYNDCJfgrW2Xn9Mw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003233; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5ebzz0txh4q26oEmhVdSaKtYdevMGFqxiQV9u7p6wPA=; b=y72bdPt6g89EAbrZ5T4cS86+sGcE1EhXeM0ZvPOk6Q3uMSO3j7LSp7Mjm5G62lJhVY4G8B IkDm94y6X1VHBoDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 12/41] x86/cpu: Move logical package and die IDs into topology info References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:52 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Yet another topology related data pair. Rename logical_proc_id to logical_pkg_id so it fits the common naming conventions. No functional change. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- Documentation/arch/x86/topology.rst | 2 +- arch/x86/events/intel/uncore.c | 2 +- arch/x86/include/asm/processor.h | 8 ++++---- arch/x86/include/asm/topology.h | 4 ++-- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/smpboot.c | 8 ++++---- 6 files changed, 13 insertions(+), 13 deletions(-) --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -67,7 +67,7 @@ AMD nomenclature for package is 'Node'. Modern systems use this value for the socket. There may be multiple packages within a socket. This value may differ from topo.die_id. =20 - - cpuinfo_x86.logical_proc_id: + - cpuinfo_x86.topo.logical_pkg_id: =20 The logical ID of the package. As we do not trust BIOSes to enumerate = the packages in a consistent way, we introduced the concept of logical pac= kage --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -74,7 +74,7 @@ int uncore_device_to_die(struct pci_dev struct cpuinfo_x86 *c =3D &cpu_data(cpu); =20 if (c->initialized && cpu_to_node(cpu) =3D=3D node) - return c->logical_die_id; + return c->topo.logical_die_id; } =20 return -1; --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -94,6 +94,10 @@ struct cpuinfo_topology { =20 // Core ID relative to the package u32 core_id; + + // Logical ID mappings + u32 logical_pkg_id; + u32 logical_die_id; }; =20 struct cpuinfo_x86 { @@ -144,10 +148,6 @@ struct cpuinfo_x86 { u16 x86_clflush_size; /* number of cores as seen by the OS: */ u16 booted_cores; - /* Logical processor id: */ - u16 logical_proc_id; - /* Core id: */ - u16 logical_die_id; /* Index into per_cpu list: */ u16 cpu_index; /* Is SMT active on this core? */ --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -105,9 +105,9 @@ static inline void setup_node_to_cpumask extern const struct cpumask *cpu_coregroup_mask(int cpu); extern const struct cpumask *cpu_clustergroup_mask(int cpu); =20 -#define topology_logical_package_id(cpu) (cpu_data(cpu).logical_proc_id) +#define topology_logical_package_id(cpu) (cpu_data(cpu).topo.logical_pkg_i= d) #define topology_physical_package_id(cpu) (cpu_data(cpu).topo.pkg_id) -#define topology_logical_die_id(cpu) (cpu_data(cpu).logical_die_id) +#define topology_logical_die_id(cpu) (cpu_data(cpu).topo.logical_die_id) #define topology_die_id(cpu) (cpu_data(cpu).topo.die_id) #define topology_core_id(cpu) (cpu_data(cpu).topo.core_id) #define topology_ppin(cpu) (cpu_data(cpu).ppin) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1770,7 +1770,7 @@ static void validate_apic_and_package_id BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu)); BUG_ON(topology_update_die_map(c->topo.die_id, cpu)); #else - c->logical_proc_id =3D 0; + c->topo.logical_pkg_id =3D 0; #endif } =20 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -348,7 +348,7 @@ int topology_phys_to_logical_pkg(unsigne struct cpuinfo_x86 *c =3D &cpu_data(cpu); =20 if (c->initialized && c->topo.pkg_id =3D=3D phys_pkg) - return c->logical_proc_id; + return c->topo.logical_pkg_id; } return -1; } @@ -370,7 +370,7 @@ static int topology_phys_to_logical_die( =20 if (c->initialized && c->topo.die_id =3D=3D die_id && c->topo.pkg_id =3D=3D proc_id) - return c->logical_die_id; + return c->topo.logical_die_id; } return -1; } @@ -395,7 +395,7 @@ int topology_update_package_map(unsigned cpu, pkg, new); } found: - cpu_data(cpu).logical_proc_id =3D new; + cpu_data(cpu).topo.logical_pkg_id =3D new; return 0; } /** @@ -418,7 +418,7 @@ int topology_update_die_map(unsigned int cpu, die, new); } found: - cpu_data(cpu).logical_die_id =3D new; + cpu_data(cpu).topo.logical_die_id =3D new; return 0; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F273C001B0 for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230302AbjHNIyq (ORCPT ); Mon, 14 Aug 2023 04:54:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234922AbjHNIx5 (ORCPT ); Mon, 14 Aug 2023 04:53:57 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AAE191 for ; Mon, 14 Aug 2023 01:53:56 -0700 (PDT) Message-ID: <20230814085112.803864641@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003235; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=YEUGY/VnQEggbRIpLvCb5kRW081uPfIIdruq26+YjFk=; b=woRD8QF/yhA26XZut3uJPtdocTNmy0iuSp2Iis/MvjeBBSUQqs6XDGTvinAE+OgY/4EsFh 6ybOdh+imgIhQW0j5KZoz02+lBQySbtBFz9tvjM2RUys2c5BWunwtC85aa+WS3P2L+SVIj hDJ+9vzpOQYAcGSU4dfB1OlysZ31h9+SPU1g05BE+n8ubR8ZuzljEQKoeOGopNfjljfdZV JeArIVITKLsuCsLClC1thAkEMZ6F1sstTP3xBETl5PcaWML1nOzaMKdtVFf6+kUE/pDXQu Ix69yRYQ1qskl5WQsBcUWJq/cEyMK1tKPnJU4NMZWBp2moAU3nHJNcwrW73nlA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003235; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=YEUGY/VnQEggbRIpLvCb5kRW081uPfIIdruq26+YjFk=; b=8E7Bkmr3c+zE2L1zNPcpmrFQFRwqyhjusjR8ZWm9WBe4ucmwv9LG93Awgq3x8pIq71Xsux 5NHZbNnwZUgLNUDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 13/41] x86/cpu: Move cpu_l[l2]c_id into topology info References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:54 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The topology IDs which identify the LLC and L2 domains clearly belong to the per CPU topology information. Move them into cpuinfo_x86::cpuinfo_topo and get rid of the extra per CPU data and the related exports. This also paves the way to do proper topology evaluation during early boot because it removes the only per CPU dependency for that. No functional change. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Reviewed-by: Arjan van de Ven Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- Documentation/arch/x86/topology.rst | 4 +--- arch/x86/events/amd/uncore.c | 2 +- arch/x86/include/asm/cacheinfo.h | 3 --- arch/x86/include/asm/processor.h | 14 +++++++++++++- arch/x86/include/asm/smp.h | 2 -- arch/x86/include/asm/topology.h | 2 +- arch/x86/kernel/apic/apic_numachip.c | 2 +- arch/x86/kernel/cpu/amd.c | 12 ++++-------- arch/x86/kernel/cpu/cacheinfo.c | 33 ++++++++++++------------------= --- arch/x86/kernel/cpu/common.c | 14 ++------------ arch/x86/kernel/cpu/cpu.h | 3 +++ arch/x86/kernel/cpu/hygon.c | 14 +++++--------- arch/x86/kernel/smpboot.c | 10 +++++----- 13 files changed, 48 insertions(+), 67 deletions(-) --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -79,9 +79,7 @@ AMD nomenclature for package is 'Node'. The maximum possible number of packages in the system. Helpful for per package facilities to preallocate per package information. =20 - - cpu_llc_id: - - A per-CPU variable containing: + - cpuinfo_x86.topo.llc_id: =20 - On Intel, the first APIC ID of the list of CPUs sharing the Last L= evel Cache --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -537,7 +537,7 @@ static int amd_uncore_cpu_starting(unsig =20 if (amd_uncore_llc) { uncore =3D *per_cpu_ptr(amd_uncore_llc, cpu); - uncore->id =3D get_llc_id(cpu); + uncore->id =3D per_cpu_llc_id(cpu); =20 uncore =3D amd_uncore_find_online_sibling(uncore, amd_uncore_llc); *per_cpu_ptr(amd_uncore_llc, cpu) =3D uncore; --- a/arch/x86/include/asm/cacheinfo.h +++ b/arch/x86/include/asm/cacheinfo.h @@ -7,9 +7,6 @@ extern unsigned int memory_caching_contr #define CACHE_MTRR 0x01 #define CACHE_PAT 0x02 =20 -void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu); -void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu); - void cache_disable(void); void cache_enable(void); void set_cache_aps_delayed_init(bool val); --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -98,6 +98,10 @@ struct cpuinfo_topology { // Logical ID mappings u32 logical_pkg_id; u32 logical_die_id; + + // Cache level topology IDs + u32 llc_id; + u32 l2c_id; }; =20 struct cpuinfo_x86 { @@ -687,7 +691,15 @@ extern int set_tsc_mode(unsigned int val =20 DECLARE_PER_CPU(u64, msr_misc_features_shadow); =20 -extern u16 get_llc_id(unsigned int cpu); +static inline u16 per_cpu_llc_id(unsigned int cpu) +{ + return per_cpu(cpu_info.topo.llc_id, cpu); +} + +static inline u16 per_cpu_l2c_id(unsigned int cpu) +{ + return per_cpu(cpu_info.topo.l2c_id, cpu); +} =20 #ifdef CONFIG_CPU_SUP_AMD extern u32 amd_get_nodes_per_socket(void); --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -17,8 +17,6 @@ DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_ /* cpus sharing the last level cache: */ DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_l2c_shared_map); -DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id); -DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id); =20 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid); DECLARE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid); --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -115,7 +115,7 @@ extern const struct cpumask *cpu_cluster extern unsigned int __max_die_per_package; =20 #ifdef CONFIG_SMP -#define topology_cluster_id(cpu) (per_cpu(cpu_l2c_id, cpu)) +#define topology_cluster_id(cpu) (cpu_data(cpu).topo.l2c_id) #define topology_die_cpumask(cpu) (per_cpu(cpu_die_map, cpu)) #define topology_cluster_cpumask(cpu) (cpu_clustergroup_mask(cpu)) #define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu)) --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -161,7 +161,7 @@ static void fixup_cpu_id(struct cpuinfo_ u64 val; u32 nodes =3D 1; =20 - this_cpu_write(cpu_llc_id, node); + c->topo.llc_id =3D node; =20 /* Account for nodes per socket in multi-core-module processors */ if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -396,8 +396,6 @@ static void legacy_fixup_core_id(struct */ static void amd_get_topology(struct cpuinfo_x86 *c) { - int cpu =3D smp_processor_id(); - /* get information required for multi-node processors */ if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { int err; @@ -425,15 +423,14 @@ static void amd_get_topology(struct cpui if (!err) c->x86_coreid_bits =3D get_count_order(c->x86_max_cores); =20 - cacheinfo_amd_init_llc_id(c, cpu); + cacheinfo_amd_init_llc_id(c); =20 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; =20 rdmsrl(MSR_FAM10H_NODE_ID, value); c->topo.die_id =3D value & 7; - - per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id; + c->topo.llc_id =3D c->topo.die_id; } else return; =20 @@ -450,7 +447,6 @@ static void amd_get_topology(struct cpui static void amd_detect_cmp(struct cpuinfo_x86 *c) { unsigned bits; - int cpu =3D smp_processor_id(); =20 bits =3D c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ @@ -458,7 +454,7 @@ static void amd_detect_cmp(struct cpuinf /* Convert the initial APIC ID into the socket ID */ c->topo.pkg_id =3D c->topo.initial_apicid >> bits; /* use socket ID also for last level cache */ - per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id =3D c->topo.pkg_id; + c->topo.llc_id =3D c->topo.die_id =3D c->topo.pkg_id; } =20 u32 amd_get_nodes_per_socket(void) @@ -476,7 +472,7 @@ static void srat_detect_node(struct cpui =20 node =3D numa_cpu_node(cpu); if (node =3D=3D NUMA_NO_NODE) - node =3D get_llc_id(cpu); + node =3D per_cpu_llc_id(cpu); =20 /* * On multi-fabric platform (e.g. Numascale NumaChip) a --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -661,7 +661,7 @@ static int find_num_cache_leaves(struct return i; } =20 -void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu) +void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c) { /* * We may have multiple LLCs if L3 caches exist, so check if we @@ -672,13 +672,13 @@ void cacheinfo_amd_init_llc_id(struct cp =20 if (c->x86 < 0x17) { /* LLC is at the node level. */ - per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id; + c->topo.llc_id =3D c->topo.die_id; } else if (c->x86 =3D=3D 0x17 && c->x86_model <=3D 0x1F) { /* * LLC is at the core complex level. * Core complex ID is ApicId[3] for these processors. */ - per_cpu(cpu_llc_id, cpu) =3D c->topo.apicid >> 3; + c->topo.llc_id =3D c->topo.apicid >> 3; } else { /* * LLC ID is calculated from the number of threads sharing the @@ -694,12 +694,12 @@ void cacheinfo_amd_init_llc_id(struct cp if (num_sharing_cache) { int bits =3D get_count_order(num_sharing_cache); =20 - per_cpu(cpu_llc_id, cpu) =3D c->topo.apicid >> bits; + c->topo.llc_id =3D c->topo.apicid >> bits; } } } =20 -void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu) +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c) { /* * We may have multiple LLCs if L3 caches exist, so check if we @@ -712,7 +712,7 @@ void cacheinfo_hygon_init_llc_id(struct * LLC is at the core complex level. * Core complex ID is ApicId[3] for these processors. */ - per_cpu(cpu_llc_id, cpu) =3D c->topo.apicid >> 3; + c->topo.llc_id =3D c->topo.apicid >> 3; } =20 void init_amd_cacheinfo(struct cpuinfo_x86 *c) @@ -740,9 +740,6 @@ void init_intel_cacheinfo(struct cpuinfo unsigned int new_l1d =3D 0, new_l1i =3D 0; /* Cache sizes from cpuid(4) */ unsigned int new_l2 =3D 0, new_l3 =3D 0, i; /* Cache sizes from cpuid(4) = */ unsigned int l2_id =3D 0, l3_id =3D 0, num_threads_sharing, index_msb; -#ifdef CONFIG_SMP - unsigned int cpu =3D c->cpu_index; -#endif =20 if (c->cpuid_level > 3) { static int is_initialized; @@ -856,30 +853,24 @@ void init_intel_cacheinfo(struct cpuinfo =20 if (new_l2) { l2 =3D new_l2; -#ifdef CONFIG_SMP - per_cpu(cpu_llc_id, cpu) =3D l2_id; - per_cpu(cpu_l2c_id, cpu) =3D l2_id; -#endif + c->topo.llc_id =3D l2_id; + c->topo.l2c_id =3D l2_id; } =20 if (new_l3) { l3 =3D new_l3; -#ifdef CONFIG_SMP - per_cpu(cpu_llc_id, cpu) =3D l3_id; -#endif + c->topo.llc_id =3D l3_id; } =20 -#ifdef CONFIG_SMP /* - * If cpu_llc_id is not yet set, this means cpuid_level < 4 which in + * If llc_id is not yet set, this means cpuid_level < 4 which in * turns means that the only possibility is SMT (as indicated in * cpuid1). Since cpuid2 doesn't specify shared caches, and we know * that SMT shares all caches, we can unconditionally set cpu_llc_id to * c->topo.pkg_id. */ - if (per_cpu(cpu_llc_id, cpu) =3D=3D BAD_APICID) - per_cpu(cpu_llc_id, cpu) =3D c->topo.pkg_id; -#endif + if (c->topo.llc_id =3D=3D BAD_APICID) + c->topo.llc_id =3D c->topo.pkg_id; =20 c->x86_cache_size =3D l3 ? l3 : (l2 ? l2 : (l1i+l1d)); =20 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -75,18 +75,6 @@ u32 elf_hwcap2 __read_mostly; int smp_num_siblings =3D 1; EXPORT_SYMBOL(smp_num_siblings); =20 -/* Last level cache ID of each logical CPU */ -DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) =3D BAD_APICID; - -u16 get_llc_id(unsigned int cpu) -{ - return per_cpu(cpu_llc_id, cpu); -} -EXPORT_SYMBOL_GPL(get_llc_id); - -/* L2 cache ID of each logical CPU */ -DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) =3D BAD_APICID; - static struct ppin_info { int feature; int msr_ppin_ctl; @@ -1790,6 +1778,8 @@ static void identify_cpu(struct cpuinfo_ c->x86_max_cores =3D 1; c->x86_coreid_bits =3D 0; c->topo.cu_id =3D 0xff; + c->topo.llc_id =3D BAD_APICID; + c->topo.l2c_id =3D BAD_APICID; #ifdef CONFIG_X86_64 c->x86_clflush_size =3D 64; c->x86_phys_bits =3D 36; --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -78,6 +78,9 @@ extern int detect_ht_early(struct cpuinf extern void detect_ht(struct cpuinfo_x86 *c); extern void check_null_seg_clears_base(struct cpuinfo_x86 *c); =20 +void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c); +void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c); + unsigned int aperfmperf_get_khz(int cpu); void cpu_select_mitigations(void); =20 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -63,8 +63,6 @@ static void hygon_get_topology_early(str */ static void hygon_get_topology(struct cpuinfo_x86 *c) { - int cpu =3D smp_processor_id(); - /* get information required for multi-node processors */ if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { int err; @@ -94,14 +92,13 @@ static void hygon_get_topology(struct cp if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && c->x86_model <=3D 0x3) c->topo.pkg_id =3D c->topo.apicid >> APICID_SOCKET_ID_BIT; =20 - cacheinfo_hygon_init_llc_id(c, cpu); + cacheinfo_hygon_init_llc_id(c); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; =20 rdmsrl(MSR_FAM10H_NODE_ID, value); c->topo.die_id =3D value & 7; - - per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id; + c->topo.llc_id =3D c->topo.die_id; } else return; =20 @@ -116,15 +113,14 @@ static void hygon_get_topology(struct cp static void hygon_detect_cmp(struct cpuinfo_x86 *c) { unsigned int bits; - int cpu =3D smp_processor_id(); =20 bits =3D c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ c->topo.core_id =3D c->topo.initial_apicid & ((1 << bits)-1); /* Convert the initial APIC ID into the socket ID */ c->topo.pkg_id =3D c->topo.initial_apicid >> bits; - /* use socket ID also for last level cache */ - per_cpu(cpu_llc_id, cpu) =3D c->topo.die_id =3D c->topo.pkg_id; + /* Use package ID also for last level cache */ + c->topo.llc_id =3D c->topo.die_id =3D c->topo.pkg_id; } =20 static void srat_detect_node(struct cpuinfo_x86 *c) @@ -136,7 +132,7 @@ static void srat_detect_node(struct cpui =20 node =3D numa_cpu_node(cpu); if (node =3D=3D NUMA_NO_NODE) - node =3D per_cpu(cpu_llc_id, cpu); + node =3D c->topo.llc_id; =20 /* * On multi-fabric platform (e.g. Numascale NumaChip) a --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -486,7 +486,7 @@ static bool match_smt(struct cpuinfo_x86 =20 if (c->topo.pkg_id =3D=3D o->topo.pkg_id && c->topo.die_id =3D=3D o->topo.die_id && - per_cpu(cpu_llc_id, cpu1) =3D=3D per_cpu(cpu_llc_id, cpu2)) { + per_cpu_llc_id(cpu1) =3D=3D per_cpu_llc_id(cpu2)) { if (c->topo.core_id =3D=3D o->topo.core_id) return topology_sane(c, o, "smt"); =20 @@ -518,11 +518,11 @@ static bool match_l2c(struct cpuinfo_x86 int cpu1 =3D c->cpu_index, cpu2 =3D o->cpu_index; =20 /* If the arch didn't set up l2c_id, fall back to SMT */ - if (per_cpu(cpu_l2c_id, cpu1) =3D=3D BAD_APICID) + if (per_cpu_l2c_id(cpu1) =3D=3D BAD_APICID) return match_smt(c, o); =20 /* Do not match if L2 cache id does not match: */ - if (per_cpu(cpu_l2c_id, cpu1) !=3D per_cpu(cpu_l2c_id, cpu2)) + if (per_cpu_l2c_id(cpu1) !=3D per_cpu_l2c_id(cpu2)) return false; =20 return topology_sane(c, o, "l2c"); @@ -568,11 +568,11 @@ static bool match_llc(struct cpuinfo_x86 bool intel_snc =3D id && id->driver_data; =20 /* Do not match if we do not have a valid APICID for cpu: */ - if (per_cpu(cpu_llc_id, cpu1) =3D=3D BAD_APICID) + if (per_cpu_llc_id(cpu1) =3D=3D BAD_APICID) return false; =20 /* Do not match if LLC id does not match: */ - if (per_cpu(cpu_llc_id, cpu1) !=3D per_cpu(cpu_llc_id, cpu2)) + if (per_cpu_llc_id(cpu1) !=3D per_cpu_llc_id(cpu2)) return false; =20 /* From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63A8FC04FDF for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234922AbjHNIyv (ORCPT ); Mon, 14 Aug 2023 04:54:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234931AbjHNIx6 (ORCPT ); Mon, 14 Aug 2023 04:53:58 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDC6D10B for ; Mon, 14 Aug 2023 01:53:57 -0700 (PDT) Message-ID: <20230814085112.862835121@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003236; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bd7aVAkdU8hKlGLozvpCQgzrwCUOG24alOTKZ7VboAQ=; b=uEjAJG0NkROXgPFtaoyDvfr/S9b5Zl0n217RTuiqSmVgO/EMg3diLngXj0b8P8fRG4MGsm iXJrSutNAbJHpsIwbyjpCNHTWzho1hAn0G9bqKzZF9JJq/eICymxN1OELDw2e4qJ+ZfT6w mAfj9ceY0OQW5sNhnTRDBQcLiJZE4YQr5nvXD52XlSoPamZByc0S52DiEh4NnK+hbrvWik 5/YAGptvLvqMwuv9sQwOl7LyYTL35xhea/GT0dCXF/1VIICpjVGaQFZV0vipJEyWZpoaL9 c2fYuxvpT0rQibKioUDNo8nLOhpzoXiBZorBPUrsPsP/xrIk3HKyhVkDWIy5cw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003236; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bd7aVAkdU8hKlGLozvpCQgzrwCUOG24alOTKZ7VboAQ=; b=udlUfvpc16LJ43bOLabICosbCFJfGjee0veDKBfD7yFKRAHsf9X2p4evlVVGXQeXo50TND txOELKFFDQIobCDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 14/41] x86/apic: Use BAD_APICID consistently References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:56 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APIC ID checks compare with BAD_APICID all over the place, but some initializers and some code which fiddles with global data structure use -1[U] instead. That simply cannot work at all. Fix it up and use BAD_APICID consistently all over the place. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V3: Fixed changelog typos - Sohil --- arch/x86/kernel/acpi/boot.c | 2 +- arch/x86/kernel/apic/apic.c | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -852,7 +852,7 @@ int acpi_unmap_cpu(int cpu) set_apicid_to_node(per_cpu(x86_cpu_to_apicid, cpu), NUMA_NO_NODE); #endif =20 - per_cpu(x86_cpu_to_apicid, cpu) =3D -1; + per_cpu(x86_cpu_to_apicid, cpu) =3D BAD_APICID; set_cpu_present(cpu, false); num_processors--; =20 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -72,7 +72,7 @@ unsigned int num_processors; unsigned disabled_cpus; =20 /* Processor that is doing the boot up */ -unsigned int boot_cpu_physical_apicid __ro_after_init =3D -1U; +unsigned int boot_cpu_physical_apicid __ro_after_init =3D BAD_APICID; EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); =20 u8 boot_cpu_apic_version __ro_after_init; @@ -2318,9 +2318,7 @@ static int nr_logical_cpuids =3D 1; /* * Used to store mapping between logical CPU IDs and APIC IDs. */ -int cpuid_to_apicid[] =3D { - [0 ... NR_CPUS - 1] =3D -1, -}; +int cpuid_to_apicid[] =3D { [0 ... NR_CPUS - 1] =3D BAD_APICID, }; =20 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79BC1C04E69 for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234710AbjHNIyz (ORCPT ); Mon, 14 Aug 2023 04:54:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234933AbjHNIyA (ORCPT ); Mon, 14 Aug 2023 04:54:00 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9103491 for ; Mon, 14 Aug 2023 01:53:59 -0700 (PDT) Message-ID: <20230814085112.922905727@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003238; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6qXwIgtlNuQlqn3hnibzw60wGRFGM50r9/5Ntn8tkso=; b=NIdZ4bPu+YdqwXOmj2jPp0Ti6XDDANPTZYeu08kq+JdITtjgqtQoKnjKUNqCATMmYAooYU jl8JDsiS/zNX/X7BLle9xXKarvK9x3aMNKIM7TsngIA2vyEytYCplVlN6kTepRrKZYOMgJ qcWqw1xUWofEEspSuQjz7IzZ0H5oIqKD5Q10K1bGp7pXhl5SxAlqYk+P4/QSsx0cETpLBR qa/C7nDmd91yHppkQFSc5UYdaIikfQc3a/FS7B3TMWBNZ1twFHjYrkUiLFx9O0THI33itE UfIbng9tyo22DcLEVGOL1JzCvLIrVYPGY50gEabM/fGi59nssx/+jkcU2XvFrw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003238; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6qXwIgtlNuQlqn3hnibzw60wGRFGM50r9/5Ntn8tkso=; b=2zrydaU/XGc5vWVm6ebLk8sWgiswxR8iHCEDy+ah/RE7VKSNLCmL6GKfuQRG8diQeWpXYt c4/UhumeFua+HLAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 15/41] x86/apic: Use u32 for APIC IDs in global data References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:57 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width and fixup the most obvious usage sites of that. The APIC callbacks will be addressed separately. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Reviewed-by: Arjan van de Ven Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/apic.h | 8 ++++---- arch/x86/include/asm/mpspec.h | 2 +- arch/x86/include/asm/processor.h | 4 ++-- arch/x86/include/asm/smp.h | 2 +- arch/x86/kernel/apic/apic.c | 16 ++++++++-------- arch/x86/kernel/apic/ipi.c | 5 +++-- arch/x86/kernel/kvm.c | 6 +++--- arch/x86/mm/numa.c | 4 ++-- 8 files changed, 24 insertions(+), 23 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -54,7 +54,7 @@ extern int local_apic_timer_c2_ok; extern bool apic_is_disabled; extern unsigned int lapic_timer_period; =20 -extern int cpuid_to_apicid[]; +extern u32 cpuid_to_apicid[]; =20 extern enum apic_intr_mode_id apic_intr_mode; enum apic_intr_mode_id { @@ -517,9 +517,9 @@ extern void generic_bigsmp_probe(void); =20 extern struct apic apic_noop; =20 -static inline unsigned int read_apic_id(void) +static inline u32 read_apic_id(void) { - unsigned int reg =3D apic_read(APIC_ID); + u32 reg =3D apic_read(APIC_ID); =20 return apic->get_apic_id(reg); } @@ -544,7 +544,7 @@ extern int default_cpu_present_to_apicid =20 #else /* CONFIG_X86_LOCAL_APIC */ =20 -static inline unsigned int read_apic_id(void) { return 0; } +static inline u32 read_apic_id(void) { return 0; } =20 #endif /* !CONFIG_X86_LOCAL_APIC */ =20 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -37,7 +37,7 @@ extern int mp_bus_id_to_type[MAX_MP_BUSS =20 extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); =20 -extern unsigned int boot_cpu_physical_apicid; +extern u32 boot_cpu_physical_apicid; extern u8 boot_cpu_apic_version; =20 #ifdef CONFIG_X86_LOCAL_APIC --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -691,12 +691,12 @@ extern int set_tsc_mode(unsigned int val =20 DECLARE_PER_CPU(u64, msr_misc_features_shadow); =20 -static inline u16 per_cpu_llc_id(unsigned int cpu) +static inline u32 per_cpu_llc_id(unsigned int cpu) { return per_cpu(cpu_info.topo.llc_id, cpu); } =20 -static inline u16 per_cpu_l2c_id(unsigned int cpu) +static inline u32 per_cpu_l2c_id(unsigned int cpu) { return per_cpu(cpu_info.topo.l2c_id, cpu); } --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -18,7 +18,7 @@ DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_ DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_l2c_shared_map); =20 -DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid); +DECLARE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid); DECLARE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid); =20 struct task_struct; --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -72,7 +72,7 @@ unsigned int num_processors; unsigned disabled_cpus; =20 /* Processor that is doing the boot up */ -unsigned int boot_cpu_physical_apicid __ro_after_init =3D BAD_APICID; +u32 boot_cpu_physical_apicid __ro_after_init =3D BAD_APICID; EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); =20 u8 boot_cpu_apic_version __ro_after_init; @@ -87,7 +87,7 @@ physid_mask_t phys_cpu_present_map; * disable_cpu_apicid=3D, mostly used for the kdump 2nd kernel to * avoid undefined behaviour caused by sending INIT from AP to BSP. */ -static unsigned int disabled_cpu_apicid __ro_after_init =3D BAD_APICID; +static u32 disabled_cpu_apicid __ro_after_init =3D BAD_APICID; =20 /* * This variable controls which CPUs receive external NMIs. By default, @@ -111,7 +111,7 @@ static inline bool apic_accessible(void) /* * Map cpu index to physical APIC ID */ -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); +DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid, BAD_APICID); DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); @@ -1765,7 +1765,7 @@ static void __x2apic_enable(void) static int __init setup_nox2apic(char *str) { if (x2apic_enabled()) { - int apicid =3D native_apic_msr_read(APIC_ID); + u32 apicid =3D native_apic_msr_read(APIC_ID); =20 if (apicid >=3D 255) { pr_warn("Apicid: %08x, cannot enforce nox2apic\n", @@ -2318,11 +2318,11 @@ static int nr_logical_cpuids =3D 1; /* * Used to store mapping between logical CPU IDs and APIC IDs. */ -int cpuid_to_apicid[] =3D { [0 ... NR_CPUS - 1] =3D BAD_APICID, }; +u32 cpuid_to_apicid[] =3D { [0 ... NR_CPUS - 1] =3D BAD_APICID, }; =20 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { - return phys_id =3D=3D cpuid_to_apicid[cpu]; + return phys_id =3D=3D (u64)cpuid_to_apicid[cpu]; } =20 #ifdef CONFIG_SMP @@ -2391,7 +2391,7 @@ static int allocate_logical_cpuid(int ap return nr_logical_cpuids++; } =20 -static void cpu_update_apic(int cpu, int apicid) +static void cpu_update_apic(int cpu, u32 apicid) { #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; @@ -2544,7 +2544,7 @@ static struct { */ int active; /* r/w apic fields */ - unsigned int apic_id; + u32 apic_id; unsigned int apic_taskpri; unsigned int apic_ldr; unsigned int apic_dfr; --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -280,7 +280,7 @@ void default_send_IPI_mask_logical(const local_irq_restore(flags); } =20 -static int convert_apicid_to_cpu(int apic_id) +static int convert_apicid_to_cpu(u32 apic_id) { int i; =20 @@ -293,7 +293,8 @@ static int convert_apicid_to_cpu(int api =20 int safe_smp_processor_id(void) { - int apicid, cpuid; + u32 apicid; + int cpuid; =20 if (!boot_cpu_has(X86_FEATURE_APIC)) return 0; --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -500,13 +500,13 @@ static bool pv_sched_yield_supported(voi static void __send_ipi_mask(const struct cpumask *mask, int vector) { unsigned long flags; - int cpu, apic_id, icr; - int min =3D 0, max =3D 0; + int cpu, min =3D 0, max =3D 0; #ifdef CONFIG_X86_64 __uint128_t ipi_bitmap =3D 0; #else u64 ipi_bitmap =3D 0; #endif + u32 apic_id, icr; long ret; =20 if (cpumask_empty(mask)) @@ -1030,8 +1030,8 @@ arch_initcall(activate_jump_labels); /* Kick a cpu by its apicid. Used to wake up a halted vcpu */ static void kvm_kick_cpu(int cpu) { - int apicid; unsigned long flags =3D 0; + u32 apicid; =20 apicid =3D per_cpu(x86_cpu_to_apicid, cpu); kvm_hypercall2(KVM_HC_KICK_CPU, flags, apicid); --- a/arch/x86/mm/numa.c +++ b/arch/x86/mm/numa.c @@ -56,7 +56,7 @@ s16 __apicid_to_node[MAX_LOCAL_APIC] =3D { =20 int numa_cpu_node(int cpu) { - int apicid =3D early_per_cpu(x86_cpu_to_apicid, cpu); + u32 apicid =3D early_per_cpu(x86_cpu_to_apicid, cpu); =20 if (apicid !=3D BAD_APICID) return __apicid_to_node[apicid]; @@ -786,7 +786,7 @@ void __init init_gi_nodes(void) void __init init_cpu_to_node(void) { int cpu; - u16 *cpu_to_apicid =3D early_per_cpu_ptr(x86_cpu_to_apicid); + u32 *cpu_to_apicid =3D early_per_cpu_ptr(x86_cpu_to_apicid); =20 BUG_ON(cpu_to_apicid =3D=3D NULL); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8892DC04FE1 for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235074AbjHNIy7 (ORCPT ); Mon, 14 Aug 2023 04:54:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234953AbjHNIyB (ORCPT ); Mon, 14 Aug 2023 04:54:01 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 115D410B for ; Mon, 14 Aug 2023 01:54:01 -0700 (PDT) Message-ID: <20230814085112.981956102@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003239; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ziamZBTASNl2sFH0KVh93VbhwlbtdBcXmYqEKL7Hxj8=; b=PkLkFohf/fNeia304l0kzv2sDu58RFwyXCVX+0jc6tXfoUML77STHzaHuSGg+AGmVf6Lhl UcFIMj8t/rAgvoTtpsne2tgW25VmugdPfAIRI9LVbzPVsGOslt9s3YTOcG2Ddr1WlNckcq rIu3/Puska9uROKnyK4EJgt+0uMDdeXzJf19ONpIO6jxNEPkDrxjOXrBQjRDTjEhNo2sQW N2RS2t/pJNeUMbUHxX625za+MMIehlYcLfYR6FWinsZ8hABpg7icJw06GuIUmMl8mVxMR2 956EY/v8rQPFFXh1Zooet/v9khJmwra+r6UTszKT+KSBAbNHMQ3UV2A2ygP+OQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003239; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ziamZBTASNl2sFH0KVh93VbhwlbtdBcXmYqEKL7Hxj8=; b=zJryGnTmfF3L9cjCLZ68mnFRcqCDoPeoE6qMJ3u+7F/JEb4Jxxg8g33HZjFaCkHkB8dLzI rIXesLfQuvjeP8Cg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 16/41] x86/apic: Use u32 for check_apicid_used() References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:53:59 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width and move the default implementation to local.h as there are no users outside the apic directory. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Reviewed-by: Arjan van de Ven Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/apic.h | 3 +-- arch/x86/kernel/apic/apic_common.c | 2 +- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 2 ++ arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/local.h | 1 + 6 files changed, 6 insertions(+), 6 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -292,7 +292,7 @@ struct apic { int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); bool (*apic_id_registered)(void); =20 - bool (*check_apicid_used)(physid_mask_t *map, int apicid); + bool (*check_apicid_used)(physid_mask_t *map, u32 apicid); void (*init_apic_ldr)(void); void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap= ); int (*cpu_present_to_apicid)(int mps_cpu); @@ -538,7 +538,6 @@ extern int default_apic_id_valid(u32 api extern u32 apic_default_calc_apicid(unsigned int cpu); extern u32 apic_flat_calc_apicid(unsigned int cpu); =20 -extern bool default_check_apicid_used(physid_mask_t *map, int apicid); extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mas= k_t *retmap); extern int default_cpu_present_to_apicid(int mps_cpu); =20 --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -18,7 +18,7 @@ u32 apic_flat_calc_apicid(unsigned int c return 1U << cpu; } =20 -bool default_check_apicid_used(physid_mask_t *map, int apicid) +bool default_check_apicid_used(physid_mask_t *map, u32 apicid) { return physid_isset(apicid, *map); } --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -158,8 +158,6 @@ static struct apic apic_physflat __ro_af =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D NULL, - .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D flat_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -18,6 +18,8 @@ =20 #include =20 +#include "local.h" + static void noop_send_IPI(int cpu, int vector) { } static void noop_send_IPI_mask(const struct cpumask *cpumask, int vector) = { } static void noop_send_IPI_mask_allbutself(const struct cpumask *cpumask, i= nt vector) { } --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -18,7 +18,7 @@ static unsigned bigsmp_get_apic_id(unsig return (x >> 24) & 0xFF; } =20 -static bool bigsmp_check_apicid_used(physid_mask_t *map, int apicid) +static bool bigsmp_check_apicid_used(physid_mask_t *map, u32 apicid) { return false; } --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -64,6 +64,7 @@ void default_send_IPI_all(int vector); void default_send_IPI_self(int vector); =20 bool default_apic_id_registered(void); +bool default_check_apicid_used(physid_mask_t *map, u32 apicid); =20 #ifdef CONFIG_X86_32 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96FA6C04FE0 for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235099AbjHNIzC (ORCPT ); Mon, 14 Aug 2023 04:55:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234966AbjHNIyD (ORCPT ); Mon, 14 Aug 2023 04:54:03 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90FDA10C for ; Mon, 14 Aug 2023 01:54:02 -0700 (PDT) Message-ID: <20230814085113.054064391@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003241; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0PoVb6rqRl+3XDmFLX4OhuCpuMKU4+OQIAfP3H7EqAk=; b=NZ4I7uW72RvN4r52jupLg6yEbY/xeziDeEZ7d0VX5ovMT2oy70KGafFdmRSjVH9r4TPLiS 9ftDRVMHRn3mA2uunb8yBVMmW5d69q9Cb+Fw3Pbh/qENuRIr7Ckz2jBKVi1I+wZbDQ82Lf j01GlWAuzJxAtvlovi/94wQXYbtufy2Q/QOP1Z1zACnjYQtIeKCYZouMAkUhoBspXNv1u5 zVe4odVYPytqPU5QulPBs7QCMjAd+Ijns5hbeRdjxZv10HX9qkWrMMQhe6vL3A4mY0iYdu XL3oGe0y7tTdZLPMWBkuZWccI0pyWPLWKUEL9KUqqb4dCEE10v0KqjebNm5qyg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003241; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0PoVb6rqRl+3XDmFLX4OhuCpuMKU4+OQIAfP3H7EqAk=; b=PqMlJ9MHaYDJyJXoDogrDMo8iQLesd+Oaak3bL8C/fyi1ZktkoM7jV5lHKZia2BNpVSDwY THS71yiXWrEk76BQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 17/41] x86/apic: Use u32 for cpu_present_to_apicid() References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:00 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width and fixup a few related usage sites for consistency sake. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Reviewed-by: Arjan van de Ven Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/apic.h | 4 ++-- arch/x86/kernel/apic/apic_common.c | 2 +- arch/x86/kernel/cpu/common.c | 3 ++- arch/x86/kernel/smpboot.c | 10 +++++----- arch/x86/xen/apic.c | 2 +- 5 files changed, 11 insertions(+), 10 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -295,7 +295,7 @@ struct apic { bool (*check_apicid_used)(physid_mask_t *map, u32 apicid); void (*init_apic_ldr)(void); void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap= ); - int (*cpu_present_to_apicid)(int mps_cpu); + u32 (*cpu_present_to_apicid)(int mps_cpu); int (*phys_pkg_id)(int cpuid_apic, int index_msb); =20 u32 (*get_apic_id)(unsigned long x); @@ -539,7 +539,7 @@ extern u32 apic_default_calc_apicid(unsi extern u32 apic_flat_calc_apicid(unsigned int cpu); =20 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mas= k_t *retmap); -extern int default_cpu_present_to_apicid(int mps_cpu); +extern u32 default_cpu_present_to_apicid(int mps_cpu); =20 #else /* CONFIG_X86_LOCAL_APIC */ =20 --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -28,7 +28,7 @@ void default_ioapic_phys_id_map(physid_m *retmap =3D *phys_map; } =20 -int default_cpu_present_to_apicid(int mps_cpu) +u32 default_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) return (int)per_cpu(x86_cpu_to_apicid, mps_cpu); --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1747,7 +1747,8 @@ static void generic_identify(struct cpui static void validate_apic_and_package_id(struct cpuinfo_x86 *c) { #ifdef CONFIG_SMP - unsigned int apicid, cpu =3D smp_processor_id(); + unsigned int cpu =3D smp_processor_id(); + u32 apicid; =20 apicid =3D apic->cpu_present_to_apicid(cpu); =20 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -816,7 +816,7 @@ static void __init smp_quirk_init_udelay /* * Wake up AP by INIT, INIT, STARTUP sequence. */ -static void send_init_sequence(int phys_apicid) +static void send_init_sequence(u32 phys_apicid) { int maxlvt =3D lapic_get_maxlvt(); =20 @@ -842,7 +842,7 @@ static void send_init_sequence(int phys_ /* * Wake up AP by INIT, INIT, STARTUP sequence. */ -static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long st= art_eip) +static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long st= art_eip) { unsigned long send_status =3D 0, accept_status =3D 0; int num_starts, j, maxlvt; @@ -989,7 +989,7 @@ int common_cpu_up(unsigned int cpu, stru * Returns zero if startup was successfully sent, else error code from * ->wakeup_secondary_cpu. */ -static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) +static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle) { unsigned long start_ip =3D real_mode_header->trampoline_start; int ret; @@ -1057,7 +1057,7 @@ static int do_boot_cpu(int apicid, int c =20 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) { - int apicid =3D apic->cpu_present_to_apicid(cpu); + u32 apicid =3D apic->cpu_present_to_apicid(cpu); int err; =20 lockdep_assert_irqs_enabled(); @@ -1250,7 +1250,7 @@ void arch_thaw_secondary_cpus_end(void) bool smp_park_other_cpus_in_init(void) { unsigned int cpu, this_cpu =3D smp_processor_id(); - unsigned int apicid; + u32 apicid; =20 if (apic->wakeup_secondary_cpu_64 || apic->wakeup_secondary_cpu) return false; --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -115,7 +115,7 @@ static int xen_phys_pkg_id(int initial_a return initial_apic_id >> index_msb; } =20 -static int xen_cpu_present_to_apicid(int cpu) +static u32 xen_cpu_present_to_apicid(int cpu) { if (cpu_present(cpu)) return cpu_data(cpu).topo.apicid; From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAFE1C05052 for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235011AbjHNIzF (ORCPT ); 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003242; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=7SOzmaEyGyIDUT14N4JmbxJU+8tyxoAvV5vfItI8g6Q=; b=p0xIMa+LKqhP59qtSyqFfFUjqTQMvMKme/dnMH2u9SGwgtvkJfgFmdyuJe3P6M7IOStma2 coIICOov5P+2GGBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 18/41] x86/apic: Use u32 for phys_pkg_id() References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:02 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width even if that callback going to be removed soonish. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Reviewed-by: Arjan van de Ven Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/apic.h | 2 +- arch/x86/kernel/apic/apic_flat_64.c | 2 +- arch/x86/kernel/apic/apic_noop.c | 2 +- arch/x86/kernel/apic/apic_numachip.c | 2 +- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/local.h | 2 +- arch/x86/kernel/apic/probe_32.c | 2 +- arch/x86/kernel/apic/x2apic_phys.c | 2 +- arch/x86/kernel/apic/x2apic_uv_x.c | 2 +- arch/x86/kernel/vsmp_64.c | 2 +- arch/x86/xen/apic.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -296,7 +296,7 @@ struct apic { void (*init_apic_ldr)(void); void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap= ); u32 (*cpu_present_to_apicid)(int mps_cpu); - int (*phys_pkg_id)(int cpuid_apic, int index_msb); + u32 (*phys_pkg_id)(u32 cpuid_apic, int index_msb); =20 u32 (*get_apic_id)(unsigned long x); u32 (*set_apic_id)(unsigned int id); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -66,7 +66,7 @@ static u32 set_apic_id(unsigned int id) return (id & 0xFF) << 24; } =20 -static int flat_phys_pkg_id(int initial_apic_id, int index_msb) +static u32 flat_phys_pkg_id(u32 initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; } --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -29,7 +29,7 @@ static void noop_send_IPI_self(int vecto static void noop_apic_icr_write(u32 low, u32 id) { } static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) = { return -1; } static u64 noop_apic_icr_read(void) { return 0; } -static int noop_phys_pkg_id(int cpuid_apic, int index_msb) { return 0; } +static u32 noop_phys_pkg_id(u32 cpuid_apic, int index_msb) { return 0; } static unsigned int noop_get_apic_id(unsigned long x) { return 0; } static void noop_apic_eoi(void) { } =20 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -56,7 +56,7 @@ static u32 numachip2_set_apic_id(unsigne return id << 24; } =20 -static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) +static u32 numachip_phys_pkg_id(u32 initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; } --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -29,7 +29,7 @@ static void bigsmp_ioapic_phys_id_map(ph physids_promote(0xFFL, retmap); } =20 -static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb) +static u32 bigsmp_phys_pkg_id(u32 cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; } --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -17,7 +17,7 @@ void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); unsigned int x2apic_get_apic_id(unsigned long id); u32 x2apic_set_apic_id(unsigned int id); -int x2apic_phys_pkg_id(int initial_apicid, int index_msb); +u32 x2apic_phys_pkg_id(u32 initial_apicid, int index_msb); =20 void x2apic_send_IPI_all(int vector); void x2apic_send_IPI_allbutself(int vector); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -18,7 +18,7 @@ =20 #include "local.h" =20 -static int default_phys_pkg_id(int cpuid_apic, int index_msb) +static u32 default_phys_pkg_id(u32 cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; } --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -134,7 +134,7 @@ u32 x2apic_set_apic_id(unsigned int id) return id; } =20 -int x2apic_phys_pkg_id(int initial_apicid, int index_msb) +u32 x2apic_phys_pkg_id(u32 initial_apicid, int index_msb) { return initial_apicid >> index_msb; } --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -790,7 +790,7 @@ static unsigned int uv_read_apic_id(void return x2apic_get_apic_id(apic_read(APIC_ID)); } =20 -static int uv_phys_pkg_id(int initial_apicid, int index_msb) +static u32 uv_phys_pkg_id(u32 initial_apicid, int index_msb) { return uv_read_apic_id() >> index_msb; } --- a/arch/x86/kernel/vsmp_64.c +++ b/arch/x86/kernel/vsmp_64.c @@ -127,7 +127,7 @@ static void __init vsmp_cap_cpus(void) #endif } =20 -static int apicid_phys_pkg_id(int initial_apic_id, int index_msb) +static u32 apicid_phys_pkg_id(u32 initial_apic_id, int index_msb) { return read_apic_id() >> index_msb; } --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -110,7 +110,7 @@ static int xen_madt_oem_check(char *oem_ return xen_pv_domain(); } =20 -static int xen_phys_pkg_id(int initial_apic_id, int index_msb) +static u32 xen_phys_pkg_id(u32 initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B97E4C04FE2 for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235130AbjHNIzI (ORCPT ); Mon, 14 Aug 2023 04:55:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234976AbjHNIyG (ORCPT ); Mon, 14 Aug 2023 04:54:06 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC6E691 for ; Mon, 14 Aug 2023 01:54:05 -0700 (PDT) Message-ID: <20230814085113.172569282@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003244; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gW9alEQWPEWU1DZHmBBF2GJvXtvud6blUQ7THdfyYng=; b=ht9fRZC+V2h5fFPk4KD1nYyRtYl7ZJqyKJiuX0fbYlXyZ2QhyKTjfA31+qm9GVIsWREB67 3dJ7lHZuKYkzdosvzHG/FuXkq8xKcagSa5POPqZObeX+EGDSoL6P4qAuio2W4FtZLvXr+P JKwrmJYs2DadR84/+RUzws/kmGLZu8+I84FVHj1DqXoek9Z9gJocHRYZWUu9qbgpXQ+DR7 MoMHWixtfra2VrpGWtHRVD+GpBdE4I7g8nvhtSgVPY7BLEV8jb0qXn1bnsgtbnt7a3ZJMl 4zuFOmPZCwE11v+vw9oK72M33xzKKmEokuFbAVL5yLAU2Kig5NrifIh69rkC7g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003244; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gW9alEQWPEWU1DZHmBBF2GJvXtvud6blUQ7THdfyYng=; b=E8Ss5s41dy1YMQTZ1esgpzyVQDRZ+ntvpGoDy49OI7+i3oznUIHKCoYn+7GU08hbOzXhWg XwSsVuMSZOBqobCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 19/41] x86/apic: Use u32 for [gs]et_apic_id() References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:03 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/apic.h | 14 ++------------ arch/x86/kernel/apic/apic_flat_64.c | 4 ++-- arch/x86/kernel/apic/apic_noop.c | 2 +- arch/x86/kernel/apic/apic_numachip.c | 8 ++++---- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/local.h | 4 ++-- arch/x86/kernel/apic/probe_32.c | 10 ++++++++++ arch/x86/kernel/apic/x2apic_phys.c | 4 ++-- arch/x86/kernel/apic/x2apic_uv_x.c | 2 +- arch/x86/xen/apic.c | 4 ++-- 10 files changed, 27 insertions(+), 27 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -298,8 +298,8 @@ struct apic { u32 (*cpu_present_to_apicid)(int mps_cpu); u32 (*phys_pkg_id)(u32 cpuid_apic, int index_msb); =20 - u32 (*get_apic_id)(unsigned long x); - u32 (*set_apic_id)(unsigned int id); + u32 (*get_apic_id)(u32 id); + u32 (*set_apic_id)(u32 apicid); =20 /* wakeup_secondary_cpu */ int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); @@ -493,16 +493,6 @@ static inline bool lapic_vector_set_in_i return !!(irr & (1U << (vector % 32))); } =20 -static inline unsigned default_get_apic_id(unsigned long x) -{ - unsigned int ver =3D GET_APIC_VERSION(apic_read(APIC_LVR)); - - if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) - return (x >> 24) & 0xFF; - else - return (x >> 24) & 0x0F; -} - /* * Warm reset vector position: */ --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -56,12 +56,12 @@ flat_send_IPI_mask_allbutself(const stru _flat_send_IPI_mask(mask, vector); } =20 -static unsigned int flat_get_apic_id(unsigned long x) +static u32 flat_get_apic_id(u32 x) { return (x >> 24) & 0xFF; } =20 -static u32 set_apic_id(unsigned int id) +static u32 set_apic_id(u32 id) { return (id & 0xFF) << 24; } --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -30,7 +30,7 @@ static void noop_apic_icr_write(u32 low, static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) = { return -1; } static u64 noop_apic_icr_read(void) { return 0; } static u32 noop_phys_pkg_id(u32 cpuid_apic, int index_msb) { return 0; } -static unsigned int noop_get_apic_id(unsigned long x) { return 0; } +static u32 noop_get_apic_id(u32 apicid) { return 0; } static void noop_apic_eoi(void) { } =20 static u32 noop_apic_read(u32 reg) --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -25,7 +25,7 @@ static const struct apic apic_numachip1; static const struct apic apic_numachip2; static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __rea= d_mostly; =20 -static unsigned int numachip1_get_apic_id(unsigned long x) +static u32 numachip1_get_apic_id(u32 x) { unsigned long value; unsigned int id =3D (x >> 24) & 0xff; @@ -38,12 +38,12 @@ static unsigned int numachip1_get_apic_i return id; } =20 -static u32 numachip1_set_apic_id(unsigned int id) +static u32 numachip1_set_apic_id(u32 id) { return (id & 0xff) << 24; } =20 -static unsigned int numachip2_get_apic_id(unsigned long x) +static u32 numachip2_get_apic_id(u32 x) { u64 mcfg; =20 @@ -51,7 +51,7 @@ static unsigned int numachip2_get_apic_i return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24); } =20 -static u32 numachip2_set_apic_id(unsigned int id) +static u32 numachip2_set_apic_id(u32 id) { return id << 24; } --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -13,7 +13,7 @@ =20 #include "local.h" =20 -static unsigned bigsmp_get_apic_id(unsigned long x) +static u32 bigsmp_get_apic_id(u32 x) { return (x >> 24) & 0xFF; } --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -15,8 +15,8 @@ =20 /* X2APIC */ void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); -unsigned int x2apic_get_apic_id(unsigned long id); -u32 x2apic_set_apic_id(unsigned int id); +u32 x2apic_get_apic_id(u32 id); +u32 x2apic_set_apic_id(u32 id); u32 x2apic_phys_pkg_id(u32 initial_apicid, int index_msb); =20 void x2apic_send_IPI_all(int vector); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -23,6 +23,16 @@ static u32 default_phys_pkg_id(u32 cpuid return cpuid_apic >> index_msb; } =20 +static u32 default_get_apic_id(u32 x) +{ + unsigned int ver =3D GET_APIC_VERSION(apic_read(APIC_LVR)); + + if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) + return (x >> 24) & 0xFF; + else + return (x >> 24) & 0x0F; +} + /* should be called last. */ static int probe_default(void) { --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -124,12 +124,12 @@ static int x2apic_phys_probe(void) return apic =3D=3D &apic_x2apic_phys; } =20 -unsigned int x2apic_get_apic_id(unsigned long id) +u32 x2apic_get_apic_id(u32 id) { return id; } =20 -u32 x2apic_set_apic_id(unsigned int id) +u32 x2apic_set_apic_id(u32 id) { return id; } --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -780,7 +780,7 @@ static void uv_send_IPI_all(int vector) uv_send_IPI_mask(cpu_online_mask, vector); } =20 -static u32 set_apic_id(unsigned int id) +static u32 set_apic_id(u32 id) { return id; } --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -33,13 +33,13 @@ static unsigned int xen_io_apic_read(uns return 0xfd; } =20 -static u32 xen_set_apic_id(unsigned int x) +static u32 xen_set_apic_id(u32 x) { WARN_ON(1); return x; } =20 -static unsigned int xen_get_apic_id(unsigned long x) +static u32 xen_get_apic_id(u32 x) { return ((x)>>24) & 0xFFu; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7DBAC07E8A for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235155AbjHNIzK (ORCPT ); Mon, 14 Aug 2023 04:55:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234979AbjHNIyI (ORCPT ); Mon, 14 Aug 2023 04:54:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46FCB91 for ; Mon, 14 Aug 2023 01:54:07 -0700 (PDT) Message-ID: <20230814085113.233274223@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003246; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4Bp/IeizQpE2MMDElY3iKzSaIkRxvlWX5qBXFslYX0g=; b=pLnB0w7hIAHpTt5BKMcid51krlX77rpXcKGPWF56p+ShmIcmnFX1WSqpD26NcONLvirOpK GGHKs6TgIpQrpc9cYtGT2ETwba+fhWYbwCU52KhTLAmkGyE2imabTkm0Z/U8c7dcPgdz/z j1DY6imFujMuc9mBTdEICOICgH5EpObBcpOstMiYIWK34GmHT9KQKagW1lRS0sRBxpG5JE uYq0aOI3XWMYgfBRLl6qt7gDuMerxG+Xq1quaXpM5pvzF4JbNm700lSyaE36MisDGevimk My66cLPEo1NCXQFlpYnVrsKheJCSwij/juGeoM1yXOUWL9Ijtxg2t79sFglwCA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003246; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4Bp/IeizQpE2MMDElY3iKzSaIkRxvlWX5qBXFslYX0g=; b=D2u6A8euewKsV+MJQFzP370jp0itRSNxVuk9wH6ZqvTpr2MRX/umOkRiA1M/mMZzsC6DNG ZBw+CAS+xUpe/fAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 20/41] x86/apic: Use u32 for wakeup_secondary_cpu[_64]() References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:05 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" APIC IDs are used with random data types u16, u32, int, unsigned int, unsigned long. Make it all consistently use u32 because that reflects the hardware register width. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Reviewed-by: Arjan van de Ven Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/hyperv/hv_vtl.c | 2 +- arch/x86/include/asm/apic.h | 8 ++++---- arch/x86/kernel/acpi/boot.c | 2 +- arch/x86/kernel/apic/apic_noop.c | 2 +- arch/x86/kernel/apic/apic_numachip.c | 2 +- arch/x86/kernel/apic/x2apic_uv_x.c | 2 +- arch/x86/kernel/sev.c | 2 +- 7 files changed, 10 insertions(+), 10 deletions(-) --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -192,7 +192,7 @@ static int hv_vtl_apicid_to_vp_id(u32 ap return ret; } =20 -static int hv_vtl_wakeup_secondary_cpu(int apicid, unsigned long start_eip) +static int hv_vtl_wakeup_secondary_cpu(u32 apicid, unsigned long start_eip) { int vp_id; =20 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -302,9 +302,9 @@ struct apic { u32 (*set_apic_id)(u32 apicid); =20 /* wakeup_secondary_cpu */ - int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); + int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); /* wakeup secondary CPU using 64-bit wakeup point */ - int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); + int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip); =20 char *name; }; @@ -322,8 +322,8 @@ struct apic_override { void (*send_IPI_self)(int vector); u64 (*icr_read)(void); void (*icr_write)(u32 low, u32 high); - int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); - int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); + int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); + int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip); }; =20 /* --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -358,7 +358,7 @@ acpi_parse_lapic_nmi(union acpi_subtable } =20 #ifdef CONFIG_X86_64 -static int acpi_wakeup_cpu(int apicid, unsigned long start_ip) +static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) { /* * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -27,7 +27,7 @@ static void noop_send_IPI_allbutself(int static void noop_send_IPI_all(int vector) { } static void noop_send_IPI_self(int vector) { } static void noop_apic_icr_write(u32 low, u32 id) { } -static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) = { return -1; } +static int noop_wakeup_secondary_cpu(u32 apicid, unsigned long start_eip) = { return -1; } static u64 noop_apic_icr_read(void) { return 0; } static u32 noop_phys_pkg_id(u32 cpuid_apic, int index_msb) { return 0; } static u32 noop_get_apic_id(u32 apicid) { return 0; } --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -71,7 +71,7 @@ static void numachip2_apic_icr_write(int numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val); } =20 -static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_= rip) +static int numachip_wakeup_secondary(u32 phys_apicid, unsigned long start_= rip) { numachip_apic_icr_write(phys_apicid, APIC_DM_INIT); numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP | --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -702,7 +702,7 @@ static __init void build_uv_gr_table(voi } } =20 -static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) +static int uv_wakeup_secondary(u32 phys_apicid, unsigned long start_rip) { unsigned long val; int pnode; --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -940,7 +940,7 @@ static void snp_cleanup_vmsa(struct sev_ free_page((unsigned long)vmsa); } =20 -static int wakeup_cpu_via_vmgexit(int apic_id, unsigned long start_ip) +static int wakeup_cpu_via_vmgexit(u32 apic_id, unsigned long start_ip) { struct sev_es_save_area *cur_vmsa, *vmsa; struct ghcb_state state; From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D631AC0729B for ; Mon, 14 Aug 2023 08:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235194AbjHNIzN (ORCPT ); Mon, 14 Aug 2023 04:55:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234980AbjHNIyJ (ORCPT ); Mon, 14 Aug 2023 04:54:09 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD40C10B for ; Mon, 14 Aug 2023 01:54:08 -0700 (PDT) Message-ID: <20230814085113.292947071@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003247; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=77oFfcRh1dz2uih5llyqW8UL7n2yCgxBjdO2NZc4Y68=; b=qsnivYD0+xmerPdy98Wtnzybf4ZAAw9DNxH+tEtrcCN9T+3asRO4AN46sWtQzbIM9K+r41 hpUa5/GZ3gYPDFpHO6gXDIe5nbDwotehtBZ+HQOCWPbnhioqz3tD9pgz4Vn11uf0/VncM3 dLC5TKqnwt4jNHtn26p9WmivrMO5vpFd/lpjS8RkUs4BVmZeHt5/g1qHVO37G6MFG7Tb/b xrkgsdjNfuU7QG292fxlHm2B3gr8E6/jw/jHSf1bxtfe78letw1jxv7XU7ZlbIFS70pKAz 6Sp0rX2DGjXBnMA7mpIyFWSNwkJXm16fuT5gkR8de8AibjbMPp5o1thWJzNmwg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003247; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=77oFfcRh1dz2uih5llyqW8UL7n2yCgxBjdO2NZc4Y68=; b=hrTTYywU313iKWFC3zyAtgZXWOV7LL3VByT1vffPcCs1cydL+gi5Hhadkckk16MsphpwGD avZ6X6eYAAYA1ICQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 21/41] x86/cpu/topology: Cure the abuse of cpuinfo for persisting logical ids References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:07 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Per CPU cpuinfo is used to persist the logical package and die IDs. That's really not the right place simply because cpuinfo is subject to be reinitialized when a CPU goes through an offline/online cycle. This works by chance today, but that's far from correct and neither obvious nor documented. Add a per cpu datastructure which persists those logical IDs, which allows to cleanup the CPUID evaluation code. This is a temporary workaround until the larger topology management is in place, which makes all of this logical management mechanics obsolete. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/kernel/smpboot.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -124,7 +124,20 @@ struct mwait_cpu_dead { */ static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); =20 -/* Logical package management. We might want to allocate that dynamically = */ +/* Logical package management. */ +struct logical_maps { + u32 phys_pkg_id; + u32 phys_die_id; + u32 logical_pkg_id; + u32 logical_die_id; +}; + +/* Temporary workaround until the full topology mechanics is in place */ +static DEFINE_PER_CPU_READ_MOSTLY(struct logical_maps, logical_maps) =3D { + .phys_pkg_id =3D U32_MAX, + .phys_die_id =3D U32_MAX, +}; + unsigned int __max_logical_packages __read_mostly; EXPORT_SYMBOL(__max_logical_packages); static unsigned int logical_packages __read_mostly; @@ -345,10 +358,8 @@ int topology_phys_to_logical_pkg(unsigne int cpu; =20 for_each_possible_cpu(cpu) { - struct cpuinfo_x86 *c =3D &cpu_data(cpu); - - if (c->initialized && c->topo.pkg_id =3D=3D phys_pkg) - return c->topo.logical_pkg_id; + if (per_cpu(logical_maps.phys_pkg_id, cpu) =3D=3D phys_pkg) + return per_cpu(logical_maps.logical_pkg_id, cpu); } return -1; } @@ -366,11 +377,9 @@ static int topology_phys_to_logical_die( int cpu, proc_id =3D cpu_data(cur_cpu).topo.pkg_id; =20 for_each_possible_cpu(cpu) { - struct cpuinfo_x86 *c =3D &cpu_data(cpu); - - if (c->initialized && c->topo.die_id =3D=3D die_id && - c->topo.pkg_id =3D=3D proc_id) - return c->topo.logical_die_id; + if (per_cpu(logical_maps.phys_pkg_id, cpu) =3D=3D proc_id && + per_cpu(logical_maps.phys_die_id, cpu) =3D=3D die_id) + return per_cpu(logical_maps.logical_die_id, cpu); } return -1; } @@ -395,6 +404,8 @@ int topology_update_package_map(unsigned cpu, pkg, new); } found: + per_cpu(logical_maps.phys_pkg_id, cpu) =3D pkg; + per_cpu(logical_maps.logical_pkg_id, cpu) =3D new; cpu_data(cpu).topo.logical_pkg_id =3D new; return 0; } @@ -418,6 +429,8 @@ int topology_update_die_map(unsigned int cpu, die, new); } found: + per_cpu(logical_maps.phys_die_id, cpu) =3D die; + per_cpu(logical_maps.logical_die_id, cpu) =3D new; cpu_data(cpu).topo.logical_die_id =3D new; return 0; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 170FDEB64DD for ; Mon, 14 Aug 2023 08:56:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235336AbjHNIzj (ORCPT ); Mon, 14 Aug 2023 04:55:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234982AbjHNIyL (ORCPT ); Mon, 14 Aug 2023 04:54:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C8B010B for ; Mon, 14 Aug 2023 01:54:10 -0700 (PDT) Message-ID: <20230814085113.353191313@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003249; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gfUTIPblkGwpIS64sQCM323mDciLTw/qUO5rOF9RNNw=; b=fUo3gc3bicjahjrwsHlIeBYy5N7A+pacJrkOICkby8OeIU/00KC0wqCG+b3NaB/C2Vr6oW W27eUPqWJ5JcZOKDNP0s8DWHmWraDRt5HAJp2jwc+UIKUondGTexegwib/vbprGbcrf1dJ tVwIajA8fZjR6kyBPctdOeweY4ty5eP+ZF1wPQWdroxkVrmGXJmOCjqaMJZ+TL2moMbdzd ggI2MpmjvLiliEDpx+ek0Eddv5jF/S4YIcp/6upI/+/jgBCWTkYx92dyuCcBJm9ev5Iyzx bTszXIr60AH/sn9gMLSqLMrVuoO1sIxTro7FV+aA22U261dZlVCm8CzO2PoMFg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003249; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=gfUTIPblkGwpIS64sQCM323mDciLTw/qUO5rOF9RNNw=; b=w5vLvANhXTr2/wnHK5MAoq3iMaabpBZwNoUvYH530HZzoZMaLZRBXsSPXFnxzmXTF3ZjEq mhZJn6J/Wk5g26Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 22/41] x86/cpu: Provide debug interface References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:08 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide debug files which dump the topology related information of cpuinfo_x86. This is useful to validate the upcoming conversion of the topology evaluation for correctness or bug compatibility. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V2: Don't return ENODEV when offline and make online a field. --- arch/x86/kernel/cpu/Makefile | 2 + arch/x86/kernel/cpu/debugfs.c | 58 +++++++++++++++++++++++++++++++++++++= +++++ 2 files changed, 60 insertions(+) --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -54,6 +54,8 @@ obj-$(CONFIG_X86_LOCAL_APIC) +=3D perfctr obj-$(CONFIG_HYPERVISOR_GUEST) +=3D vmware.o hypervisor.o mshyperv.o obj-$(CONFIG_ACRN_GUEST) +=3D acrn.o =20 +obj-$(CONFIG_DEBUG_FS) +=3D debugfs.o + quiet_cmd_mkcapflags =3D MKCAP $@ cmd_mkcapflags =3D $(CONFIG_SHELL) $(srctree)/$(src)/mkcapflags.sh $= @ $^ =20 --- /dev/null +++ b/arch/x86/kernel/cpu/debugfs.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +#include +#include + +static int cpu_debug_show(struct seq_file *m, void *p) +{ + unsigned long cpu =3D (unsigned long)m->private; + struct cpuinfo_x86 *c =3D per_cpu_ptr(&cpu_info, cpu); + + seq_printf(m, "online: %d\n", cpu_online(cpu)); + if (!c->initialized) + return 0; + + seq_printf(m, "initial_apicid: %x\n", c->topo.initial_apicid); + seq_printf(m, "apicid: %x\n", c->topo.apicid); + seq_printf(m, "pkg_id: %u\n", c->topo.pkg_id); + seq_printf(m, "die_id: %u\n", c->topo.die_id); + seq_printf(m, "cu_id: %u\n", c->topo.cu_id); + seq_printf(m, "core_id: %u\n", c->topo.core_id); + seq_printf(m, "logical_pkg_id: %u\n", c->topo.logical_pkg_id); + seq_printf(m, "logical_die_id: %u\n", c->topo.logical_die_id); + seq_printf(m, "llc_id: %u\n", c->topo.llc_id); + seq_printf(m, "l2c_id: %u\n", c->topo.l2c_id); + seq_printf(m, "max_cores: %u\n", c->x86_max_cores); + seq_printf(m, "max_die_per_pkg: %u\n", __max_die_per_package); + seq_printf(m, "smp_num_siblings: %u\n", smp_num_siblings); + return 0; +} + +static int cpu_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, cpu_debug_show, inode->i_private); +} + +static const struct file_operations dfs_cpu_ops =3D { + .open =3D cpu_debug_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static __init int cpu_init_debugfs(void) +{ + struct dentry *dir, *base =3D debugfs_create_dir("topo", arch_debugfs_dir= ); + unsigned long id; + char name[10]; + + dir =3D debugfs_create_dir("cpus", base); + for_each_possible_cpu(id) { + sprintf(name, "%lu", id); + debugfs_create_file(name, 0444, dir, (void *)id, &dfs_cpu_ops); + } + return 0; +} +late_initcall(cpu_init_debugfs); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29AB2C04A94 for ; Mon, 14 Aug 2023 08:56:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235413AbjHNIzn (ORCPT ); Mon, 14 Aug 2023 04:55:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234445AbjHNIyM (ORCPT ); Mon, 14 Aug 2023 04:54:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E42BF10B for ; Mon, 14 Aug 2023 01:54:11 -0700 (PDT) Message-ID: <20230814085113.411614522@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003250; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XFu1uEQMDTgWTl5t42BMgLcsBElydD0EUbS0RHt1IKs=; b=XplJFTXNGfBaO6PFFHungwhGIvlRKMSOMb03RDfAQLUwt5SsrLY00NNv73oh6gJV6rNFIt rX0JzWimAdOIpXFglcvvg/7lpw8ELxv0dAc9i6Koebwc8RcQc1TgnuNo1t/DVRqUAwAK0X SGMdSs4Glf7YLgo23f3WSkj20PwzrPtHmgtph7p6JekbBfLa9EfXXtVgWxg2/nxNn97sKK 5saC5dCASwh9ZXdZwSCvWwos3wU1Y1uxBwzwyzF1cRnSJX66kLuDe5/JfILOrhyUaxNWD9 2w7JblcxEsNRkoG38DgcFZ0ztzMdLrAUxA5GzjMMN/X8FSZkZCRKLTM5DejKmg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003250; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XFu1uEQMDTgWTl5t42BMgLcsBElydD0EUbS0RHt1IKs=; b=O55RXWI5qQ1Z624gMZ104IUccXphm975qWRTv846R4JKAHB61LDqPHJohRfykt/A2YKM5l TbeVpeJbZfXdafCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 23/41] x86/cpu: Provide cpuid_read() et al. References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:10 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide a few helper functions to read CPUID leafs or individual registers into a data structure without requiring unions. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/cpuid.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) --- a/arch/x86/include/asm/cpuid.h +++ b/arch/x86/include/asm/cpuid.h @@ -127,6 +127,42 @@ static inline unsigned int cpuid_edx(uns return edx; } =20 +static inline void __cpuid_read(unsigned int leaf, unsigned int subleaf, u= 32 *regs) +{ + regs[CPUID_EAX] =3D leaf; + regs[CPUID_ECX] =3D subleaf; + __cpuid(regs, regs + 1, regs + 2, regs + 3); +} + +#define cpuid_subleaf(leaf, subleaf, regs) { \ + BUILD_BUG_ON(sizeof(*(regs)) !=3D 16); \ + __cpuid_read(leaf, subleaf, (u32 *)(regs)); \ +} + +#define cpuid_leaf(leaf, regs) { \ + BUILD_BUG_ON(sizeof(*(regs)) !=3D 16); \ + __cpuid_read(leaf, 0, (u32 *)(regs)); \ +} + +static inline void __cpuid_read_reg(unsigned int leaf, unsigned int sublea= f, + enum cpuid_regs_idx regidx, u32 *reg) +{ + u32 regs[4]; + + __cpuid_read(leaf, subleaf, regs); + *reg =3D regs[regidx]; +} + +#define cpuid_subleaf_reg(leaf, subleaf, regidx, reg) { \ + BUILD_BUG_ON(sizeof(*(reg)) !=3D 4); \ + __cpuid_read_reg(leaf, subleaf, regidx, (u32 *)(reg)); \ +} + +#define cpuid_leaf_reg(leaf, regidx, reg) { \ + BUILD_BUG_ON(sizeof(*(reg)) !=3D 4); \ + __cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg)); \ +} + static __always_inline bool cpuid_function_is_indexed(u32 function) { switch (function) { From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D61FC04E69 for ; Mon, 14 Aug 2023 08:56:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235469AbjHNIz4 (ORCPT ); Mon, 14 Aug 2023 04:55:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235030AbjHNIyQ (ORCPT ); Mon, 14 Aug 2023 04:54:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BB6310D for ; Mon, 14 Aug 2023 01:54:13 -0700 (PDT) Message-ID: <20230814085113.471353147@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003252; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3e4YyZPBZON8eZ6TcEOpoEAsfB5JVs+EpGnEo3+YWbk=; b=m0i+XuG0e7dT/O5UVMfdNDMOImfXI2uo0/xJqoEoOs5FPAm8mnxUp6eQn9RMjGfRb3nWLC +De2qjEgaW/ixVy3GTJ4ZZcKLQF+glsO3xvz0dK1QeotgCy9Jd7JgjGtWPm5PAjFsCoFNL MG2ZhpGKVffcErwk38Mfyc8gtYSCXMIjjLfNTEFH3F4jefgfAHKb9OzL2+hI8I7eShfXMZ Obj9hnCCLT5kpavrB2sC5uQQE8Cprd8PlU7ObxWa/hWuHv2Y1yu/yYXP5J0msCZr3hRr1U 6/2r4batcO/Xe1oMOvmfrfqYfmAurMXjse+cR/o2STvjt7SMXxS1omTSRhsbtg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003252; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3e4YyZPBZON8eZ6TcEOpoEAsfB5JVs+EpGnEo3+YWbk=; b=e6Akx8v9oCXizkJKqhXrXjx2OiXijP+0zffNMVjTGfbwfentkJVgz24QCD0Y2bAfeHPp5c VX4OaRAbIaEWw+BA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 24/41] x86/cpu: Provide cpu_init/parse_topology() References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:11 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Topology evaluation is a complete disaster and impenetrable mess. It's scattered all over the place with some vendor implementations doing early evaluation and some not. The most horrific part is the permanent overwriting of smt_max_siblings and __max_die_per_package, instead of establishing them once on the boot CPU and validating the result on the APs. The goals are: - One topology evaluation entry point - Proper sharing of pointlessly duplicated code - Proper structuring of the evaluation logic and preferences. - Evaluating important system wide information only once on the boot CPU - Making the 0xb/0x1f leaf parsing less convoluted and actually fixing the short comings of leaf 0x1f evaluation. Start to consolidate the topology evaluation code by providing the entry points for the early boot CPU evaluation and for the final parsing on the boot CPU and the APs. Move the trivial pieces into that new code: - The initialization of cpuinfo_x86::topo - The evaluation of CPUID leaf 1, which presets topo::initial_apicid - topo_apicid is set to topo::initial_apicid when invoked from early boot. When invoked for the final evaluation on the boot CPU it reads the actual APIC ID, which makes apic_get_initial_apicid() obsolete once everything is converted over. Provide a temporary helper function topo_converted() which shields off the not yet converted CPU vendors from invoking code which would break them. This shielding covers all vendor CPUs which support SMP, but not the historical pure UP ones as they only need the topology info init and eventually the initial APIC initialization. Provide two new members in cpuinfo_x86::topo to store the maximum number of SMT siblings and the number of dies per package and add them to the debugfs readout. These two members will be used to populate this information on the boot CPU and to validate the APs against it. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V2: Make core ID package relativ not relative to the next level - Rui --- arch/x86/include/asm/topology.h | 19 +++ arch/x86/kernel/cpu/Makefile | 3=20 arch/x86/kernel/cpu/common.c | 23 +--- arch/x86/kernel/cpu/cpu.h | 6 + arch/x86/kernel/cpu/debugfs.c | 37 ++++++ arch/x86/kernel/cpu/topology.h | 36 ++++++ arch/x86/kernel/cpu/topology_common.c | 188 +++++++++++++++++++++++++++++= +++++ 7 files changed, 295 insertions(+), 17 deletions(-) --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -102,6 +102,25 @@ static inline void setup_node_to_cpumask =20 #include =20 +/* Topology information */ +enum x86_topology_domains { + TOPO_SMT_DOMAIN, + TOPO_CORE_DOMAIN, + TOPO_MODULE_DOMAIN, + TOPO_TILE_DOMAIN, + TOPO_DIE_DOMAIN, + TOPO_PKG_DOMAIN, + TOPO_ROOT_DOMAIN, + TOPO_MAX_DOMAIN, +}; + +struct x86_topology_system { + unsigned int dom_shifts[TOPO_MAX_DOMAIN]; + unsigned int dom_size[TOPO_MAX_DOMAIN]; +}; + +extern struct x86_topology_system x86_topo_system; + extern const struct cpumask *cpu_coregroup_mask(int cpu); extern const struct cpumask *cpu_clustergroup_mask(int cpu); =20 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -17,7 +17,8 @@ KMSAN_SANITIZE_common.o :=3D n # As above, instrumenting secondary CPU boot code causes boot hangs. KCSAN_SANITIZE_common.o :=3D n =20 -obj-y :=3D cacheinfo.o scattered.o topology.o +obj-y :=3D cacheinfo.o scattered.o +obj-y +=3D topology_common.o topology.o obj-y +=3D common.o obj-y +=3D rdrand.o obj-y +=3D match.o --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1553,6 +1553,8 @@ static void __init early_identify_cpu(st setup_force_cpu_cap(X86_FEATURE_CPUID); cpu_parse_early_param(); =20 + cpu_init_topology(c); + if (this_cpu->c_early_init) this_cpu->c_early_init(c); =20 @@ -1563,6 +1565,7 @@ static void __init early_identify_cpu(st this_cpu->c_bsp_init(c); } else { setup_clear_cpu_cap(X86_FEATURE_CPUID); + cpu_init_topology(c); } =20 setup_force_cpu_cap(X86_FEATURE_ALWAYS); @@ -1708,18 +1711,6 @@ static void generic_identify(struct cpui =20 get_cpu_address_sizes(c); =20 - if (c->cpuid_level >=3D 0x00000001) { - c->topo.initial_apicid =3D (cpuid_ebx(1) >> 24) & 0xFF; -#ifdef CONFIG_X86_32 -# ifdef CONFIG_SMP - c->topo.apicid =3D apic->phys_pkg_id(c->topo.initial_apicid, 0); -# else - c->topo.apicid =3D c->topo.initial_apicid; -# endif -#endif - c->topo.pkg_id =3D c->topo.initial_apicid; - } - get_model_name(c); /* Default name */ =20 /* @@ -1778,9 +1769,6 @@ static void identify_cpu(struct cpuinfo_ c->x86_model_id[0] =3D '\0'; /* Unset */ c->x86_max_cores =3D 1; c->x86_coreid_bits =3D 0; - c->topo.cu_id =3D 0xff; - c->topo.llc_id =3D BAD_APICID; - c->topo.l2c_id =3D BAD_APICID; #ifdef CONFIG_X86_64 c->x86_clflush_size =3D 64; c->x86_phys_bits =3D 36; @@ -1799,6 +1787,8 @@ static void identify_cpu(struct cpuinfo_ =20 generic_identify(c); =20 + cpu_parse_topology(c); + if (this_cpu->c_identify) this_cpu->c_identify(c); =20 @@ -1806,7 +1796,8 @@ static void identify_cpu(struct cpuinfo_ apply_forced_caps(c); =20 #ifdef CONFIG_X86_64 - c->topo.apicid =3D apic->phys_pkg_id(c->topo.initial_apicid, 0); + if (!topo_is_converted(c)) + c->topo.apicid =3D apic->phys_pkg_id(c->topo.initial_apicid, 0); #endif =20 /* --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -2,6 +2,11 @@ #ifndef ARCH_X86_CPU_H #define ARCH_X86_CPU_H =20 +#include +#include + +#include "topology.h" + /* attempt to consolidate cpu attributes */ struct cpu_dev { const char *c_vendor; @@ -95,4 +100,5 @@ static inline bool spectre_v2_in_eibrs_m mode =3D=3D SPECTRE_V2_EIBRS_RETPOLINE || mode =3D=3D SPECTRE_V2_EIBRS_LFENCE; } + #endif /* ARCH_X86_CPU_H */ --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -5,6 +5,8 @@ #include #include =20 +#include "cpu.h" + static int cpu_debug_show(struct seq_file *m, void *p) { unsigned long cpu =3D (unsigned long)m->private; @@ -42,12 +44,47 @@ static const struct file_operations dfs_ .release =3D single_release, }; =20 +static int dom_debug_show(struct seq_file *m, void *p) +{ + static const char *domain_names[TOPO_ROOT_DOMAIN] =3D { + [TOPO_SMT_DOMAIN] =3D "Thread", + [TOPO_CORE_DOMAIN] =3D "Core", + [TOPO_MODULE_DOMAIN] =3D "Module", + [TOPO_TILE_DOMAIN] =3D "Tile", + [TOPO_DIE_DOMAIN] =3D "Die", + [TOPO_PKG_DOMAIN] =3D "Package", + }; + unsigned int dom, nthreads =3D 1; + + for (dom =3D 0; dom < TOPO_ROOT_DOMAIN; dom++) { + nthreads *=3D x86_topo_system.dom_size[dom]; + seq_printf(m, "domain: %-10s shift: %u dom_size: %5u max_threads: %5u\n", + domain_names[dom], x86_topo_system.dom_shifts[dom], + x86_topo_system.dom_size[dom], nthreads); + } + return 0; +} + +static int dom_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, dom_debug_show, inode->i_private); +} + +static const struct file_operations dfs_dom_ops =3D { + .open =3D dom_debug_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + static __init int cpu_init_debugfs(void) { struct dentry *dir, *base =3D debugfs_create_dir("topo", arch_debugfs_dir= ); unsigned long id; char name[10]; =20 + debugfs_create_file("domains", 0444, base, NULL, &dfs_dom_ops); + dir =3D debugfs_create_dir("cpus", base); for_each_possible_cpu(id) { sprintf(name, "%lu", id); --- /dev/null +++ b/arch/x86/kernel/cpu/topology.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef ARCH_X86_TOPOLOGY_H +#define ARCH_X86_TOPOLOGY_H + +struct topo_scan { + struct cpuinfo_x86 *c; + unsigned int dom_shifts[TOPO_MAX_DOMAIN]; + unsigned int dom_ncpus[TOPO_MAX_DOMAIN]; +}; + +bool topo_is_converted(struct cpuinfo_x86 *c); +void cpu_init_topology(struct cpuinfo_x86 *c); +void cpu_parse_topology(struct cpuinfo_x86 *c); +void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains d= om, + unsigned int shift, unsigned int ncpus); + +static inline u32 topo_shift_apicid(u32 apicid, enum x86_topology_domains = dom) +{ + if (dom =3D=3D TOPO_SMT_DOMAIN) + return apicid; + return apicid >> x86_topo_system.dom_shifts[dom - 1]; +} + +static inline u32 topo_relative_domain_id(u32 apicid, enum x86_topology_do= mains dom) +{ + if (dom !=3D TOPO_SMT_DOMAIN) + apicid >>=3D x86_topo_system.dom_shifts[dom - 1]; + return apicid & (x86_topo_system.dom_size[dom] - 1); +} + +static inline u32 topo_domain_mask(enum x86_topology_domains dom) +{ + return (1U << x86_topo_system.dom_shifts[dom]) - 1; +} + +#endif /* ARCH_X86_TOPOLOGY_H */ --- /dev/null +++ b/arch/x86/kernel/cpu/topology_common.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +#include + +#include +#include +#include + +#include "cpu.h" + +struct x86_topology_system x86_topo_system __ro_after_init; + +void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains d= om, + unsigned int shift, unsigned int ncpus) +{ + tscan->dom_shifts[dom] =3D shift; + tscan->dom_ncpus[dom] =3D ncpus; + + /* Propagate to the upper levels */ + for (dom++; dom < TOPO_MAX_DOMAIN; dom++) { + tscan->dom_shifts[dom] =3D tscan->dom_shifts[dom - 1]; + tscan->dom_ncpus[dom] =3D tscan->dom_ncpus[dom - 1]; + } +} + +bool topo_is_converted(struct cpuinfo_x86 *c) +{ + /* Temporary until everything is converted over. */ + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_AMD: + case X86_VENDOR_CENTAUR: + case X86_VENDOR_INTEL: + case X86_VENDOR_HYGON: + case X86_VENDOR_ZHAOXIN: + return false; + default: + /* Let all UP systems use the below */ + return true; + } +} + +static bool fake_topology(struct topo_scan *tscan) +{ + /* + * Preset the CORE level shift for CPUID less systems and XEN_PV, + * which has useless CPUID information. + */ + topology_set_dom(tscan, TOPO_SMT_DOMAIN, 0, 1); + topology_set_dom(tscan, TOPO_CORE_DOMAIN, 1, 1); + + return tscan->c->cpuid_level < 1 || xen_pv_domain(); +} + +static void parse_topology(struct topo_scan *tscan, bool early) +{ + const struct cpuinfo_topology topo_defaults =3D { + .cu_id =3D 0xff, + .llc_id =3D BAD_APICID, + .l2c_id =3D BAD_APICID, + }; + struct cpuinfo_x86 *c =3D tscan->c; + struct { + u32 unused0 : 16, + nproc : 8, + apicid : 8; + } ebx; + + c->topo =3D topo_defaults; + + if (fake_topology(tscan)) + return; + + /* Preset Initial APIC ID from CPUID leaf 1 */ + cpuid_leaf_reg(1, CPUID_EBX, &ebx); + c->topo.initial_apicid =3D ebx.apicid; + + /* + * The initial invocation from early_identify_cpu() happens before + * the APIC is mapped or X2APIC enabled. For establishing the + * topology, that's not required. Use the initial APIC ID. + */ + if (early) + c->topo.apicid =3D c->topo.initial_apicid; + else + c->topo.apicid =3D read_apic_id(); + + /* The above is sufficient for UP */ + if (!IS_ENABLED(CONFIG_SMP)) + return; +} + +static void topo_set_ids(struct topo_scan *tscan) +{ + struct cpuinfo_x86 *c =3D tscan->c; + u32 apicid =3D c->topo.apicid; + + c->topo.pkg_id =3D topo_shift_apicid(apicid, TOPO_PKG_DOMAIN); + c->topo.die_id =3D topo_shift_apicid(apicid, TOPO_DIE_DOMAIN); + + /* Package relative core ID */ + c->topo.core_id =3D (apicid & topo_domain_mask(TOPO_PKG_DOMAIN)) >> + x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; +} + +static void topo_set_max_cores(struct topo_scan *tscan) +{ + /* + * Bug compatible for now. This is broken on hybrid systems: + * 8 cores SMT + 8 cores w/o SMT + * tscan.dom_ncpus[TOPO_CORE_DOMAIN] =3D 24; 24 / 2 =3D 12 !! + * + * Cannot be fixed without further topology enumeration changes. + */ + tscan->c->x86_max_cores =3D tscan->dom_ncpus[TOPO_CORE_DOMAIN] >> + x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; +} + +void cpu_parse_topology(struct cpuinfo_x86 *c) +{ + unsigned int dom, cpu =3D smp_processor_id(); + struct topo_scan tscan =3D { .c =3D c, }; + + parse_topology(&tscan, false); + + if (!topo_is_converted(c)) + return; + + for (dom =3D TOPO_SMT_DOMAIN; dom < TOPO_MAX_DOMAIN; dom++) { + if (tscan.dom_shifts[dom] =3D=3D x86_topo_system.dom_shifts[dom]) + continue; + pr_err(FW_BUG "CPU%d: Topology domain %u shift %u !=3D %u\n", cpu, dom, + tscan.dom_shifts[dom], x86_topo_system.dom_shifts[dom]); + } + + /* Bug compatible with the existing parsers */ + if (tscan.dom_ncpus[TOPO_SMT_DOMAIN] > smp_num_siblings) { + if (system_state =3D=3D SYSTEM_BOOTING) { + pr_warn_once("CPU%d: SMT detected and enabled late\n", cpu); + smp_num_siblings =3D tscan.dom_ncpus[TOPO_SMT_DOMAIN]; + } else { + pr_warn_once("CPU%d: SMT detected after init. Too late!\n", cpu); + } + } + + topo_set_ids(&tscan); + topo_set_max_cores(&tscan); +} + +void __init cpu_init_topology(struct cpuinfo_x86 *c) +{ + struct topo_scan tscan =3D { .c =3D c, }; + unsigned int dom, sft; + + parse_topology(&tscan, true); + + if (!topo_is_converted(c)) + return; + + /* Copy the shift values and calculate the unit sizes. */ + memcpy(x86_topo_system.dom_shifts, tscan.dom_shifts, sizeof(x86_topo_syst= em.dom_shifts)); + + dom =3D TOPO_SMT_DOMAIN; + x86_topo_system.dom_size[dom] =3D 1U << x86_topo_system.dom_shifts[dom]; + + for (dom++; dom < TOPO_MAX_DOMAIN; dom++) { + sft =3D x86_topo_system.dom_shifts[dom] - x86_topo_system.dom_shifts[dom= - 1]; + x86_topo_system.dom_size[dom] =3D 1U << sft; + } + + topo_set_ids(&tscan); + topo_set_max_cores(&tscan); + + /* + * Bug compatible with the existing code. If the boot CPU does not + * have SMT this ends up with one sibling. This needs way deeper + * changes further down the road to get it right during early boot. + */ + smp_num_siblings =3D tscan.dom_ncpus[TOPO_SMT_DOMAIN]; + + /* + * Neither it's clear whether there are as many dies as the APIC + * space indicating die level is. But assume that the actual number + * of CPUs gives a proper indication for now to stay bug compatible. + */ + __max_die_per_package =3D tscan.dom_ncpus[TOPO_DIE_DOMAIN] / + tscan.dom_ncpus[TOPO_DIE_DOMAIN - 1]; +} From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DFCFC41513 for ; Mon, 14 Aug 2023 08:56:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235425AbjHNIzr (ORCPT ); Mon, 14 Aug 2023 04:55:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235029AbjHNIyQ (ORCPT ); Mon, 14 Aug 2023 04:54:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1223612D for ; Mon, 14 Aug 2023 01:54:15 -0700 (PDT) Message-ID: <20230814085113.530288551@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003253; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=n2JIWQXMZsDripo49SW/KKqhdAhpMEcxQ76bjpW2vPI=; b=a/wx3tb/04GRjqTfTs+AIbluSHJlG7IKJxT8UWZDmO3bx0KwVoJqN9XCqexV7ZGbVqj/eV 2jvV2JSktuK5H2A63+89bZHxjgc7ouirVWyaRFLx/J1C+6nN0hfpqW4xYzrT0FSbKEhqbk XwVra01v3/RDbQfmb4dHuU7Yvd1bGLA/F9eyJbTIc3xjGDsmgzhiduz7QgLLeg/gqdCual 3B9h6/1pgmgcjN8B84cdHePWd3m6eNKQRajccf2JnMs1r3diWdAcLEvZKrQAvdQBYIQW+W xAMKng5QDIC9oLa/wA+MOm38Gphz6LHykZ7VYVj6X7Sc5k2dqNcV851UXNzjTQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003253; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=n2JIWQXMZsDripo49SW/KKqhdAhpMEcxQ76bjpW2vPI=; b=Yab2ugCEn/xohHyMI2ZZi1wKA5RHPbIT1HMHEDaClMRJhQs0BUipACWeDiFR82hlUpWSFo PXztzKmbfydVQECw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 25/41] x86/cpu: Add legacy topology parser References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:13 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The legacy topology detection via CPUID leaf 4, which provides the number of cores in the package and CPUID leaf 1 which provides the number of logical CPUs in case that FEATURE_HT is enabled and the CMP_LEGACY feature is not set, is shared for Intel, Centaur amd Zhaoxin CPUs. Lift the code from common.c without the early detection hack and provide it as common fallback mechanism. Will be utilized in later changes. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V4: Cure the off by one in fake_topology() V3: Provide legacy data in leaf 0xb/0x1f format as expected by the rest of the code - Borislav --- arch/x86/kernel/cpu/common.c | 3 ++ arch/x86/kernel/cpu/topology.h | 3 ++ arch/x86/kernel/cpu/topology_common.c | 46 +++++++++++++++++++++++++++++= ++++- 3 files changed, 51 insertions(+), 1 deletion(-) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -883,6 +883,9 @@ void detect_ht(struct cpuinfo_x86 *c) #ifdef CONFIG_SMP int index_msb, core_bits; =20 + if (topo_is_converted(c)) + return; + if (detect_ht_early(c) < 0) return; =20 --- a/arch/x86/kernel/cpu/topology.h +++ b/arch/x86/kernel/cpu/topology.h @@ -6,6 +6,9 @@ struct topo_scan { struct cpuinfo_x86 *c; unsigned int dom_shifts[TOPO_MAX_DOMAIN]; unsigned int dom_ncpus[TOPO_MAX_DOMAIN]; + + // Legacy CPUID[1]:EBX[23:16] number of logical processors + unsigned int ebx1_nproc_shift; }; =20 bool topo_is_converted(struct cpuinfo_x86 *c); --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -24,6 +24,48 @@ void topology_set_dom(struct topo_scan * } } =20 +static unsigned int parse_num_cores(struct cpuinfo_x86 *c) +{ + struct { + u32 cache_type : 5, + unused : 21, + ncores : 6; + } eax; + + if (c->cpuid_level < 4) + return 1; + + cpuid_subleaf_reg(4, 0, CPUID_EAX, &eax); + if (!eax.cache_type) + return 1; + + return eax.ncores + 1; +} + +static void __maybe_unused parse_legacy(struct topo_scan *tscan) +{ + unsigned int cores, core_shift, smt_shift =3D 0; + struct cpuinfo_x86 *c =3D tscan->c; + + cores =3D parse_num_cores(c); + core_shift =3D get_count_order(cores); + + if (cpu_has(c, X86_FEATURE_HT)) { + if (!WARN_ON_ONCE(tscan->ebx1_nproc_shift < core_shift)) + smt_shift =3D tscan->ebx1_nproc_shift - core_shift; + /* + * The parser expects leaf 0xb/0x1f format, which means + * the number of logical processors at core level is + * counting threads. + */ + core_shift +=3D smt_shift; + cores <<=3D smt_shift; + } + + topology_set_dom(tscan, TOPO_SMT_DOMAIN, smt_shift, 1U << smt_shift); + topology_set_dom(tscan, TOPO_CORE_DOMAIN, core_shift, cores); +} + bool topo_is_converted(struct cpuinfo_x86 *c) { /* Temporary until everything is converted over. */ @@ -47,7 +89,7 @@ static bool fake_topology(struct topo_sc * which has useless CPUID information. */ topology_set_dom(tscan, TOPO_SMT_DOMAIN, 0, 1); - topology_set_dom(tscan, TOPO_CORE_DOMAIN, 1, 1); + topology_set_dom(tscan, TOPO_CORE_DOMAIN, 0, 1); =20 return tscan->c->cpuid_level < 1 || xen_pv_domain(); } @@ -88,6 +130,8 @@ static void parse_topology(struct topo_s /* The above is sufficient for UP */ if (!IS_ENABLED(CONFIG_SMP)) return; + + tscan->ebx1_nproc_shift =3D get_count_order(ebx.nproc); } =20 static void topo_set_ids(struct topo_scan *tscan) From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E13FC001B0 for ; Mon, 14 Aug 2023 08:56:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235545AbjHNIzv (ORCPT ); Mon, 14 Aug 2023 04:55:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235058AbjHNIyR (ORCPT ); Mon, 14 Aug 2023 04:54:17 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4C6E1AA for ; Mon, 14 Aug 2023 01:54:16 -0700 (PDT) Message-ID: <20230814085113.588701843@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003255; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZG/EXWy0RVlNB1gv0Rdu33CQfwetyGKKBsf9BNZ5Uv8=; b=b2Y6JEYF0l284Ztmnc80j+qjT1TvPV0OZJ7eMMqmJgrEwA3l6JIdDLaDda0kCCVNc00au8 2lF0gryQohsuCy8D16IadCY1UlOznUNIzF+KvESr2i4t5lHhiokmg+SpDAhgVB79+ltYPi yNnUmR8HuSFkQJVoU4omBUefExeoAyH4sCHcTNOAXG1jfutwzapAVE8v9RQlMkYgcdejiJ SLL0UTGdwbV7r3pdrf3/aSaj4ydsBVOjsIbplh3LTLnDoEbyNGoGhObGdTwGLB1GzM9Ep2 WJeP6mt9oKsyHgj39AqcCdz44cj1g8M1WkQbviZ0XVZ+c0/XTWBHiVnDu+/e5A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003255; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZG/EXWy0RVlNB1gv0Rdu33CQfwetyGKKBsf9BNZ5Uv8=; b=FuoYBzBPQZGyooNROspFQLk1jl1Gjrm5mC44rctA6htSZPfctejwAY7R8X5BfllugOI0v7 xAM2PncP1FMMefCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 26/41] x86/cpu: Use common topology code for Centaur and Zhaoxin References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:14 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Centaur and Zhaoxin CPUs use only the legacy SMP detection. Remove the invocations from their 32bit path and exempt them from the call 64bit. No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/kernel/cpu/centaur.c | 4 ---- arch/x86/kernel/cpu/topology_common.c | 11 ++++++++--- arch/x86/kernel/cpu/zhaoxin.c | 4 ---- 3 files changed, 8 insertions(+), 11 deletions(-) --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -128,10 +128,6 @@ static void init_centaur(struct cpuinfo_ #endif early_init_centaur(c); init_intel_cacheinfo(c); - detect_num_cpu_cores(c); -#ifdef CONFIG_X86_32 - detect_ht(c); -#endif =20 if (c->cpuid_level > 9) { unsigned int eax =3D cpuid_eax(10); --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -42,7 +42,7 @@ static unsigned int parse_num_cores(stru return eax.ncores + 1; } =20 -static void __maybe_unused parse_legacy(struct topo_scan *tscan) +static void parse_legacy(struct topo_scan *tscan) { unsigned int cores, core_shift, smt_shift =3D 0; struct cpuinfo_x86 *c =3D tscan->c; @@ -71,10 +71,8 @@ bool topo_is_converted(struct cpuinfo_x8 /* Temporary until everything is converted over. */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - case X86_VENDOR_CENTAUR: case X86_VENDOR_INTEL: case X86_VENDOR_HYGON: - case X86_VENDOR_ZHAOXIN: return false; default: /* Let all UP systems use the below */ @@ -132,6 +130,13 @@ static void parse_topology(struct topo_s return; =20 tscan->ebx1_nproc_shift =3D get_count_order(ebx.nproc); + + switch (c->x86_vendor) { + case X86_VENDOR_CENTAUR: + case X86_VENDOR_ZHAOXIN: + parse_legacy(tscan); + break; + } } =20 static void topo_set_ids(struct topo_scan *tscan) --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -71,10 +71,6 @@ static void init_zhaoxin(struct cpuinfo_ { early_init_zhaoxin(c); init_intel_cacheinfo(c); - detect_num_cpu_cores(c); -#ifdef CONFIG_X86_32 - detect_ht(c); -#endif =20 if (c->cpuid_level > 9) { unsigned int eax =3D cpuid_eax(10); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83EB7C04FDF for ; Mon, 14 Aug 2023 08:56:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235205AbjHNI4A (ORCPT ); Mon, 14 Aug 2023 04:56:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234862AbjHNIyT (ORCPT ); Mon, 14 Aug 2023 04:54:19 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 695F51AA for ; Mon, 14 Aug 2023 01:54:18 -0700 (PDT) Message-ID: <20230814085113.646802453@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003256; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=hGG18YRpAzYxpKTnwH+uiIi5fZmUPp4aoRZn/mz3oxM=; b=UUYvQhLGJ6lL+hVqyH0uLzifGsuHpLWV5WLTrOxoxplN9w4vxb+J/Kb8Z6aABnoZJsuQ1k xCjkO9P1cyj7ygc8QmIOq2Gfk0EmlO6984UcntvOsmEKuriq/0IxNkGMRBtcN8vQwAeHKZ xLUnSQ/U4WHtkPYHz+/F6Vk5RrnqjKbHQCcVdDO3nBcQFe4MxuW9zyG89pI4WtxyAKJduv f6nsVDTAIv19lwp17ceeHv9k4kijfmNDf503rumbEzr3chfvQcxWR08SHYq4AV32cSIzA4 gFSq4kTgKYKGvTbXN5E2YqyuuWEcAxpRkPiowUn68ehiPqx4fDwJDXNDOFZZVQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003256; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=hGG18YRpAzYxpKTnwH+uiIi5fZmUPp4aoRZn/mz3oxM=; b=5HpOfSb2ftYMCvkwTLtvn7F/YzsGinTG3ZYP0XQJlKsa1j1PTuBDstXsvq4yOsbSAtnzci 3iWS3gNDntyx1ECQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 27/41] x86/cpu: Move __max_die_per_package to common.c References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:16 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation of a complete replacement for the topology leaf 0xb/0x1f evaluation, move __max_die_per_package into the common code. Will be removed once everything is converted over. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kernel/cpu/topology.c | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -75,6 +75,9 @@ u32 elf_hwcap2 __read_mostly; int smp_num_siblings =3D 1; EXPORT_SYMBOL(smp_num_siblings); =20 +unsigned int __max_die_per_package __read_mostly =3D 1; +EXPORT_SYMBOL(__max_die_per_package); + static struct ppin_info { int feature; int msr_ppin_ctl; --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -25,9 +25,6 @@ #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) #define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff) =20 -unsigned int __max_die_per_package __read_mostly =3D 1; -EXPORT_SYMBOL(__max_die_per_package); - #ifdef CONFIG_SMP /* * Check if given CPUID extended topology "leaf" is implemented From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93045C04FE1 for ; Mon, 14 Aug 2023 08:56:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235201AbjHNI4F (ORCPT ); Mon, 14 Aug 2023 04:56:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235147AbjHNIyX (ORCPT ); Mon, 14 Aug 2023 04:54:23 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEE46E7D for ; Mon, 14 Aug 2023 01:54:19 -0700 (PDT) Message-ID: <20230814085113.705691574@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003258; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Vh23GAdKR2k+QgZKWm5uISvklevqGJQMFU6tYsix5zs=; b=4x/gIiJgvOC9ExMD46ZjigfBn1QjSxY1u9X3GzSq4Qs9joFiDkSa2pQ7ldUJXBjJJSCXqY /RnS/oWE1vuf+naobFOdd6N5FXzfvVs53TBU8l3qv77O95oQkMahD81HUIS/wKEiRKqA3x XnrgrSR6eTfI4aakdDTWyvuqi65OoRvtPtBQvqGH83y1A99x+tauKE6ie/xHsL3LRnL+GT Df38BPHrc0b/7UubWkcgsOAqWKEj64AtlrX/ZlXMzEC8i31Za+Vx2ftBZbB/TLSj9xG3iT LX/vhW3P600WvM2/kF+TkHkuiRmH82O+Jp6JggKHgzy7cwO2ytlmg9eLsSMT8Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003258; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Vh23GAdKR2k+QgZKWm5uISvklevqGJQMFU6tYsix5zs=; b=x9tVDmMAAWHT2+ywu1Fu0gGVJPUwV0un4LeboWcKD+O19Fl0txixqGCXAeRNCtrzLJyky+ eLZ2hTlWX4TNuABQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 28/41] x86/cpu: Provide a sane leaf 0xb/0x1f parser References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:17 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" detect_extended_topology() along with it's early() variant is a classic example for duct tape engineering: - It evaluates an array of subleafs with a boatload of local variables for the relevant topology levels instead of using an array to save the enumerated information and propagate it to the right level - It has no boundary checks for subleafs - It prevents updating the die_id with a crude workaround instead of checking for leaf 0xb which does not provide die information. - It's broken vs. the number of dies evaluation as it uses: num_processors[DIE_LEVEL] / num_processors[CORE_LEVEL] which "works" only correctly if there is none of the intermediate topology levels (MODULE/TILE) enumerated. There is zero value in trying to "fix" that code as the only proper fix is to rewrite it from scratch. Implement a sane parser with proper code documentation, which will be used for the consolidated topology evaluation in the next step. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V4: Handle unknown domain types gracefully - Rui V2: Fixed up the comment alignment for registers - Peterz --- arch/x86/kernel/cpu/Makefile | 2=20 arch/x86/kernel/cpu/topology.h | 12 +++ arch/x86/kernel/cpu/topology_ext.c | 132 ++++++++++++++++++++++++++++++++= +++++ 3 files changed, 145 insertions(+), 1 deletion(-) --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -18,7 +18,7 @@ KMSAN_SANITIZE_common.o :=3D n KCSAN_SANITIZE_common.o :=3D n =20 obj-y :=3D cacheinfo.o scattered.o -obj-y +=3D topology_common.o topology.o +obj-y +=3D topology_common.o topology_ext.o topology.o obj-y +=3D common.o obj-y +=3D rdrand.o obj-y +=3D match.o --- a/arch/x86/kernel/cpu/topology.h +++ b/arch/x86/kernel/cpu/topology.h @@ -16,6 +16,7 @@ void cpu_init_topology(struct cpuinfo_x8 void cpu_parse_topology(struct cpuinfo_x86 *c); void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains d= om, unsigned int shift, unsigned int ncpus); +bool cpu_parse_topology_ext(struct topo_scan *tscan); =20 static inline u32 topo_shift_apicid(u32 apicid, enum x86_topology_domains = dom) { @@ -36,4 +37,15 @@ static inline u32 topo_domain_mask(enum return (1U << x86_topo_system.dom_shifts[dom]) - 1; } =20 +/* + * Update a domain level after the fact without propagating. Used to fixup + * broken CPUID enumerations. + */ +static inline void topology_update_dom(struct topo_scan *tscan, enum x86_t= opology_domains dom, + unsigned int shift, unsigned int ncpus) +{ + tscan->dom_shifts[dom] =3D shift; + tscan->dom_ncpus[dom] =3D ncpus; +} + #endif /* ARCH_X86_TOPOLOGY_H */ --- /dev/null +++ b/arch/x86/kernel/cpu/topology_ext.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +#include +#include +#include + +#include "cpu.h" + +enum topo_types { + INVALID_TYPE =3D 0, + SMT_TYPE =3D 1, + CORE_TYPE =3D 2, + MODULE_TYPE =3D 3, + TILE_TYPE =3D 4, + DIE_TYPE =3D 5, + DIEGRP_TYPE =3D 6, + MAX_TYPE =3D 7, +}; + +/* + * Use a lookup table for the case that there are future types > 6 which + * describe an intermediate domain level which does not exist today. + * + * A table will also be handy to parse the new AMD 0x80000026 leaf which + * has defined different domain types, but otherwise uses the same layout + * with some of the reserved bits used for new information. + */ +static const unsigned int topo_domain_map[MAX_TYPE] =3D { + [SMT_TYPE] =3D TOPO_SMT_DOMAIN, + [CORE_TYPE] =3D TOPO_CORE_DOMAIN, + [MODULE_TYPE] =3D TOPO_MODULE_DOMAIN, + [TILE_TYPE] =3D TOPO_TILE_DOMAIN, + [DIE_TYPE] =3D TOPO_DIE_DOMAIN, + [DIEGRP_TYPE] =3D TOPO_PKG_DOMAIN, +}; + +static inline bool topo_subleaf(struct topo_scan *tscan, u32 leaf, u32 sub= leaf, + unsigned int *last_dom) +{ + unsigned int dom, maxtype =3D leaf =3D=3D 0xb ? CORE_TYPE + 1 : MAX_TYPE; + struct { + // eax + u32 x2apic_shift : 5, // Number of bits to shift APIC ID right + // for the topology ID at the next level + __rsvd0 : 27; // Reserved + // ebx + u32 num_processors : 16, // Number of processors at current level + __rsvd1 : 16; // Reserved + // ecx + u32 level : 8, // Current topology level. Same as sub leaf number + type : 8, // Level type. If 0, invalid + __rsvd2 : 16; // Reserved + // edx + u32 x2apic_id : 32; // X2APIC ID of the current logical processor + } sl; + + cpuid_subleaf(leaf, subleaf, &sl); + + if (!sl.num_processors || sl.type =3D=3D INVALID_TYPE) + return false; + + if (sl.type >=3D maxtype) { + pr_err_once("Topology: leaf 0x%x:%d Unknown domain type %u\n", + leaf, subleaf, sl.type); + /* + * The subleafs are ordered in domain level order so + * propagate it into the next domain level carefully: if + * the last domain level was PKG, then overwrite PKG + * as otherwise this would end up in the root domain. + * + * It really would have been too obvious to make the domain + * type space sparse and leave a few reserved types between + * the points which might change instead of following the + * usual "this can be fixed in software" principle. + */ + dom =3D *last_dom =3D=3D TOPO_PKG_DOMAIN ? TOPO_PKG_DOMAIN : *last_dom += 1; + } else { + dom =3D topo_domain_map[sl.type]; + *last_dom =3D dom; + } + + if (!dom) { + tscan->c->topo.initial_apicid =3D sl.x2apic_id; + } else if (tscan->c->topo.initial_apicid !=3D sl.x2apic_id) { + pr_warn_once(FW_BUG "CPUID leaf 0x%x subleaf %d APIC ID mismatch %x !=3D= %x\n", + leaf, subleaf, tscan->c->topo.initial_apicid, sl.x2apic_id); + } + + topology_set_dom(tscan, dom, sl.x2apic_shift, sl.num_processors); + return true; +} + +static bool parse_topology_leaf(struct topo_scan *tscan, u32 leaf) +{ + unsigned int last_dom; + u32 subleaf; + + if (tscan->c->cpuid_level < leaf) + return false; + + /* Read all available subleafs and populate the levels */ + for (subleaf =3D 0, last_dom =3D 0; topo_subleaf(tscan, leaf, subleaf, &l= ast_dom); subleaf++); + + /* If subleaf 0 failed to parse, give up */ + if (!subleaf) + return false; + + /* + * There are machines in the wild which have shift 0 in the subleaf + * 0, but advertise 2 logical processors at that level. They are + * truly SMT. + */ + if (!tscan->dom_shifts[TOPO_SMT_DOMAIN] && tscan->dom_ncpus[TOPO_SMT_DOMA= IN] > 1) { + unsigned int sft =3D get_count_order(tscan->dom_ncpus[TOPO_SMT_DOMAIN]); + + pr_warn_once(FW_BUG "CPUID leaf 0x%x subleaf 0 has shift level 0 but %u = CPUs\n", + leaf, tscan->dom_ncpus[TOPO_SMT_DOMAIN]); + topology_update_dom(tscan, TOPO_SMT_DOMAIN, sft, tscan->dom_ncpus[TOPO_S= MT_DOMAIN]); + } + + set_cpu_cap(tscan->c, X86_FEATURE_XTOPOLOGY); + return true; +} + +bool cpu_parse_topology_ext(struct topo_scan *tscan) +{ + /* Try lead 0x1F first. If not available try leaf 0x0b */ + if (parse_topology_leaf(tscan, 0x1f)) + return true; + return parse_topology_leaf(tscan, 0x0b); +} From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 283DBEB64DD for ; Mon, 14 Aug 2023 08:56:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235210AbjHNI4J (ORCPT ); Mon, 14 Aug 2023 04:56:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235177AbjHNIy0 (ORCPT ); Mon, 14 Aug 2023 04:54:26 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7938210FE for ; Mon, 14 Aug 2023 01:54:21 -0700 (PDT) Message-ID: <20230814085113.764264669@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003260; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=GFENnwX+EQXucyzICf77kLz8TQxe+yt9RE4ePYTTB00=; b=NMvWh4ghqq0y26qLaVsXzvmNFq3Axq9DWhEjGkWG/gnru66mdJvT/ch4Ctr+yMT1PIHxim iXGEOykqN4FP4OUlnDSbx5ndRNJrZbKqQQW7oqZ9iqC5ytIKuMKNSJcGueuU+oJajcbqjs rfUJ2r5JiXiiyQfAcasNwuMsI8/Wgz3vO0fj25rrTDD2IF29oarHuuVxscBbr9KdwGJ4ng MiqMpl2LIkBCSteAdI2Rj63Wy9SxsqBAEb0f8IG90bdy/VZcWM//P5jxGgO5li254NrTP+ KNBlbN89LjOdUDLlhMcqkgVJnpyagnv6FNgcLAmqKalCoypViUDvLr+OJEKRjw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003260; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=GFENnwX+EQXucyzICf77kLz8TQxe+yt9RE4ePYTTB00=; b=cRE74DFcMifAdPoxEODOhf0gaEDFUwYYy3yi7IKyTZg6QtBiOzIcGbxenCpXKRfbtsMdct XwAidVgTxeB6O/AA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 29/41] x86/cpu: Use common topology code for Intel References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:19 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel CPUs use either topology leaf 0xb/0x1f evaluation or the legacy SMP/HT evaluation based on CPUID leaf 0x1/0x4. Move it over to the consolidated topology code and remove the random topology hacks which are sprinkled into the Intel and the common code. No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/kernel/cpu/common.c | 65 -----------------------------= ----- arch/x86/kernel/cpu/cpu.h | 4 -- arch/x86/kernel/cpu/intel.c | 25 ------------- arch/x86/kernel/cpu/topology_common.c | 5 ++ 4 files changed, 4 insertions(+), 95 deletions(-) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -784,19 +784,6 @@ static void get_model_name(struct cpuinf *(s + 1) =3D '\0'; } =20 -void detect_num_cpu_cores(struct cpuinfo_x86 *c) -{ - unsigned int eax, ebx, ecx, edx; - - c->x86_max_cores =3D 1; - if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) - return; - - cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); - if (eax & 0x1f) - c->x86_max_cores =3D (eax >> 26) + 1; -} - void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) { unsigned int n, dummy, ebx, ecx, edx, l2size; @@ -858,54 +845,6 @@ static void cpu_detect_tlb(struct cpuinf tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); } =20 -int detect_ht_early(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_SMP - u32 eax, ebx, ecx, edx; - - if (!cpu_has(c, X86_FEATURE_HT)) - return -1; - - if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) - return -1; - - if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) - return -1; - - cpuid(1, &eax, &ebx, &ecx, &edx); - - smp_num_siblings =3D (ebx & 0xff0000) >> 16; - if (smp_num_siblings =3D=3D 1) - pr_info_once("CPU0: Hyper-Threading is disabled\n"); -#endif - return 0; -} - -void detect_ht(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_SMP - int index_msb, core_bits; - - if (topo_is_converted(c)) - return; - - if (detect_ht_early(c) < 0) - return; - - index_msb =3D get_count_order(smp_num_siblings); - c->topo.pkg_id =3D apic->phys_pkg_id(c->topo.initial_apicid, index_msb); - - smp_num_siblings =3D smp_num_siblings / c->x86_max_cores; - - index_msb =3D get_count_order(smp_num_siblings); - - core_bits =3D get_count_order(c->x86_max_cores); - - c->topo.core_id =3D apic->phys_pkg_id(c->topo.initial_apicid, index_msb) & - ((1 << core_bits) - 1); -#endif -} - static void get_cpu_vendor(struct cpuinfo_x86 *c) { char *v =3D c->x86_vendor_id; @@ -1853,10 +1792,6 @@ static void identify_cpu(struct cpuinfo_ c->x86, c->x86_model); } =20 -#ifdef CONFIG_X86_64 - detect_ht(c); -#endif - x86_init_rdrand(c); setup_pku(c); setup_cet(c); --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -76,11 +76,7 @@ extern void init_intel_cacheinfo(struct extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c); =20 -extern void detect_num_cpu_cores(struct cpuinfo_x86 *c); -extern int detect_extended_topology_early(struct cpuinfo_x86 *c); extern int detect_extended_topology(struct cpuinfo_x86 *c); -extern int detect_ht_early(struct cpuinfo_x86 *c); -extern void detect_ht(struct cpuinfo_x86 *c); extern void check_null_seg_clears_base(struct cpuinfo_x86 *c); =20 void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c); --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -489,13 +489,6 @@ static void early_init_intel(struct cpui } =20 check_memory_type_self_snoop_errata(c); - - /* - * Get the number of SMT siblings early from the extended topology - * leaf, if available. Otherwise try the legacy SMT detection. - */ - if (detect_extended_topology_early(c) < 0) - detect_ht_early(c); } =20 static void bsp_init_intel(struct cpuinfo_x86 *c) @@ -777,24 +770,6 @@ static void init_intel(struct cpuinfo_x8 =20 intel_workarounds(c); =20 - /* - * Detect the extended topology information if available. This - * will reinitialise the initial_apicid which will be used - * in init_intel_cacheinfo() - */ - detect_extended_topology(c); - - if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { - /* - * let's use the legacy cpuid vector 0x1 and 0x4 for topology - * detection. - */ - detect_num_cpu_cores(c); -#ifdef CONFIG_X86_32 - detect_ht(c); -#endif - } - init_intel_cacheinfo(c); =20 if (c->cpuid_level > 9) { --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -71,7 +71,6 @@ bool topo_is_converted(struct cpuinfo_x8 /* Temporary until everything is converted over. */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - case X86_VENDOR_INTEL: case X86_VENDOR_HYGON: return false; default: @@ -136,6 +135,10 @@ static void parse_topology(struct topo_s case X86_VENDOR_ZHAOXIN: parse_legacy(tscan); break; + case X86_VENDOR_INTEL: + if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan)) + parse_legacy(tscan); + break; } } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4695C001DB for ; Mon, 14 Aug 2023 08:56:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235168AbjHNI4N (ORCPT ); Mon, 14 Aug 2023 04:56:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235220AbjHNIy3 (ORCPT ); Mon, 14 Aug 2023 04:54:29 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05FC11707 for ; Mon, 14 Aug 2023 01:54:23 -0700 (PDT) Message-ID: <20230814085113.824492521@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003261; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JiFKuPBKlN24KG+PjTPN55A/Pkj3ndmSBHCiS+xUuSU=; b=xav5fB4zqAEMosg01b1Qggjktak3dpXA1vDlL09AvNnekos3wpSlLgJb+xePdlMKU1xs3X FdpkZet4BwIrYs9MGhSe0ZVYCbKM5rtoI9VOc/dH5QawP1V8XXsvAiKvzKwFVfW4hUwmwk imcNv1QyuW4/p2+9t5R/GOu0brcExg0v5x0hpixO0JUKmJ1DrDbbGZhn2JLWwTjN6NyKNr a6/SC0XD+7csnQlR3QIqLbNVm26qyvc0b4tuuH5xlG3K4jIsPVvZUep9kQF3RXRGYgRuZ4 ed/8stKqqlHl3e/6s8qUFhN0ROq+Hgt4QpjbEF06FjtNnxK5ZEOJImhSX0AwBw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003261; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JiFKuPBKlN24KG+PjTPN55A/Pkj3ndmSBHCiS+xUuSU=; b=SNrQaEHqgH7tnoytfQale5M4s/WoAeR/PGNcUM1DuoQo1+2HmKmFf2+g+3AF/hXuQ5nVnO +E4KepEejRbVe9AQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 30/41] x86/cpu/amd: Provide a separate accessor for Node ID References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:21 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD (ab)uses topology_die_id() to store the Node ID information and topology_max_dies_per_pkg to store the number of nodes per package. This collides with the proper processor die level enumeration which is coming on AMD with CPUID 8000_0026, unless there is a correlation between the two. There is zero documentation about that. So provide new storage and new accessors which for now still access die_id and topology_max_dies_per_pkg. Will be mopped up after AMD and HYGON are converted over. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/events/amd/core.c | 2 +- arch/x86/include/asm/processor.h | 3 +++ arch/x86/include/asm/topology.h | 8 ++++++++ arch/x86/kernel/amd_nb.c | 4 ++-- arch/x86/kernel/cpu/cacheinfo.c | 2 +- arch/x86/kernel/cpu/mce/amd.c | 4 ++-- arch/x86/kernel/cpu/mce/inject.c | 4 ++-- drivers/edac/amd64_edac.c | 4 ++-- drivers/edac/mce_amd.c | 4 ++-- 9 files changed, 23 insertions(+), 12 deletions(-) --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -574,7 +574,7 @@ static void amd_pmu_cpu_starting(int cpu if (!x86_pmu.amd_nb_constraints) return; =20 - nb_id =3D topology_die_id(cpu); + nb_id =3D topology_amd_node_id(cpu); WARN_ON_ONCE(nb_id =3D=3D BAD_APICID); =20 for_each_online_cpu(i) { --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -99,6 +99,9 @@ struct cpuinfo_topology { u32 logical_pkg_id; u32 logical_die_id; =20 + // AMD Node ID and Nodes per Package info + u32 amd_node_id; + // Cache level topology IDs u32 llc_id; u32 l2c_id; --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -131,6 +131,8 @@ extern const struct cpumask *cpu_cluster #define topology_core_id(cpu) (cpu_data(cpu).topo.core_id) #define topology_ppin(cpu) (cpu_data(cpu).ppin) =20 +#define topology_amd_node_id(cpu) (cpu_data(cpu).topo.die_id) + extern unsigned int __max_die_per_package; =20 #ifdef CONFIG_SMP @@ -160,6 +162,11 @@ int topology_update_die_map(unsigned int int topology_phys_to_logical_pkg(unsigned int pkg); bool topology_smt_supported(void); =20 +static inline unsigned int topology_amd_nodes_per_pkg(void) +{ + return __max_die_per_package; +} + extern struct cpumask __cpu_primary_thread_mask; #define cpu_primary_thread_mask ((const struct cpumask *)&__cpu_primary_th= read_mask) =20 @@ -182,6 +189,7 @@ static inline int topology_max_die_per_p static inline int topology_max_smt_threads(void) { return 1; } static inline bool topology_is_primary_thread(unsigned int cpu) { return t= rue; } static inline bool topology_smt_supported(void) { return false; } +static inline unsigned int topology_amd_nodes_per_pkg(void) { return 0; }; #endif /* !CONFIG_SMP */ =20 static inline void arch_fix_phys_package_id(int num, u32 slot) --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -370,7 +370,7 @@ struct resource *amd_get_mmconfig_range( =20 int amd_get_subcaches(int cpu) { - struct pci_dev *link =3D node_to_amd_nb(topology_die_id(cpu))->link; + struct pci_dev *link =3D node_to_amd_nb(topology_amd_node_id(cpu))->link; unsigned int mask; =20 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) @@ -384,7 +384,7 @@ int amd_get_subcaches(int cpu) int amd_set_subcaches(int cpu, unsigned long mask) { static unsigned int reset, ban; - struct amd_northbridge *nb =3D node_to_amd_nb(topology_die_id(cpu)); + struct amd_northbridge *nb =3D node_to_amd_nb(topology_amd_node_id(cpu)); unsigned int reg; int cuid; =20 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -595,7 +595,7 @@ static void amd_init_l3_cache(struct _cp if (index < 3) return; =20 - node =3D topology_die_id(smp_processor_id()); + node =3D topology_amd_node_id(smp_processor_id()); this_leaf->nb =3D node_to_amd_nb(node); if (this_leaf->nb && !this_leaf->nb->l3_cache.indices) amd_calc_l3_indices(this_leaf->nb); --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -1181,7 +1181,7 @@ static int threshold_create_bank(struct return -ENODEV; =20 if (is_shared_bank(bank)) { - nb =3D node_to_amd_nb(topology_die_id(cpu)); + nb =3D node_to_amd_nb(topology_amd_node_id(cpu)); =20 /* threshold descriptor already initialized on this node? */ if (nb && nb->bank4) { @@ -1285,7 +1285,7 @@ static void threshold_remove_bank(struct * The last CPU on this node using the shared bank is going * away, remove that bank now. */ - nb =3D node_to_amd_nb(topology_die_id(smp_processor_id())); + nb =3D node_to_amd_nb(topology_amd_node_id(smp_processor_id())); nb->bank4 =3D NULL; } =20 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -543,8 +543,8 @@ static void do_inject(void) if (boot_cpu_has(X86_FEATURE_AMD_DCM) && b =3D=3D 4 && boot_cpu_data.x86 < 0x17) { - toggle_nb_mca_mst_cpu(topology_die_id(cpu)); - cpu =3D get_nbc_for_node(topology_die_id(cpu)); + toggle_nb_mca_mst_cpu(topology_amd_node_id(cpu)); + cpu =3D get_nbc_for_node(topology_amd_node_id(cpu)); } =20 cpus_read_lock(); --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1907,7 +1907,7 @@ static void dct_determine_memory_type(st /* On F10h and later ErrAddr is MC4_ADDR[47:1] */ static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) { - u16 mce_nid =3D topology_die_id(m->extcpu); + u16 mce_nid =3D topology_amd_node_id(m->extcpu); struct mem_ctl_info *mci; u8 start_bit =3D 1; u8 end_bit =3D 47; @@ -3438,7 +3438,7 @@ static void get_cpus_on_this_dct_cpumask int cpu; =20 for_each_online_cpu(cpu) - if (topology_die_id(cpu) =3D=3D nid) + if (topology_amd_node_id(cpu) =3D=3D nid) cpumask_set_cpu(cpu, mask); } =20 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1060,7 +1060,7 @@ static void decode_mc3_mce(struct mce *m static void decode_mc4_mce(struct mce *m) { unsigned int fam =3D x86_family(m->cpuid); - int node_id =3D topology_die_id(m->extcpu); + int node_id =3D topology_amd_node_id(m->extcpu); u16 ec =3D EC(m->status); u8 xec =3D XEC(m->status, 0x1f); u8 offset =3D 0; @@ -1188,7 +1188,7 @@ static void decode_smca_error(struct mce =20 if ((bank_type =3D=3D SMCA_UMC || bank_type =3D=3D SMCA_UMC_V2) && xec =3D=3D 0 && decode_dram_ecc) - decode_dram_ecc(topology_die_id(m->extcpu), m); + decode_dram_ecc(topology_amd_node_id(m->extcpu), m); } =20 static inline void amd_decode_err_code(u16 ec) From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7325C001B0 for ; Mon, 14 Aug 2023 08:56:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235323AbjHNI4T (ORCPT ); Mon, 14 Aug 2023 04:56:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235239AbjHNIya (ORCPT ); Mon, 14 Aug 2023 04:54:30 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC19718F for ; Mon, 14 Aug 2023 01:54:24 -0700 (PDT) Message-ID: <20230814085113.883990779@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003263; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=NYGuwdJ//rPFHqKo+0l67C4fCihy8Nqu66LcaLqg8p8=; b=Mhy9Cva4UePD+V9nJAEc47ntgasTJTMfDb/Y0v5wCAMqcKFHqH4cTWzbOun38WS3G+Wqoj jnM044kRyYBlYvtL52ed0BhfF+DQiSwgon3WVWAQi6TNlQvjVudM0zKxuUETnYEebaHtiu M5Ksh4JI6cyKbL8n22Wvmom6tyQ7LyrjVUxX605ZeZVrGrRvpVF25TptjEj4uSNM+B8aUz b0JNJb0RU+ywKo7J35+5y82SX2AKc1WWxpzOIvgnt+T2mbOI+s61BrOMHa5hs9nuj6Urzo 40K+aWpbT9tzOjfdvueeMcMgHGTWkXZVJFxCNuNcu1IEbxNqYwUNyM8KBGUTIg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003263; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=NYGuwdJ//rPFHqKo+0l67C4fCihy8Nqu66LcaLqg8p8=; b=si3SNBmX5nAYQqxt3TVh8oI0xHYErZhxeAeLdd8lLso/ZqMUdNMM4d9ooVmzgU34OkK6T8 M88sBIHAJaO3jVDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 31/41] x86/cpu: Provide an AMD/HYGON specific topology parser References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:22 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD/HYGON uses various methods for topology evaluation: - Leaf 0x80000008 and 0x8000001e based with an optional leaf 0xb, which is the preferred variant for modern CPUs. Leaf 0xb will be superseded by leaf 0x80000026 soon, which is just another variant of the Intel 0x1f leaf for whatever reasons. =20 - Subleaf 0x80000008 and NODEID_MSR base - Legacy fallback That code is following the principle of random bits and pieces all over the place which results in multiple evaluations and impenetrable code flows in the same way as the Intel parsing did. Provide a sane implementation by clearly separating the three variants and bringing them in the proper preference order in one place. This provides the parsing for both AMD and HYGON because there is no point in having a separate HYGON parser which only differs by 3 lines of code. Any further divergence between AMD and HYGON can be handled in different functions, while still sharing the existing parsers. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V4: Fix the off by one completely - Michael V4: Integrate the Hygon fixup - Pu V3: Fix the off by one with leaf 0x8000001e::ebx::threads_per_cu - Michael --- arch/x86/include/asm/topology.h | 2=20 arch/x86/kernel/cpu/Makefile | 2=20 arch/x86/kernel/cpu/amd.c | 2=20 arch/x86/kernel/cpu/cacheinfo.c | 4=20 arch/x86/kernel/cpu/cpu.h | 2=20 arch/x86/kernel/cpu/debugfs.c | 2=20 arch/x86/kernel/cpu/topology.h | 6 + arch/x86/kernel/cpu/topology_amd.c | 182 +++++++++++++++++++++++++++++= +++++ arch/x86/kernel/cpu/topology_common.c | 19 +++ 9 files changed, 214 insertions(+), 7 deletions(-) --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -162,6 +162,8 @@ int topology_update_die_map(unsigned int int topology_phys_to_logical_pkg(unsigned int pkg); bool topology_smt_supported(void); =20 +extern unsigned int __amd_nodes_per_pkg; + static inline unsigned int topology_amd_nodes_per_pkg(void) { return __max_die_per_package; --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -18,7 +18,7 @@ KMSAN_SANITIZE_common.o :=3D n KCSAN_SANITIZE_common.o :=3D n =20 obj-y :=3D cacheinfo.o scattered.o -obj-y +=3D topology_common.o topology_ext.o topology.o +obj-y +=3D topology_common.o topology_ext.o topology_amd.o topology.o obj-y +=3D common.o obj-y +=3D rdrand.o obj-y +=3D match.o --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -423,7 +423,7 @@ static void amd_get_topology(struct cpui if (!err) c->x86_coreid_bits =3D get_count_order(c->x86_max_cores); =20 - cacheinfo_amd_init_llc_id(c); + cacheinfo_amd_init_llc_id(c, c->topo.die_id); =20 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -661,7 +661,7 @@ static int find_num_cache_leaves(struct return i; } =20 -void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c) +void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id) { /* * We may have multiple LLCs if L3 caches exist, so check if we @@ -672,7 +672,7 @@ void cacheinfo_amd_init_llc_id(struct cp =20 if (c->x86 < 0x17) { /* LLC is at the node level. */ - c->topo.llc_id =3D c->topo.die_id; + c->topo.llc_id =3D die_id; } else if (c->x86 =3D=3D 0x17 && c->x86_model <=3D 0x1F) { /* * LLC is at the core complex level. --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -79,7 +79,7 @@ extern void init_hygon_cacheinfo(struct extern int detect_extended_topology(struct cpuinfo_x86 *c); extern void check_null_seg_clears_base(struct cpuinfo_x86 *c); =20 -void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c); +void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id); void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c); =20 unsigned int aperfmperf_get_khz(int cpu); --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -26,6 +26,8 @@ static int cpu_debug_show(struct seq_fil seq_printf(m, "logical_die_id: %u\n", c->topo.logical_die_id); seq_printf(m, "llc_id: %u\n", c->topo.llc_id); seq_printf(m, "l2c_id: %u\n", c->topo.l2c_id); + seq_printf(m, "amd_node_id: %u\n", c->topo.amd_node_id); + seq_printf(m, "amd_nodes_per_pkg: %u\n", topology_amd_nodes_per_pkg()); seq_printf(m, "max_cores: %u\n", c->x86_max_cores); seq_printf(m, "max_die_per_pkg: %u\n", __max_die_per_package); seq_printf(m, "smp_num_siblings: %u\n", smp_num_siblings); --- a/arch/x86/kernel/cpu/topology.h +++ b/arch/x86/kernel/cpu/topology.h @@ -9,6 +9,10 @@ struct topo_scan { =20 // Legacy CPUID[1]:EBX[23:16] number of logical processors unsigned int ebx1_nproc_shift; + + // AMD specific node ID which cannot be mapped into APIC space. + u16 amd_nodes_per_pkg; + u16 amd_node_id; }; =20 bool topo_is_converted(struct cpuinfo_x86 *c); @@ -17,6 +21,8 @@ void cpu_parse_topology(struct cpuinfo_x void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains d= om, unsigned int shift, unsigned int ncpus); bool cpu_parse_topology_ext(struct topo_scan *tscan); +void cpu_parse_topology_amd(struct topo_scan *tscan); +void cpu_topology_fixup_amd(struct topo_scan *tscan); =20 static inline u32 topo_shift_apicid(u32 apicid, enum x86_topology_domains = dom) { --- /dev/null +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +#include +#include +#include + +#include "cpu.h" + +static bool parse_8000_0008(struct topo_scan *tscan) +{ + struct { + u32 ncores : 8, + __rsvd0 : 4, + apicidsize : 4, + perftscsize : 2, + __rsvd1 : 14; + } ecx; + unsigned int sft; + + if (tscan->c->extended_cpuid_level < 0x80000008) + return false; + + cpuid_leaf_reg(0x80000008, CPUID_ECX, &ecx); + + /* If the APIC ID size is 0, then get the shift value from ecx.ncores */ + sft =3D ecx.apicidsize; + if (!sft) + sft =3D get_count_order(ecx.ncores + 1); + + topology_set_dom(tscan, TOPO_CORE_DOMAIN, sft, ecx.ncores + 1); + return true; +} + +static void store_node(struct topo_scan *tscan, unsigned int nr_nodes, u16= node_id) +{ + /* + * Starting with Fam 17h the DIE domain could probably be used to + * retrieve the node info on AMD/HYGON. Analysis of CPUID dumps + * suggests it's the topmost bit(s) of the CPU cores area, but + * that's guess work and neither enumerated nor documented. + * + * Up to Fam 16h this does not work at all and the legacy node ID + * has to be used. + */ + tscan->amd_nodes_per_pkg =3D nr_nodes; + tscan->amd_node_id =3D node_id; +} + +static bool parse_8000_001e(struct topo_scan *tscan, bool has_0xb) +{ + struct { + // eax + u32 x2apic_id : 32; + // ebx + u32 cuid : 8, + threads_per_cu : 8, + __rsvd0 : 16; + // ecx + u32 nodeid : 8, + nodes_per_pkg : 3, + __rsvd1 : 21; + // edx + u32 __rsvd2 : 32; + } leaf; + + if (!boot_cpu_has(X86_FEATURE_TOPOEXT)) + return false; + + cpuid_leaf(0x8000001e, &leaf); + + tscan->c->topo.initial_apicid =3D leaf.x2apic_id; + + /* + * If leaf 0xb is available, then SMT shift is set already. If not + * take it from ecx.threads_per_cu and use topo_update_dom() - + * topology_set_dom() would propagate and overwrite the already + * propagated CORE level. + */ + if (!has_0xb) { + unsigned int nthreads =3D leaf.threads_per_cu + 1; + + topology_update_dom(tscan, TOPO_SMT_DOMAIN, get_count_order(nthreads), n= threads); + } + + store_node(tscan, leaf.nodes_per_pkg + 1, leaf.nodeid); + + if (tscan->c->x86_vendor =3D=3D X86_VENDOR_AMD) { + if (tscan->c->x86 =3D=3D 0x15) + tscan->c->topo.cu_id =3D leaf.cuid; + + cacheinfo_amd_init_llc_id(tscan->c, leaf.nodeid); + } else { + /* + * Package ID is ApicId[6..] on certain Hygon CPUs. See + * commit e0ceeae708ce for explanation. The topology info + * is screwed up: The package shift is always 6 and the + * node ID is bit [4:5]. + */ + if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && tscan->c->x86_model <=3D 0x= 3) { + topology_set_dom(tscan, TOPO_CORE_DOMAIN, 6, + tscan->dom_ncpus[TOPO_CORE_DOMAIN]); + } + cacheinfo_hygon_init_llc_id(tscan->c); + } + return true; +} + +static bool parse_fam10h_node_id(struct topo_scan *tscan) +{ + struct { + union { + u64 node_id : 3, + nodes_per_pkg : 3, + unused : 58; + u64 msr; + }; + } nid; + + if (!boot_cpu_has(X86_FEATURE_NODEID_MSR)) + return false; + + rdmsrl(MSR_FAM10H_NODE_ID, nid.msr); + store_node(tscan, nid.nodes_per_pkg + 1, nid.node_id); + tscan->c->topo.llc_id =3D nid.node_id; + return true; +} + +static void legacy_set_llc(struct topo_scan *tscan) +{ + unsigned int apicid =3D tscan->c->topo.initial_apicid; + + /* parse_8000_0008() set everything up except llc_id */ + tscan->c->topo.llc_id =3D apicid >> tscan->dom_shifts[TOPO_CORE_DOMAIN]; +} + +static void parse_topology_amd(struct topo_scan *tscan) +{ + bool has_0xb =3D false; + + /* + * If the extended topology leaf 0x8000_001e is available + * try to get SMT and CORE shift from leaf 0xb first, then + * try to get the CORE shift from leaf 0x8000_0008. + */ + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) + has_0xb =3D cpu_parse_topology_ext(tscan); + + if (!has_0xb && !parse_8000_0008(tscan)) + return; + + /* Prefer leaf 0x8000001e if available */ + if (parse_8000_001e(tscan, has_0xb)) + return; + + /* Try the NODEID MSR */ + if (parse_fam10h_node_id(tscan)) + return; + + legacy_set_llc(tscan); +} + +void cpu_parse_topology_amd(struct topo_scan *tscan) +{ + tscan->amd_nodes_per_pkg =3D 1; + parse_topology_amd(tscan); + + if (tscan->amd_nodes_per_pkg > 1) + set_cpu_cap(tscan->c, X86_FEATURE_AMD_DCM); +} + +void cpu_topology_fixup_amd(struct topo_scan *tscan) +{ + struct cpuinfo_x86 *c =3D tscan->c; + + /* + * Adjust the core_id relative to the node when there is more than + * one node. + */ + if (tscan->c->x86 < 0x17 && tscan->amd_nodes_per_pkg > 1) + c->topo.core_id %=3D tscan->dom_ncpus[TOPO_CORE_DOMAIN] / tscan->amd_nod= es_per_pkg; +} --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -11,11 +11,13 @@ =20 struct x86_topology_system x86_topo_system __ro_after_init; =20 +unsigned int __amd_nodes_per_pkg __ro_after_init; +EXPORT_SYMBOL_GPL(__amd_nodes_per_pkg); + void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains d= om, unsigned int shift, unsigned int ncpus) { - tscan->dom_shifts[dom] =3D shift; - tscan->dom_ncpus[dom] =3D ncpus; + topology_update_dom(tscan, dom, shift, ncpus); =20 /* Propagate to the upper levels */ for (dom++; dom < TOPO_MAX_DOMAIN; dom++) { @@ -153,6 +155,13 @@ static void topo_set_ids(struct topo_sca /* Package relative core ID */ c->topo.core_id =3D (apicid & topo_domain_mask(TOPO_PKG_DOMAIN)) >> x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; + + /* Temporary workaround */ + if (tscan->amd_nodes_per_pkg) + c->topo.amd_node_id =3D c->topo.die_id =3D tscan->amd_node_id; + + if (c->x86_vendor =3D=3D X86_VENDOR_AMD) + cpu_topology_fixup_amd(tscan); } =20 static void topo_set_max_cores(struct topo_scan *tscan) @@ -237,4 +246,10 @@ void __init cpu_init_topology(struct cpu */ __max_die_per_package =3D tscan.dom_ncpus[TOPO_DIE_DOMAIN] / tscan.dom_ncpus[TOPO_DIE_DOMAIN - 1]; + /* + * AMD systems have Nodes per package which cannot be mapped to + * APIC ID (yet). + */ + if (c->x86_vendor =3D=3D X86_VENDOR_AMD || c->x86_vendor =3D=3D X86_VENDO= R_HYGON) + __amd_nodes_per_pkg =3D __max_die_per_package =3D tscan.amd_nodes_per_pk= g; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C315FC41513 for ; Mon, 14 Aug 2023 08:56:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235289AbjHNI4Q (ORCPT ); Mon, 14 Aug 2023 04:56:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230138AbjHNIyb (ORCPT ); Mon, 14 Aug 2023 04:54:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48B00E63 for ; Mon, 14 Aug 2023 01:54:26 -0700 (PDT) Message-ID: <20230814085113.943741781@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003264; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4iXkw5b5yzZbS9P0CLmmPoIGWnWH9U/f1eKITrK8kpw=; b=sklJX4oAPlfvpMTY5+d2q0Au85TgEjcHLA9xdA43L5u3Iyq1cmB0cc/eUvfGMD5J3bhUEX P48mwKli15guQW3EjGUz3yntth+fpRA+bPKMrP+ptYWpECbXH+irPHxkZh44jPMD58+Npy 3F850MWIkdUfpR15izpt9Syk/Chve3K9JS5u6VbaN19hDETY4RClvZURfQC1J+MOMLJb2O U2vl9e3zaqCInXyE8anzLHa3YxZz3GMa32YM58ee+jr9aOL6MM9MJjqL4EiCiWJlFZdpz1 qWQJJv1Hid2nWVshIaFj5oudK+A0efUw3kHsCyulKvBZzldg/AklIssOvznk5Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003264; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4iXkw5b5yzZbS9P0CLmmPoIGWnWH9U/f1eKITrK8kpw=; b=AcsWVBpCTuRd2eOsOedhyz0xNvRtlRz+J3WJc9E4BhY7ceFU1AJamHR2WOVtK3xHi+jFJr RKMI0EbgBqm+CRAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 32/41] x86/smpboot: Teach it about topo.amd_node_id References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:24 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When switching AMD over to the new topology parser then the match functions need to look for AMD systems with the extended topology feature at the new topo.amd_node_id member which is then holding the node id information. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/kernel/smpboot.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -499,6 +499,7 @@ static bool match_smt(struct cpuinfo_x86 =20 if (c->topo.pkg_id =3D=3D o->topo.pkg_id && c->topo.die_id =3D=3D o->topo.die_id && + c->topo.amd_node_id =3D=3D o->topo.amd_node_id && per_cpu_llc_id(cpu1) =3D=3D per_cpu_llc_id(cpu2)) { if (c->topo.core_id =3D=3D o->topo.core_id) return topology_sane(c, o, "smt"); @@ -520,10 +521,13 @@ static bool match_smt(struct cpuinfo_x86 =20 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) { - if (c->topo.pkg_id =3D=3D o->topo.pkg_id && - c->topo.die_id =3D=3D o->topo.die_id) - return true; - return false; + if (c->topo.pkg_id !=3D o->topo.pkg_id || c->topo.die_id !=3D o->topo.die= _id) + return false; + + if (boot_cpu_has(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1) + return c->topo.amd_node_id =3D=3D o->topo.amd_node_id; + + return true; } =20 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7559C04E69 for ; Mon, 14 Aug 2023 08:56:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235459AbjHNI4W (ORCPT ); Mon, 14 Aug 2023 04:56:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235273AbjHNIyc (ORCPT ); Mon, 14 Aug 2023 04:54:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C435F10C for ; Mon, 14 Aug 2023 01:54:27 -0700 (PDT) Message-ID: <20230814085114.002953361@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003266; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/DmRw+WfLZvgCDxn8Hw1HKZNr4tPuD3Da23+jG0TmgU=; b=PLFOD5RNw7Oaj4rdp2LrSaV+euaSNDDzZiandRFexPEG70Tv2zJlUgW6OYvqxtpr9hjqYI um1iQGrVXIDN/JXp5PhhlGrbQTY/QKegZ1uW5uWqPx7jeQCRdlq8oD2hfP7kjw+WLALP6H HLYYXODeBv3NHpkAk+2FfxCGFxhkSZj3npFng51GEF8DEie0LIv7Xnt4xCCabSMTj45Z6b ed/IC+EMderH4IpLvIjNFEjsMw4umwQg9k3X+hEQzxZ+UVOl4anmo+QjCPyqyFiqfZvek1 5cK/bqmOLsA6mqeNaBQLH7+Q2uvwPJrn9oePICJ8pu0pxjs2zgow8gL+XJdxSQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003266; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/DmRw+WfLZvgCDxn8Hw1HKZNr4tPuD3Da23+jG0TmgU=; b=hNzkPZAi1myY4lTjSXPOCSEAi/9ytCcFDv5p7CGG8y0tLpIuU4iU78fTdywNwA9nenWUIX 3hUNMx68bx+TQrCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 33/41] x86/cpu: Use common topology code for AMD References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:25 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch it over to the new topology evaluation mechanism and remove the random bits and pieces which are sprinkled all over the place. No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/processor.h | 2=20 arch/x86/include/asm/topology.h | 5 + arch/x86/kernel/cpu/amd.c | 146 -----------------------------= ----- arch/x86/kernel/cpu/mce/inject.c | 3=20 arch/x86/kernel/cpu/topology_common.c | 5 - 5 files changed, 10 insertions(+), 151 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -705,10 +705,8 @@ static inline u32 per_cpu_l2c_id(unsigne } =20 #ifdef CONFIG_CPU_SUP_AMD -extern u32 amd_get_nodes_per_socket(void); extern u32 amd_get_highest_perf(void); #else -static inline u32 amd_get_nodes_per_socket(void) { return 0; } static inline u32 amd_get_highest_perf(void) { return 0; } #endif =20 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -121,6 +121,11 @@ struct x86_topology_system { =20 extern struct x86_topology_system x86_topo_system; =20 +static inline unsigned int topology_get_domain_size(enum x86_topology_doma= ins dom) +{ + return x86_topo_system.dom_size[dom]; +} + extern const struct cpumask *cpu_coregroup_mask(int cpu); extern const struct cpumask *cpu_clustergroup_mask(int cpu); =20 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -28,13 +28,6 @@ #include "cpu.h" =20 /* - * nodes_per_socket: Stores the number of nodes per socket. - * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX - * Node Identifiers[10:8] - */ -static u32 nodes_per_socket =3D 1; - -/* * AMD errata checking * * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or @@ -372,97 +365,6 @@ static int nearby_node(int apicid) } #endif =20 -/* - * Fix up topo::core_id for pre-F17h systems to be in the - * [0 .. cores_per_node - 1] range. Not really needed but - * kept so as not to break existing setups. - */ -static void legacy_fixup_core_id(struct cpuinfo_x86 *c) -{ - u32 cus_per_node; - - if (c->x86 >=3D 0x17) - return; - - cus_per_node =3D c->x86_max_cores / nodes_per_socket; - c->topo.core_id %=3D cus_per_node; -} - -/* - * Fixup core topology information for - * (1) AMD multi-node processors - * Assumption: Number of cores in each internal node is the same. - * (2) AMD processors supporting compute units - */ -static void amd_get_topology(struct cpuinfo_x86 *c) -{ - /* get information required for multi-node processors */ - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - int err; - u32 eax, ebx, ecx, edx; - - cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); - - c->topo.die_id =3D ecx & 0xff; - - if (c->x86 =3D=3D 0x15) - c->topo.cu_id =3D ebx & 0xff; - - if (c->x86 >=3D 0x17) { - c->topo.core_id =3D ebx & 0xff; - - if (smp_num_siblings > 1) - c->x86_max_cores /=3D smp_num_siblings; - } - - /* - * In case leaf B is available, use it to derive - * topology information. - */ - err =3D detect_extended_topology(c); - if (!err) - c->x86_coreid_bits =3D get_count_order(c->x86_max_cores); - - cacheinfo_amd_init_llc_id(c, c->topo.die_id); - - } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { - u64 value; - - rdmsrl(MSR_FAM10H_NODE_ID, value); - c->topo.die_id =3D value & 7; - c->topo.llc_id =3D c->topo.die_id; - } else - return; - - if (nodes_per_socket > 1) { - set_cpu_cap(c, X86_FEATURE_AMD_DCM); - legacy_fixup_core_id(c); - } -} - -/* - * On a AMD dual core setup the lower bits of the APIC id distinguish the = cores. - * Assumes number of cores is a power of two. - */ -static void amd_detect_cmp(struct cpuinfo_x86 *c) -{ - unsigned bits; - - bits =3D c->x86_coreid_bits; - /* Low order bits define the core id (index of core in socket) */ - c->topo.core_id =3D c->topo.initial_apicid & ((1 << bits)-1); - /* Convert the initial APIC ID into the socket ID */ - c->topo.pkg_id =3D c->topo.initial_apicid >> bits; - /* use socket ID also for last level cache */ - c->topo.llc_id =3D c->topo.die_id =3D c->topo.pkg_id; -} - -u32 amd_get_nodes_per_socket(void) -{ - return nodes_per_socket; -} -EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); - static void srat_detect_node(struct cpuinfo_x86 *c) { #ifdef CONFIG_NUMA @@ -514,32 +416,6 @@ static void srat_detect_node(struct cpui #endif } =20 -static void early_init_amd_mc(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_SMP - unsigned bits, ecx; - - /* Multi core CPU? */ - if (c->extended_cpuid_level < 0x80000008) - return; - - ecx =3D cpuid_ecx(0x80000008); - - c->x86_max_cores =3D (ecx & 0xff) + 1; - - /* CPU telling us the core id bits shift? */ - bits =3D (ecx >> 12) & 0xF; - - /* Otherwise recompute */ - if (bits =3D=3D 0) { - while ((1 << bits) < c->x86_max_cores) - bits++; - } - - c->x86_coreid_bits =3D bits; -#endif -} - static void bsp_init_amd(struct cpuinfo_x86 *c) { if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { @@ -572,18 +448,6 @@ static void bsp_init_amd(struct cpuinfo_ if (cpu_has(c, X86_FEATURE_MWAITX)) use_mwaitx_delay(); =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - u32 ecx; - - ecx =3D cpuid_ecx(0x8000001e); - __max_die_per_package =3D nodes_per_socket =3D ((ecx >> 8) & 7) + 1; - } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { - u64 value; - - rdmsrl(MSR_FAM10H_NODE_ID, value); - __max_die_per_package =3D nodes_per_socket =3D ((value >> 3) & 7) + 1; - } - if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && c->x86 >=3D 0x15 && c->x86 <=3D 0x17) { @@ -665,8 +529,6 @@ static void early_init_amd(struct cpuinf u64 value; u32 dummy; =20 - early_init_amd_mc(c); - if (c->x86 >=3D 0xf) set_cpu_cap(c, X86_FEATURE_K8); =20 @@ -754,9 +616,6 @@ static void early_init_amd(struct cpuinf } } } - - if (cpu_has(c, X86_FEATURE_TOPOEXT)) - smp_num_siblings =3D ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; } =20 static void init_amd_k8(struct cpuinfo_x86 *c) @@ -1037,9 +896,6 @@ static void init_amd(struct cpuinfo_x86 if (cpu_has(c, X86_FEATURE_FSRM)) set_cpu_cap(c, X86_FEATURE_FSRS); =20 - /* get apicid instead of initial apic id from cpuid */ - c->topo.apicid =3D read_apic_id(); - /* K6s reports MCEs but don't actually have all the MSRs */ if (c->x86 < 6) clear_cpu_cap(c, X86_FEATURE_MCE); @@ -1067,8 +923,6 @@ static void init_amd(struct cpuinfo_x86 =20 cpu_detect_cache_sizes(c); =20 - amd_detect_cmp(c); - amd_get_topology(c); srat_detect_node(c); =20 init_amd_cacheinfo(c); --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -433,8 +433,7 @@ static u32 get_nbc_for_node(int node_id) struct cpuinfo_x86 *c =3D &boot_cpu_data; u32 cores_per_node; =20 - cores_per_node =3D (c->x86_max_cores * smp_num_siblings) / amd_get_nodes_= per_socket(); - + cores_per_node =3D (c->x86_max_cores * smp_num_siblings) / topology_amd_n= odes_per_pkg(); return cores_per_node * node_id; } =20 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -72,7 +72,6 @@ bool topo_is_converted(struct cpuinfo_x8 { /* Temporary until everything is converted over. */ switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_AMD: case X86_VENDOR_HYGON: return false; default: @@ -133,6 +132,10 @@ static void parse_topology(struct topo_s tscan->ebx1_nproc_shift =3D get_count_order(ebx.nproc); =20 switch (c->x86_vendor) { + case X86_VENDOR_AMD: + if (IS_ENABLED(CONFIG_CPU_SUP_AMD)) + cpu_parse_topology_amd(tscan); + break; case X86_VENDOR_CENTAUR: case X86_VENDOR_ZHAOXIN: parse_legacy(tscan); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57D49C04FE0 for ; Mon, 14 Aug 2023 08:56:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235557AbjHNI43 (ORCPT ); Mon, 14 Aug 2023 04:56:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235277AbjHNIye (ORCPT ); Mon, 14 Aug 2023 04:54:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C6CB114 for ; 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b=Bxs/eVeVBR3e1zaWtypiaOd4U75shmGnzCELG5ifYRJzr4APj+54mvDMfafA3zdjjWoseB NZDzyKoU5ICFzGBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 34/41] x86/cpu: Use common topology code for HYGON References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:27 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch it over to use the consolidated topology evaluation and remove the temporary safe guards which are not longer needed. No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V4: Remove the stale define - Pu --- arch/x86/kernel/cpu/common.c | 5 - arch/x86/kernel/cpu/cpu.h | 1=20 arch/x86/kernel/cpu/hygon.c | 129 -----------------------------= ----- arch/x86/kernel/cpu/topology.h | 1=20 arch/x86/kernel/cpu/topology_common.c | 22 +---- 5 files changed, 4 insertions(+), 154 deletions(-) --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1740,11 +1740,6 @@ static void identify_cpu(struct cpuinfo_ /* Clear/Set all flags overridden by options, after probe */ apply_forced_caps(c); =20 -#ifdef CONFIG_X86_64 - if (!topo_is_converted(c)) - c->topo.apicid =3D apic->phys_pkg_id(c->topo.initial_apicid, 0); -#endif - /* * Vendor-specific initialization. In this section we * canonicalize the feature flags, meaning if there are --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -76,7 +76,6 @@ extern void init_intel_cacheinfo(struct extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c); =20 -extern int detect_extended_topology(struct cpuinfo_x86 *c); extern void check_null_seg_clears_base(struct cpuinfo_x86 *c); =20 void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id); --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -18,14 +18,6 @@ =20 #include "cpu.h" =20 -#define APICID_SOCKET_ID_BIT 6 - -/* - * nodes_per_socket: Stores the number of nodes per socket. - * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8] - */ -static u32 nodes_per_socket =3D 1; - #ifdef CONFIG_NUMA /* * To workaround broken NUMA config. Read the comment in @@ -49,80 +41,6 @@ static int nearby_node(int apicid) } #endif =20 -static void hygon_get_topology_early(struct cpuinfo_x86 *c) -{ - if (cpu_has(c, X86_FEATURE_TOPOEXT)) - smp_num_siblings =3D ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; -} - -/* - * Fixup core topology information for - * (1) Hygon multi-node processors - * Assumption: Number of cores in each internal node is the same. - * (2) Hygon processors supporting compute units - */ -static void hygon_get_topology(struct cpuinfo_x86 *c) -{ - /* get information required for multi-node processors */ - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - int err; - u32 eax, ebx, ecx, edx; - - cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); - - c->topo.die_id =3D ecx & 0xff; - - c->topo.core_id =3D ebx & 0xff; - - if (smp_num_siblings > 1) - c->x86_max_cores /=3D smp_num_siblings; - - /* - * In case leaf B is available, use it to derive - * topology information. - */ - err =3D detect_extended_topology(c); - if (!err) - c->x86_coreid_bits =3D get_count_order(c->x86_max_cores); - - /* - * Socket ID is ApicId[6] for the processors with model <=3D 0x3 - * when running on host. - */ - if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && c->x86_model <=3D 0x3) - c->topo.pkg_id =3D c->topo.apicid >> APICID_SOCKET_ID_BIT; - - cacheinfo_hygon_init_llc_id(c); - } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { - u64 value; - - rdmsrl(MSR_FAM10H_NODE_ID, value); - c->topo.die_id =3D value & 7; - c->topo.llc_id =3D c->topo.die_id; - } else - return; - - if (nodes_per_socket > 1) - set_cpu_cap(c, X86_FEATURE_AMD_DCM); -} - -/* - * On Hygon setup the lower bits of the APIC id distinguish the cores. - * Assumes number of cores is a power of two. - */ -static void hygon_detect_cmp(struct cpuinfo_x86 *c) -{ - unsigned int bits; - - bits =3D c->x86_coreid_bits; - /* Low order bits define the core id (index of core in socket) */ - c->topo.core_id =3D c->topo.initial_apicid & ((1 << bits)-1); - /* Convert the initial APIC ID into the socket ID */ - c->topo.pkg_id =3D c->topo.initial_apicid >> bits; - /* Use package ID also for last level cache */ - c->topo.llc_id =3D c->topo.die_id =3D c->topo.pkg_id; -} - static void srat_detect_node(struct cpuinfo_x86 *c) { #ifdef CONFIG_NUMA @@ -173,32 +91,6 @@ static void srat_detect_node(struct cpui #endif } =20 -static void early_init_hygon_mc(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_SMP - unsigned int bits, ecx; - - /* Multi core CPU? */ - if (c->extended_cpuid_level < 0x80000008) - return; - - ecx =3D cpuid_ecx(0x80000008); - - c->x86_max_cores =3D (ecx & 0xff) + 1; - - /* CPU telling us the core id bits shift? */ - bits =3D (ecx >> 12) & 0xF; - - /* Otherwise recompute */ - if (bits =3D=3D 0) { - while ((1 << bits) < c->x86_max_cores) - bits++; - } - - c->x86_coreid_bits =3D bits; -#endif -} - static void bsp_init_hygon(struct cpuinfo_x86 *c) { if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { @@ -212,18 +104,6 @@ static void bsp_init_hygon(struct cpuinf if (cpu_has(c, X86_FEATURE_MWAITX)) use_mwaitx_delay(); =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - u32 ecx; - - ecx =3D cpuid_ecx(0x8000001e); - __max_die_per_package =3D nodes_per_socket =3D ((ecx >> 8) & 7) + 1; - } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { - u64 value; - - rdmsrl(MSR_FAM10H_NODE_ID, value); - __max_die_per_package =3D nodes_per_socket =3D ((value >> 3) & 7) + 1; - } - if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) { /* @@ -242,8 +122,6 @@ static void early_init_hygon(struct cpui { u32 dummy; =20 - early_init_hygon_mc(c); - set_cpu_cap(c, X86_FEATURE_K8); =20 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); @@ -284,8 +162,6 @@ static void early_init_hygon(struct cpui * we can set it unconditionally. */ set_cpu_cap(c, X86_FEATURE_VMMCALL); - - hygon_get_topology_early(c); } =20 static void init_hygon(struct cpuinfo_x86 *c) @@ -300,9 +176,6 @@ static void init_hygon(struct cpuinfo_x8 =20 set_cpu_cap(c, X86_FEATURE_REP_GOOD); =20 - /* get apicid instead of initial apic id from cpuid */ - c->topo.apicid =3D read_apic_id(); - /* * XXX someone from Hygon needs to confirm this DTRT * @@ -314,8 +187,6 @@ static void init_hygon(struct cpuinfo_x8 =20 cpu_detect_cache_sizes(c); =20 - hygon_detect_cmp(c); - hygon_get_topology(c); srat_detect_node(c); =20 init_hygon_cacheinfo(c); --- a/arch/x86/kernel/cpu/topology.h +++ b/arch/x86/kernel/cpu/topology.h @@ -15,7 +15,6 @@ struct topo_scan { u16 amd_node_id; }; =20 -bool topo_is_converted(struct cpuinfo_x86 *c); void cpu_init_topology(struct cpuinfo_x86 *c); void cpu_parse_topology(struct cpuinfo_x86 *c); void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains d= om, --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -68,18 +68,6 @@ static void parse_legacy(struct topo_sca topology_set_dom(tscan, TOPO_CORE_DOMAIN, core_shift, cores); } =20 -bool topo_is_converted(struct cpuinfo_x86 *c) -{ - /* Temporary until everything is converted over. */ - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_HYGON: - return false; - default: - /* Let all UP systems use the below */ - return true; - } -} - static bool fake_topology(struct topo_scan *tscan) { /* @@ -144,6 +132,10 @@ static void parse_topology(struct topo_s if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan)) parse_legacy(tscan); break; + case X86_VENDOR_HYGON: + if (IS_ENABLED(CONFIG_CPU_SUP_HYGON)) + cpu_parse_topology_amd(tscan); + break; } } =20 @@ -187,9 +179,6 @@ void cpu_parse_topology(struct cpuinfo_x =20 parse_topology(&tscan, false); =20 - if (!topo_is_converted(c)) - return; - for (dom =3D TOPO_SMT_DOMAIN; dom < TOPO_MAX_DOMAIN; dom++) { if (tscan.dom_shifts[dom] =3D=3D x86_topo_system.dom_shifts[dom]) continue; @@ -218,9 +207,6 @@ void __init cpu_init_topology(struct cpu =20 parse_topology(&tscan, true); =20 - if (!topo_is_converted(c)) - return; - /* Copy the shift values and calculate the unit sizes. */ memcpy(x86_topo_system.dom_shifts, tscan.dom_shifts, sizeof(x86_topo_syst= em.dom_shifts)); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4422DC04A94 for ; Mon, 14 Aug 2023 08:56:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235503AbjHNI41 (ORCPT ); Mon, 14 Aug 2023 04:56:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235288AbjHNIye (ORCPT ); Mon, 14 Aug 2023 04:54:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D916A1BD for ; Mon, 14 Aug 2023 01:54:30 -0700 (PDT) Message-ID: <20230814085114.122486064@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003269; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=KNjlYqK62kvWWNdZZBwz2X0bSzPm//v1My83FVIs0LE=; b=y32DxOthr4bdHzCepPeCBGvrJjWN+PshCCm7Ido13cXCC/q61sCOizcxzkRfl3tuwX4U0l xTKC04oKKx03utvQp83umNWARZc/7JDH4ZFBVcugb1s6BW4/ll1Emkk9WwzDd/fmcwqAFC HX9wLU4J/Pjjk6FsDxLhzUtcOFEaiEfDBXOK4visJMw/S5DgXjamJ42dOZ+Jhy4iMAVO03 Ng2Pew376PBoA+uMvUnq1gstcyTvKgBxOutTJ5fGWaAQAms1NE7VyDQSrqoICCK2bVaJra Y1FfTIvGxYNZx+jKjNz8FkO9BrV/VSdsnS/PjiWX/qWSQ4Wj9XxGVmccoJbttQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003269; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=KNjlYqK62kvWWNdZZBwz2X0bSzPm//v1My83FVIs0LE=; b=nYtRPNGmcgvVRf0ireuShfidQojMADom6vxlmsPdFK4shcIqOMngLUPsQ5bQNuQIRGMW3l /u8OOBOjHAKe9/CA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 35/41] x86/mm/numa: Use core domain size on AMD References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:29 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cpuinfo::topo::x86_coreid_bits is about to be phased out. Use the core domain size from the topology information. Add a comment why the early MPTABLE parsing is required and decrapify the loop which sets the APIC ID to node map. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/mm/amdtopology.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) --- a/arch/x86/mm/amdtopology.c +++ b/arch/x86/mm/amdtopology.c @@ -54,13 +54,11 @@ static __init int find_northbridge(void) =20 int __init amd_numa_init(void) { - u64 start =3D PFN_PHYS(0); + unsigned int numnodes, cores, apicid; + u64 prevbase, start =3D PFN_PHYS(0); u64 end =3D PFN_PHYS(max_pfn); - unsigned numnodes; - u64 prevbase; - int i, j, nb; u32 nodeid, reg; - unsigned int bits, cores, apicid_base; + int i, j, nb; =20 if (!early_pci_allowed()) return -EINVAL; @@ -158,26 +156,25 @@ int __init amd_numa_init(void) return -ENOENT; =20 /* - * We seem to have valid NUMA configuration. Map apicids to nodes - * using the coreid bits from early_identify_cpu. + * We seem to have valid NUMA configuration. Map apicids to nodes + * using the size of the core domain in the APIC space. */ - bits =3D boot_cpu_data.x86_coreid_bits; - cores =3D 1 << bits; - apicid_base =3D 0; + cores =3D topology_get_domain_size(TOPO_CORE_DOMAIN); =20 /* - * get boot-time SMP configuration: + * Scan MPTABLE to map the local APIC and ensure that the boot CPU + * APIC ID is valid. This is required because on pre ACPI/SRAT + * systems IO-APICs are mapped before the boot CPU. */ early_get_smp_config(); =20 - if (boot_cpu_physical_apicid > 0) { - pr_info("BSP APIC ID: %02x\n", boot_cpu_physical_apicid); - apicid_base =3D boot_cpu_physical_apicid; + apicid =3D boot_cpu_physical_apicid; + if (apicid > 0) + pr_info("BSP APIC ID: %02x\n", apicid); + + for_each_node_mask(i, numa_nodes_parsed) { + for (j =3D 0; j < cores; j++, apicid++) + set_apicid_to_node(apicid, i); } - - for_each_node_mask(i, numa_nodes_parsed) - for (j =3D apicid_base; j < cores + apicid_base; j++) - set_apicid_to_node((i << bits) + j, i); - return 0; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65FACC04FDF for ; Mon, 14 Aug 2023 08:56:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235583AbjHNI4c (ORCPT ); Mon, 14 Aug 2023 04:56:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234663AbjHNIye (ORCPT ); Mon, 14 Aug 2023 04:54:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7327A18E for ; Mon, 14 Aug 2023 01:54:32 -0700 (PDT) Message-ID: <20230814085114.183018283@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003271; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=53nlX+r/fEq0JBYCW+1MqV4BLn6IkJJvtfrqLhkPQXE=; b=eNgC1LsoEznrxFiuUNUWa33Gw7F3kPsxszaafBI1YkLk/VMqXpxggYRauYy/zBtlquCfw5 N6RSOQF3FXQXMqEYpzUyCFFE+EcrtVSiXP5t0QeTCvcpRk40mh3nyVYmknvJ/1NrFlKxAB CWwn0HlQ5w3gjVj/7A4Lr0SEBLqaIGyiKnZJ9YunpZNXCw+FZv1ThbO/+Tj443f55zDh/F xPBKLS/H1nItKZK56ZITZZFCBS0ju0vIUAzCytbAvE4aG4Zo8MCTwzB1MWSFJ2JyecYsFu AQGWzRg9djwNBtgYVGJMSKhU/Y8gyg1RKQxQKlc4h71T9tQqz8YWkAaZS0XstQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003271; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=53nlX+r/fEq0JBYCW+1MqV4BLn6IkJJvtfrqLhkPQXE=; b=ccngd3SNxF6qfuRpIxGi97cI9OLxWSkpv8b7gUwj+60KeFNXlRnMxjqtySuZFqJgFU7Xny 9dwvGjNahKtL44Ag== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 36/41] x86/cpu: Make topology_amd_node_id() use the actual node info References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:30 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that everything is converted switch it over and remove the intermediate operation. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/topology.h | 4 ++-- arch/x86/kernel/cpu/topology_common.c | 7 ++----- 2 files changed, 4 insertions(+), 7 deletions(-) --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -136,7 +136,7 @@ extern const struct cpumask *cpu_cluster #define topology_core_id(cpu) (cpu_data(cpu).topo.core_id) #define topology_ppin(cpu) (cpu_data(cpu).ppin) =20 -#define topology_amd_node_id(cpu) (cpu_data(cpu).topo.die_id) +#define topology_amd_node_id(cpu) (cpu_data(cpu).topo.amd_node_id) =20 extern unsigned int __max_die_per_package; =20 @@ -171,7 +171,7 @@ extern unsigned int __amd_nodes_per_pkg; =20 static inline unsigned int topology_amd_nodes_per_pkg(void) { - return __max_die_per_package; + return __amd_nodes_per_pkg; } =20 extern struct cpumask __cpu_primary_thread_mask; --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -151,9 +151,7 @@ static void topo_set_ids(struct topo_sca c->topo.core_id =3D (apicid & topo_domain_mask(TOPO_PKG_DOMAIN)) >> x86_topo_system.dom_shifts[TOPO_SMT_DOMAIN]; =20 - /* Temporary workaround */ - if (tscan->amd_nodes_per_pkg) - c->topo.amd_node_id =3D c->topo.die_id =3D tscan->amd_node_id; + c->topo.amd_node_id =3D tscan->amd_node_id; =20 if (c->x86_vendor =3D=3D X86_VENDOR_AMD) cpu_topology_fixup_amd(tscan); @@ -239,6 +237,5 @@ void __init cpu_init_topology(struct cpu * AMD systems have Nodes per package which cannot be mapped to * APIC ID (yet). */ - if (c->x86_vendor =3D=3D X86_VENDOR_AMD || c->x86_vendor =3D=3D X86_VENDO= R_HYGON) - __amd_nodes_per_pkg =3D __max_die_per_package =3D tscan.amd_nodes_per_pk= g; + __amd_nodes_per_pkg =3D tscan.amd_nodes_per_pkg; } From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94CDFC04FE1 for ; Mon, 14 Aug 2023 08:56:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235611AbjHNI4g (ORCPT ); Mon, 14 Aug 2023 04:56:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235321AbjHNIyg (ORCPT ); Mon, 14 Aug 2023 04:54:36 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DF87E63 for ; Mon, 14 Aug 2023 01:54:34 -0700 (PDT) Message-ID: <20230814085114.243119281@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003272; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=urg9ytenNECEHko0hv7V/DJOW+M53i4YgT/nUx/NrAo=; b=Dff6vXRY8j7D8T6GTpUIc+eXgxv2k6GB9peCX9NHgSt6tblr9kVrOeGsPDSShLGI699itB Ngt+Bmnqzsn3xFYcp8/CwBl2aXfDWmcQ8sMhibhspHnOwDIRylyxzFut0EO1H/0ktB0UX1 3U68EMcwlZ8g+vEuiiaBL7T1XbYy4A2irrlsBy/4dASiBGYLNDuIQjiIWwPW6QLcb8vb2P 2WGXUwaoh7AFRffwuJ1btFtYbJJtRhHIpYwASfj2wkNm5sZKlEn2y5K2EYXuh4JV2CyrWZ JP4jhd6WTGEBrFPZ299vBOWI1p1s894ajc9tRbCiPgwyAKcHGKEPFdR1c4+47w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003272; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=urg9ytenNECEHko0hv7V/DJOW+M53i4YgT/nUx/NrAo=; b=/3Bkwk89vFBQ9+PT8swpGd0ZY+7cJ8X+TIppoi2sZm+AbFuD0fUNIpRus3pmfh87e080I2 2yDUW5NSVjsZ1EBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 37/41] x86/cpu: Remove topology.c References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:32 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No more users. Stick it into the ugly code museum. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/kernel/cpu/Makefile | 2=20 arch/x86/kernel/cpu/topology.c | 164 ------------------------------------= ----- 2 files changed, 1 insertion(+), 165 deletions(-) --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -18,7 +18,7 @@ KMSAN_SANITIZE_common.o :=3D n KCSAN_SANITIZE_common.o :=3D n =20 obj-y :=3D cacheinfo.o scattered.o -obj-y +=3D topology_common.o topology_ext.o topology_amd.o topology.o +obj-y +=3D topology_common.o topology_ext.o topology_amd.o obj-y +=3D common.o obj-y +=3D rdrand.o obj-y +=3D match.o --- a/arch/x86/kernel/cpu/topology.c +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Check for extended topology enumeration cpuid leaf 0xb and if it - * exists, use it for populating initial_apicid and cpu topology - * detection. - */ - -#include -#include -#include -#include - -#include "cpu.h" - -/* leaf 0xb SMT level */ -#define SMT_LEVEL 0 - -/* extended topology sub-leaf types */ -#define INVALID_TYPE 0 -#define SMT_TYPE 1 -#define CORE_TYPE 2 -#define DIE_TYPE 5 - -#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) -#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) -#define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff) - -#ifdef CONFIG_SMP -/* - * Check if given CPUID extended topology "leaf" is implemented - */ -static int check_extended_topology_leaf(int leaf) -{ - unsigned int eax, ebx, ecx, edx; - - cpuid_count(leaf, SMT_LEVEL, &eax, &ebx, &ecx, &edx); - - if (ebx =3D=3D 0 || (LEAFB_SUBTYPE(ecx) !=3D SMT_TYPE)) - return -1; - - return 0; -} -/* - * Return best CPUID Extended Topology Leaf supported - */ -static int detect_extended_topology_leaf(struct cpuinfo_x86 *c) -{ - if (c->cpuid_level >=3D 0x1f) { - if (check_extended_topology_leaf(0x1f) =3D=3D 0) - return 0x1f; - } - - if (c->cpuid_level >=3D 0xb) { - if (check_extended_topology_leaf(0xb) =3D=3D 0) - return 0xb; - } - - return -1; -} -#endif - -int detect_extended_topology_early(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_SMP - unsigned int eax, ebx, ecx, edx; - int leaf; - - leaf =3D detect_extended_topology_leaf(c); - if (leaf < 0) - return -1; - - set_cpu_cap(c, X86_FEATURE_XTOPOLOGY); - - cpuid_count(leaf, SMT_LEVEL, &eax, &ebx, &ecx, &edx); - /* - * initial apic id, which also represents 32-bit extended x2apic id. - */ - c->topo.initial_apicid =3D edx; - smp_num_siblings =3D max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)= ); -#endif - return 0; -} - -/* - * Check for extended topology enumeration cpuid leaf, and if it - * exists, use it for populating initial_apicid and cpu topology - * detection. - */ -int detect_extended_topology(struct cpuinfo_x86 *c) -{ -#ifdef CONFIG_SMP - unsigned int eax, ebx, ecx, edx, sub_index; - unsigned int ht_mask_width, core_plus_mask_width, die_plus_mask_width; - unsigned int core_select_mask, core_level_siblings; - unsigned int die_select_mask, die_level_siblings; - unsigned int pkg_mask_width; - bool die_level_present =3D false; - int leaf; - - leaf =3D detect_extended_topology_leaf(c); - if (leaf < 0) - return -1; - - /* - * Populate HT related information from sub-leaf level 0. - */ - cpuid_count(leaf, SMT_LEVEL, &eax, &ebx, &ecx, &edx); - c->topo.initial_apicid =3D edx; - core_level_siblings =3D LEVEL_MAX_SIBLINGS(ebx); - smp_num_siblings =3D max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)= ); - core_plus_mask_width =3D ht_mask_width =3D BITS_SHIFT_NEXT_LEVEL(eax); - die_level_siblings =3D LEVEL_MAX_SIBLINGS(ebx); - pkg_mask_width =3D die_plus_mask_width =3D BITS_SHIFT_NEXT_LEVEL(eax); - - sub_index =3D 1; - while (true) { - cpuid_count(leaf, sub_index, &eax, &ebx, &ecx, &edx); - - /* - * Check for the Core type in the implemented sub leaves. - */ - if (LEAFB_SUBTYPE(ecx) =3D=3D CORE_TYPE) { - core_level_siblings =3D LEVEL_MAX_SIBLINGS(ebx); - core_plus_mask_width =3D BITS_SHIFT_NEXT_LEVEL(eax); - die_level_siblings =3D core_level_siblings; - die_plus_mask_width =3D BITS_SHIFT_NEXT_LEVEL(eax); - } - if (LEAFB_SUBTYPE(ecx) =3D=3D DIE_TYPE) { - die_level_present =3D true; - die_level_siblings =3D LEVEL_MAX_SIBLINGS(ebx); - die_plus_mask_width =3D BITS_SHIFT_NEXT_LEVEL(eax); - } - - if (LEAFB_SUBTYPE(ecx) !=3D INVALID_TYPE) - pkg_mask_width =3D BITS_SHIFT_NEXT_LEVEL(eax); - else - break; - - sub_index++; - } - - core_select_mask =3D (~(-1 << pkg_mask_width)) >> ht_mask_width; - die_select_mask =3D (~(-1 << die_plus_mask_width)) >> - core_plus_mask_width; - - c->topo.core_id =3D apic->phys_pkg_id(c->topo.initial_apicid, - ht_mask_width) & core_select_mask; - - if (die_level_present) { - c->topo.die_id =3D apic->phys_pkg_id(c->topo.initial_apicid, - core_plus_mask_width) & die_select_mask; - } - - c->topo.pkg_id =3D apic->phys_pkg_id(c->topo.initial_apicid, pkg_mask_wid= th); - /* - * Reinit the apicid, now that we have extended initial_apicid. - */ - c->topo.apicid =3D apic->phys_pkg_id(c->topo.initial_apicid, 0); - - c->x86_max_cores =3D (core_level_siblings / smp_num_siblings); - __max_die_per_package =3D (die_level_siblings / core_level_siblings); -#endif - return 0; -} From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76726C05052 for ; Mon, 14 Aug 2023 08:56:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235597AbjHNI4d (ORCPT ); Mon, 14 Aug 2023 04:56:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235337AbjHNIyh (ORCPT ); Mon, 14 Aug 2023 04:54:37 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79BF010F for ; Mon, 14 Aug 2023 01:54:35 -0700 (PDT) Message-ID: <20230814085114.301935500@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003274; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qdYGHf8yT/gB4O6cmEBR3VKAOVLhFCZDX/t11ieb+ro=; b=10Ht+OO+Uoa0b5Xrjvc8/M+k48npCX71PHilfCqJNwuyLLNlN743NNnes21us/RfaY0iTK MzDPvwZVjQUWn8BWpDeH/6Zek9rIriH/opgdPUiWDzFqliWw/RjQ897eQFQsPSA5fuCajN 6K6QrxHUzkDT6p1VwQjjVsIyh8HYvw2642ZFTKUPX9VbzPF8T7ckVlIpg5Ig8/hX5K6TNH CwjpV/A16Fz8wvBSSvk2kYfwyNjHv14/cDA6EDeIQFu7Y6rXLwDjZowrRJ6pu6fIY9qbPo eZbZsWP5e1PMzCyoiAMefcjl3XXWi8SUHMXAVSfpMp5VgEXZfXXa8PKi5JkOTw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003274; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qdYGHf8yT/gB4O6cmEBR3VKAOVLhFCZDX/t11ieb+ro=; b=U8D8LVuZac0lWRhZ8P0i2SUgJLNsWpXHfFP2OYNIchaUFMNQ6uv9qNy4h8QRtt1Lj04D7h 5JNprjJoaT05dnDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 38/41] x86/cpu: Remove x86_coreid_bits References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:33 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No more users. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/processor.h | 2 -- arch/x86/kernel/cpu/common.c | 1 - 2 files changed, 3 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -119,8 +119,6 @@ struct cpuinfo_x86 { #endif __u8 x86_virt_bits; __u8 x86_phys_bits; - /* CPUID returned core id bits: */ - __u8 x86_coreid_bits; /* Max extended CPUID function supported: */ __u32 extended_cpuid_level; /* Maximum supported CPUID level, -1=3Dno CPUID: */ --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1712,7 +1712,6 @@ static void identify_cpu(struct cpuinfo_ c->x86_vendor_id[0] =3D '\0'; /* Unset */ c->x86_model_id[0] =3D '\0'; /* Unset */ c->x86_max_cores =3D 1; - c->x86_coreid_bits =3D 0; #ifdef CONFIG_X86_64 c->x86_clflush_size =3D 64; c->x86_phys_bits =3D 36; From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34ADFEB64DD for ; Mon, 14 Aug 2023 08:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235628AbjHNI4m (ORCPT ); Mon, 14 Aug 2023 04:56:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235352AbjHNIyi (ORCPT ); Mon, 14 Aug 2023 04:54:38 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2566712D for ; Mon, 14 Aug 2023 01:54:37 -0700 (PDT) Message-ID: <20230814085114.360997471@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003275; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6kotpziBexnHaTc7L0AVu1xBQOcptwc2pW/uxqW6phU=; b=scQsBQUFqdazkZs172qVq7XlaYQ1BcF/HLAYIIVEght/4M6cAgPTf4AkcREkvi5/tOgDZ4 mlrpRw5V39ZtBVqxAEg1TvON4wq+uQgJT5PHu7N5bHFGjNbQaD9Hzj/vZime4RGAa6mmmo CJCd+dVbkfrvBKhNV7EWBneL/3bwSm1gKjnMDhoGw2Y7UCEipcs3LWF0br3R3jiLmQVUcG D+gLcBuX84aDlns8ZZC69IZBWsBIAqQML9RVWNV4p2SzPVbT61ZT9LiW54HzoiBWjyMRrT kiwWQXgPy4yo4TXJ7TFJN4cysPQ5hgAU+AsU/XG5rSajeXyvTyfJx91CsZx3eA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003275; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6kotpziBexnHaTc7L0AVu1xBQOcptwc2pW/uxqW6phU=; b=wmw3X3ffrJos8ej72EVgYnrH7NkMPPAzYMYuhJnstfz1X8rsn6Wbxu4jZDJmk4X89Ehk85 2jXNTi8liaMDiqCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 39/41] x86/apic: Remove unused phys_pkg_id() callback References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:35 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the core code does not use this monstrosity anymore, it's time to put it to rest. The only real purpose was to read the APIC ID on UV and VSMP systems for the actual evaluation. That's what the core code does now. For doing the actual shift operation there is truly no APIC callback required. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic_flat_64.c | 7 ------- arch/x86/kernel/apic/apic_noop.c | 3 --- arch/x86/kernel/apic/apic_numachip.c | 7 ------- arch/x86/kernel/apic/bigsmp_32.c | 6 ------ arch/x86/kernel/apic/local.h | 1 - arch/x86/kernel/apic/probe_32.c | 6 ------ arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 6 ------ arch/x86/kernel/apic/x2apic_uv_x.c | 11 ----------- arch/x86/kernel/vsmp_64.c | 13 ------------- arch/x86/xen/apic.c | 6 ------ 12 files changed, 68 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -296,7 +296,6 @@ struct apic { void (*init_apic_ldr)(void); void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap= ); u32 (*cpu_present_to_apicid)(int mps_cpu); - u32 (*phys_pkg_id)(u32 cpuid_apic, int index_msb); =20 u32 (*get_apic_id)(u32 id); u32 (*set_apic_id)(u32 apicid); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -66,11 +66,6 @@ static u32 set_apic_id(u32 id) return (id & 0xFF) << 24; } =20 -static u32 flat_phys_pkg_id(u32 initial_apic_id, int index_msb) -{ - return initial_apic_id >> index_msb; -} - static int flat_probe(void) { return 1; @@ -89,7 +84,6 @@ static struct apic apic_flat __ro_after_ =20 .init_apic_ldr =3D default_init_apic_ldr, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D flat_phys_pkg_id, =20 .max_apic_id =3D 0xFE, .get_apic_id =3D flat_get_apic_id, @@ -159,7 +153,6 @@ static struct apic apic_physflat __ro_af .disable_esr =3D 0, =20 .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D flat_phys_pkg_id, =20 .max_apic_id =3D 0xFE, .get_apic_id =3D flat_get_apic_id, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -29,7 +29,6 @@ static void noop_send_IPI_self(int vecto static void noop_apic_icr_write(u32 low, u32 id) { } static int noop_wakeup_secondary_cpu(u32 apicid, unsigned long start_eip) = { return -1; } static u64 noop_apic_icr_read(void) { return 0; } -static u32 noop_phys_pkg_id(u32 cpuid_apic, int index_msb) { return 0; } static u32 noop_get_apic_id(u32 apicid) { return 0; } static void noop_apic_eoi(void) { } =20 @@ -56,8 +55,6 @@ struct apic apic_noop __ro_after_init =3D .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 - .phys_pkg_id =3D noop_phys_pkg_id, - .max_apic_id =3D 0xFE, .get_apic_id =3D noop_get_apic_id, =20 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -56,11 +56,6 @@ static u32 numachip2_set_apic_id(u32 id) return id << 24; } =20 -static u32 numachip_phys_pkg_id(u32 initial_apic_id, int index_msb) -{ - return initial_apic_id >> index_msb; -} - static void numachip1_apic_icr_write(int apicid, unsigned int val) { write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val); @@ -228,7 +223,6 @@ static const struct apic apic_numachip1 .disable_esr =3D 0, =20 .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D numachip_phys_pkg_id, =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D numachip1_get_apic_id, @@ -265,7 +259,6 @@ static const struct apic apic_numachip2 .disable_esr =3D 0, =20 .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D numachip_phys_pkg_id, =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D numachip2_get_apic_id, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -29,11 +29,6 @@ static void bigsmp_ioapic_phys_id_map(ph physids_promote(0xFFL, retmap); } =20 -static u32 bigsmp_phys_pkg_id(u32 cpuid_apic, int index_msb) -{ - return cpuid_apic >> index_msb; -} - static void bigsmp_send_IPI_allbutself(int vector) { default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector); @@ -88,7 +83,6 @@ static struct apic apic_bigsmp __ro_afte .check_apicid_used =3D bigsmp_check_apicid_used, .ioapic_phys_id_map =3D bigsmp_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D bigsmp_phys_pkg_id, =20 .max_apic_id =3D 0xFE, .get_apic_id =3D bigsmp_get_apic_id, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -17,7 +17,6 @@ void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); u32 x2apic_get_apic_id(u32 id); u32 x2apic_set_apic_id(u32 id); -u32 x2apic_phys_pkg_id(u32 initial_apicid, int index_msb); =20 void x2apic_send_IPI_all(int vector); void x2apic_send_IPI_allbutself(int vector); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -18,11 +18,6 @@ =20 #include "local.h" =20 -static u32 default_phys_pkg_id(u32 cpuid_apic, int index_msb) -{ - return cpuid_apic >> index_msb; -} - static u32 default_get_apic_id(u32 x) { unsigned int ver =3D GET_APIC_VERSION(apic_read(APIC_LVR)); @@ -54,7 +49,6 @@ static struct apic apic_default __ro_aft .init_apic_ldr =3D default_init_apic_ldr, .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D default_phys_pkg_id, =20 .max_apic_id =3D 0xFE, .get_apic_id =3D default_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -236,7 +236,6 @@ static struct apic apic_x2apic_cluster _ .init_apic_ldr =3D init_x2apic_ldr, .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D x2apic_phys_pkg_id, =20 .max_apic_id =3D UINT_MAX, .x2apic_set_max_apicid =3D true, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -134,11 +134,6 @@ u32 x2apic_set_apic_id(u32 id) return id; } =20 -u32 x2apic_phys_pkg_id(u32 initial_apicid, int index_msb) -{ - return initial_apicid >> index_msb; -} - static struct apic apic_x2apic_phys __ro_after_init =3D { =20 .name =3D "physical x2apic", @@ -151,7 +146,6 @@ static struct apic apic_x2apic_phys __ro .disable_esr =3D 0, =20 .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D x2apic_phys_pkg_id, =20 .max_apic_id =3D UINT_MAX, .x2apic_set_max_apicid =3D true, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -785,16 +785,6 @@ static u32 set_apic_id(u32 id) return id; } =20 -static unsigned int uv_read_apic_id(void) -{ - return x2apic_get_apic_id(apic_read(APIC_ID)); -} - -static u32 uv_phys_pkg_id(u32 initial_apicid, int index_msb) -{ - return uv_read_apic_id() >> index_msb; -} - static int uv_probe(void) { return apic =3D=3D &apic_x2apic_uv_x; @@ -812,7 +802,6 @@ static struct apic apic_x2apic_uv_x __ro .disable_esr =3D 0, =20 .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .phys_pkg_id =3D uv_phys_pkg_id, =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D x2apic_get_apic_id, --- a/arch/x86/kernel/vsmp_64.c +++ b/arch/x86/kernel/vsmp_64.c @@ -127,25 +127,12 @@ static void __init vsmp_cap_cpus(void) #endif } =20 -static u32 apicid_phys_pkg_id(u32 initial_apic_id, int index_msb) -{ - return read_apic_id() >> index_msb; -} - -static void vsmp_apic_post_init(void) -{ - /* need to update phys_pkg_id */ - apic->phys_pkg_id =3D apicid_phys_pkg_id; -} - void __init vsmp_init(void) { detect_vsmp_box(); if (!is_vsmp_box()) return; =20 - x86_platform.apic_post_init =3D vsmp_apic_post_init; - vsmp_cap_cpus(); =20 set_vsmp_ctl(); --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -110,11 +110,6 @@ static int xen_madt_oem_check(char *oem_ return xen_pv_domain(); } =20 -static u32 xen_phys_pkg_id(u32 initial_apic_id, int index_msb) -{ - return initial_apic_id >> index_msb; -} - static u32 xen_cpu_present_to_apicid(int cpu) { if (cpu_present(cpu)) @@ -133,7 +128,6 @@ static struct apic xen_pv_apic __ro_afte .disable_esr =3D 0, =20 .cpu_present_to_apicid =3D xen_cpu_present_to_apicid, - .phys_pkg_id =3D xen_phys_pkg_id, /* detect_ht */ =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D xen_get_apic_id, From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43719C001B0 for ; Mon, 14 Aug 2023 08:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235658AbjHNI4s (ORCPT ); Mon, 14 Aug 2023 04:56:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235358AbjHNIyj (ORCPT ); Mon, 14 Aug 2023 04:54:39 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BB8610B for ; Mon, 14 Aug 2023 01:54:38 -0700 (PDT) Message-ID: <20230814085114.422748199@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003277; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=DKDeifQNE2gzfZT0qDOAFL1F6DNu3u0Ktu+/JKbdS38=; b=TYxBIHZkonVHLLx5Ica8jZF8hPJkiGu6nOwHuvcTV02nnbSacsa77jMhhbEUoiyurrWJK8 j4IKNVELYN90/ZcloktkeGNLslegl4wmiNGio7xwH5nnS1UL2IvQcmheLK9E9GS03UrOML SdzCbiHyvoeG8YkenYQ6zDKasg8DBhwjFUAz7Lqmp1Lt7QvaSIsQ1WLsykaadsRos2VJg6 +mvpxkdOljE5/vT2UGKok50TMqUEP+E/bzvMbPYXNFa/5Leu5Jeu6895Q7t3im2F4lDjKZ xyaR4Y9BvoEN/6bdZYvuMcjx/KX6iamAj9nQZmTueNzKrNuHkpIk/YQdrzMVGw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003277; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=DKDeifQNE2gzfZT0qDOAFL1F6DNu3u0Ktu+/JKbdS38=; b=kusI9gzoglLVpvJc/LiUKOYcTlzdvhUeXFlIWHGapRktAY7UnVOXqv2GUZPj8K17UfiBMt ujln9XXjJawqrXDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 40/41] x86/xen/smp_pv: Remove cpudata fiddling References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:36 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The new topology CPUID parser installs already fake topology for XEN/PV, which ends up with cpuinfo::max_cores =3D 1. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- V2: New patch --- arch/x86/xen/smp_pv.c | 3 --- 1 file changed, 3 deletions(-) --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -73,7 +73,6 @@ static void cpu_bringup(void) } cpu =3D smp_processor_id(); smp_store_cpu_info(cpu); - cpu_data(cpu).x86_max_cores =3D 1; set_cpu_sibling_map(cpu); =20 speculative_store_bypass_ht_init(); @@ -223,8 +222,6 @@ static void __init xen_pv_smp_prepare_cp =20 smp_prepare_cpus_common(); =20 - cpu_data(0).x86_max_cores =3D 1; - speculative_store_bypass_ht_init(); =20 xen_pmu_init(0); From nobody Thu Sep 11 10:16:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61427C04A94 for ; Mon, 14 Aug 2023 08:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235674AbjHNI4x (ORCPT ); Mon, 14 Aug 2023 04:56:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234789AbjHNIyl (ORCPT ); Mon, 14 Aug 2023 04:54:41 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35EBC91 for ; Mon, 14 Aug 2023 01:54:40 -0700 (PDT) Message-ID: <20230814085114.482126235@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1692003278; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4TtY+1BKk2VzsdzxqCUP6yDH6um+f9/iPyUkn07hGk0=; b=l72TkYrQwV6LW8hQZt71/dDvRtb7NxF8HOES3gDb5v2Mz8640IdnZcrD7toGSuTZr78Mx9 Jpcsiyv8yWlGkBOzntESGws+vLxQVHNqBl+8iDfrqifsrhAc9deAyzPH0SU9VLivfliYZ0 9wgsZGJ9RZVoCkPa4QdJiRBxDpOVduWu/DgEKX8WCw395qOqkrZmuaD68xi3P37FHoap9I hH+k50kjTH7+SaEK/eV3dfZIjUgF9nQMPvw+kij3skPnG9ghjhphN6pcgMzoMW1iYlgh+X xy4IzVvEHvgxRvHCExzuNYeL5GrFWIGQUbEtTOYVpyO0Kv5qcqYXugAwv26IzQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1692003278; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4TtY+1BKk2VzsdzxqCUP6yDH6um+f9/iPyUkn07hGk0=; b=Z1HnqMzmn7qUdropDSVkabzYBHAiuvagJseIA5kpwcROSQTee7BYwnWybyz2x7Ppw2WPG/ uVLN0uFV1EYQ48Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Michael Kelley , Wei Liu , Pu Wen , Qiuxu Zhuo , Sohil Mehta Subject: [patch V4 41/41] x86/apic/uv: Remove the private leaf 0xb parser References: <20230814085006.593997112@linutronix.de> MIME-Version: 1.0 Date: Mon, 14 Aug 2023 10:54:38 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The package shift has been already evaluated by the early CPU init. Put the mindless copy right next to the original leaf 0xb parser. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Acked-by: Peter Zijlstra (Intel) Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui --- arch/x86/include/asm/topology.h | 5 +++ arch/x86/kernel/apic/x2apic_uv_x.c | 52 ++++++--------------------------= ----- 2 files changed, 14 insertions(+), 43 deletions(-) --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -126,6 +126,11 @@ static inline unsigned int topology_get_ return x86_topo_system.dom_size[dom]; } =20 +static inline unsigned int topology_get_domain_shift(enum x86_topology_dom= ains dom) +{ + return dom =3D=3D TOPO_SMT_DOMAIN ? 0 : x86_topo_system.dom_shifts[dom - = 1]; +} + extern const struct cpumask *cpu_coregroup_mask(int cpu); extern const struct cpumask *cpu_clustergroup_mask(int cpu); =20 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -241,54 +241,20 @@ static void __init uv_tsc_check_sync(voi is_uv(UV3) ? sname.s3.field : \ undef) =20 -/* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()]= */ - -#define SMT_LEVEL 0 /* Leaf 0xb SMT level */ -#define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ -#define SMT_TYPE 1 -#define CORE_TYPE 2 -#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) -#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) - -static void set_x2apic_bits(void) -{ - unsigned int eax, ebx, ecx, edx, sub_index; - unsigned int sid_shift; - - cpuid(0, &eax, &ebx, &ecx, &edx); - if (eax < 0xb) { - pr_info("UV: CPU does not have CPUID.11\n"); - return; - } - - cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); - if (ebx =3D=3D 0 || (LEAFB_SUBTYPE(ecx) !=3D SMT_TYPE)) { - pr_info("UV: CPUID.11 not implemented\n"); - return; - } - - sid_shift =3D BITS_SHIFT_NEXT_LEVEL(eax); - sub_index =3D 1; - do { - cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); - if (LEAFB_SUBTYPE(ecx) =3D=3D CORE_TYPE) { - sid_shift =3D BITS_SHIFT_NEXT_LEVEL(eax); - break; - } - sub_index++; - } while (LEAFB_SUBTYPE(ecx) !=3D INVALID_TYPE); - - uv_cpuid.apicid_shift =3D 0; - uv_cpuid.apicid_mask =3D (~(-1 << sid_shift)); - uv_cpuid.socketid_shift =3D sid_shift; -} - static void __init early_get_apic_socketid_shift(void) { + unsigned int sid_shift =3D topology_get_domain_shift(TOPO_ROOT_DOMAIN); + if (is_uv2_hub() || is_uv3_hub()) uvh_apicid.v =3D uv_early_read_mmr(UVH_APICID); =20 - set_x2apic_bits(); + if (sid_shift) { + uv_cpuid.apicid_shift =3D 0; + uv_cpuid.apicid_mask =3D (~(-1 << sid_shift)); + uv_cpuid.socketid_shift =3D sid_shift; + } else { + pr_info("UV: CPU does not have valid CPUID.11\n"); + } =20 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, = uv_cpuid.apicid_mask); pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shif= t, uv_cpuid.pnode_mask);