From nobody Thu Dec 18 19:59:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40FA3C04A94 for ; Mon, 14 Aug 2023 08:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234629AbjHNIV2 (ORCPT ); Mon, 14 Aug 2023 04:21:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234731AbjHNIUh (ORCPT ); Mon, 14 Aug 2023 04:20:37 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A53421710; Mon, 14 Aug 2023 01:20:30 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 6A75324E2BA; Mon, 14 Aug 2023 16:20:29 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 14 Aug 2023 16:20:29 +0800 Received: from ubuntu.localdomain (183.27.98.20) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 14 Aug 2023 16:20:28 +0800 From: Minda Chen To: Daire McNamara , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Emil Renner Berthing CC: , , , , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v3 11/11] riscv: dts: starfive: add PCIe dts configuration for JH7110 Date: Mon, 14 Aug 2023 16:20:16 +0800 Message-ID: <20230814082016.104181-12-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230814082016.104181-1-minda.chen@starfivetech.com> References: <20230814082016.104181-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.20] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCIe dts configuraion for JH7110 SoC platform. Signed-off-by: Minda Chen Reviewed-by: Hal Feng --- .../jh7110-starfive-visionfive-2.dtsi | 64 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ 2 files changed, 150 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index de0f40a8be93..3f7d07966997 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -15,6 +15,8 @@ i2c2 =3D &i2c2; i2c5 =3D &i2c5; i2c6 =3D &i2c6; + pcie0 =3D &pcie0; + pcie1 =3D &pcie1; serial0 =3D &uart0; }; =20 @@ -208,6 +210,54 @@ }; }; =20 + pcie0_pins: pcie0-0 { + wake-pins { + pinmux =3D ; + bias-pull-up; + drive-strength =3D <2>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + clkreq-pins { + pinmux =3D ; + bias-pull-down; + drive-strength =3D <2>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + pcie1_pins: pcie1-0 { + wake-pins { + pinmux =3D ; + bias-pull-up; + drive-strength =3D <2>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + clkreq-pins { + pinmux =3D ; + bias-pull-down; + drive-strength =3D <2>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pinmux =3D ; + pinctrl-0 =3D <&pcie0_pins>; + status =3D "okay"; +}; + +&pcie1 { + pinctrl-names =3D "default"; + perst-gpios =3D <&sysgpio 28 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pcie1_pins>; + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 02354e642c44..7a5dc43cf63c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -629,5 +629,91 @@ #reset-cells =3D <1>; power-domains =3D <&pwrc JH7110_PD_VOUT>; }; + + pcie0: pcie@940000000 { + compatible =3D "starfive,jh7110-pcie"; + reg =3D <0x9 0x40000000 0x0 0x1000000>, + <0x0 0x2b000000 0x0 0x100000>; + reg-names =3D "cfg", "apb"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + ranges =3D <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + interrupts =3D <56>; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-controller; + device_type =3D "pci"; + starfive,stg-syscon =3D <&stg_syscon>; + bus-range =3D <0x0 0xff>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE0_TL>, + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE0_APB>; + clock-names =3D "noc", "tl", "axi_mst0", "apb"; + resets =3D <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE0_BRG>, + <&stgcrg JH7110_STGRST_PCIE0_CORE>, + <&stgcrg JH7110_STGRST_PCIE0_APB>; + reset-names =3D "mst0", "slv0", "slv", "brg", + "core", "apb"; + status =3D "disabled"; + + pcie_intc0: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@9c0000000 { + compatible =3D "starfive,jh7110-pcie"; + reg =3D <0x9 0xc0000000 0x0 0x1000000>, + <0x0 0x2c000000 0x0 0x100000>; + reg-names =3D "cfg", "apb"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + ranges =3D <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; + interrupts =3D <57>; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; + msi-controller; + device_type =3D "pci"; + starfive,stg-syscon =3D <&stg_syscon>; + bus-range =3D <0x0 0xff>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE1_TL>, + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE1_APB>; + clock-names =3D "noc", "tl", "axi_mst0", "apb"; + resets =3D <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE1_BRG>, + <&stgcrg JH7110_STGRST_PCIE1_CORE>, + <&stgcrg JH7110_STGRST_PCIE1_APB>; + reset-names =3D "mst0", "slv0", "slv", "brg", + "core", "apb"; + status =3D "disabled"; + + pcie_intc1: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; }; }; --=20 2.17.1