From nobody Thu Dec 18 22:07:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CDE3C0015E for ; Sat, 12 Aug 2023 20:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230331AbjHLUAR (ORCPT ); Sat, 12 Aug 2023 16:00:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230173AbjHLUAI (ORCPT ); Sat, 12 Aug 2023 16:00:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8A501998 for ; Sat, 12 Aug 2023 12:59:47 -0700 (PDT) Message-ID: <20230812195727.660453052@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691870320; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Om38mOGR5rsJ+3kNGer82JR+w3FtSUZk8MQVXgwmwBw=; b=HWheSECgs8fHA0pwSALBVWIHDDQWpxZArpuN8fup5l5Qc2d493d7zgXyDpd+pwVJhAtwpR ZOwSCdWdYoOY3uG7mg+FnwFl/bDDO9gu666ujoKGdzlm1aTB20X2ntzZ82YN+0rDOG2hn0 cXFQh9hXAUEz5DJaD0HRzWRhyyiBANA5zW01GzyE2ltpGB5Cn8G9Ay6flDkW9wgsx1F/IZ 2lUe33U6YWPmDLw9Ng97BAtqYpLmnuprwBwwQBCil7tkXpgMipw04RnySDb2Uk6lS9+IMX etqisTUYbGge31Ilnqcek/ry+RH2Jl7ysnSDqaUsTzdudIduG8pt8BegYvT76Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691870320; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Om38mOGR5rsJ+3kNGer82JR+w3FtSUZk8MQVXgwmwBw=; b=D9YFE1jmwB2zsJ9vCq140UTrDSkeNM1bvbcX0su+/Alb1gBbXolfDE/+Lg0404YH2qVqgL J34xbMVZuoaSEUBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven , Nikolay Borisov Subject: [patch V2 02/37] x86/microcode: Hide the config knob References: <20230812194003.682298127@linutronix.de> MIME-Version: 1.0 Date: Sat, 12 Aug 2023 21:58:39 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In reality CONFIG_MICROCODE is enabled in any reasonable configuration when Intel or AMD support is enabled. Accomodate to reality. Requested-by: Borislav Petkov Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 38 ----------------------------= ----- arch/x86/include/asm/microcode.h | 6 ++--- arch/x86/include/asm/microcode_amd.h | 2 - arch/x86/include/asm/microcode_intel.h | 2 - arch/x86/kernel/cpu/microcode/Makefile | 4 +-- 5 files changed, 8 insertions(+), 44 deletions(-) --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1308,44 +1308,8 @@ config X86_REBOOTFIXUPS Say N otherwise. =20 config MICROCODE - bool "CPU microcode loading support" - default y + def_bool y depends on CPU_SUP_AMD || CPU_SUP_INTEL - help - If you say Y here, you will be able to update the microcode on - Intel and AMD processors. The Intel support is for the IA32 family, - e.g. Pentium Pro, Pentium II, Pentium III, Pentium 4, Xeon etc. The - AMD support is for families 0x10 and later. You will obviously need - the actual microcode binary data itself which is not shipped with - the Linux kernel. - - The preferred method to load microcode from a detached initrd is descri= bed - in Documentation/arch/x86/microcode.rst. For that you need to enable - CONFIG_BLK_DEV_INITRD in order for the loader to be able to scan the - initrd for microcode blobs. - - In addition, you can build the microcode into the kernel. For that you - need to add the vendor-supplied microcode to the CONFIG_EXTRA_FIRMWARE - config option. - -config MICROCODE_INTEL - bool "Intel microcode loading support" - depends on CPU_SUP_INTEL && MICROCODE - default MICROCODE - help - This options enables microcode patch loading support for Intel - processors. - - For the current Intel microcode data package go to - and search for - 'Linux Processor Microcode Data File'. - -config MICROCODE_AMD - bool "AMD microcode loading support" - depends on CPU_SUP_AMD && MICROCODE - help - If you select this option, microcode patch loading support for AMD - processors will be enabled. =20 config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -54,16 +54,16 @@ struct ucode_cpu_info { extern struct ucode_cpu_info ucode_cpu_info[]; struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); =20 -#ifdef CONFIG_MICROCODE_INTEL +#ifdef CONFIG_CPU_SUP_INTEL extern struct microcode_ops * __init init_intel_microcode(void); #else static inline struct microcode_ops * __init init_intel_microcode(void) { return NULL; } -#endif /* CONFIG_MICROCODE_INTEL */ +#endif /* CONFIG_CPU_SUP_INTEL */ =20 -#ifdef CONFIG_MICROCODE_AMD +#ifdef CONFIG_CPU_SUP_AMD extern struct microcode_ops * __init init_amd_microcode(void); extern void __exit exit_amd_microcode(void); #else --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -43,7 +43,7 @@ struct microcode_amd { =20 #define PATCH_MAX_SIZE (3 * PAGE_SIZE) =20 -#ifdef CONFIG_MICROCODE_AMD +#ifdef CONFIG_CPU_SUP_AMD extern void load_ucode_amd_early(unsigned int cpuid_1_eax); extern int __init save_microcode_in_initrd_amd(unsigned int family); void reload_ucode_amd(unsigned int cpu); --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -71,7 +71,7 @@ static inline u32 intel_get_microcode_re return rev; } =20 -#ifdef CONFIG_MICROCODE_INTEL +#ifdef CONFIG_CPU_SUP_INTEL extern void __init load_ucode_intel_bsp(void); extern void load_ucode_intel_ap(void); extern void show_ucode_info_early(void); --- a/arch/x86/kernel/cpu/microcode/Makefile +++ b/arch/x86/kernel/cpu/microcode/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only microcode-y :=3D core.o obj-$(CONFIG_MICROCODE) +=3D microcode.o -microcode-$(CONFIG_MICROCODE_INTEL) +=3D intel.o -microcode-$(CONFIG_MICROCODE_AMD) +=3D amd.o +microcode-$(CONFIG_CPU_SUP_INTEL) +=3D intel.o +microcode-$(CONFIG_CPU_SUP_AMD) +=3D amd.o