From nobody Fri Dec 19 05:02:05 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13D9CC0015E for ; Fri, 11 Aug 2023 21:53:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230153AbjHKVxr (ORCPT ); Fri, 11 Aug 2023 17:53:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229734AbjHKVxo (ORCPT ); Fri, 11 Aug 2023 17:53:44 -0400 Received: from smtpdh19-su.aruba.it (smtpdh19-su.aruba.it [62.149.155.160]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C5F82712 for ; Fri, 11 Aug 2023 14:53:42 -0700 (PDT) Received: from localhost.localdomain ([95.47.160.93]) by Aruba Outgoing Smtp with ESMTPSA id Ua4Wq7aKXFroIUa4cqW64A; Fri, 11 Aug 2023 23:53:41 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1691790821; bh=sgLKTG2jgUCHzbZ0AC5kRxPygfCZIK1iFs84y1o2j2k=; h=From:To:Subject:Date:MIME-Version; b=jalyRI6EQNn6aUL6iQvydrergSSz/TqtmgKSnViuLZ3n4ZfrYvojaVfjDb2brbucT XsiQn1PcAUN6NpYnp0ZHj7etLAvFw1h5TwvX5ZCE7gERdiu4rU6cZF6ukD75BkSKKS q7pwlH1xe9/CxKryN3euiYzSnqfQJUXEIyH+jCaAAwDvylI/X96Iu4vr/FGIZeNa2V xBT1KmwdPpvJq3UJfNEGLwVQFymA+VE+zFUtwIu4DWMD+r5FkDbgZNnlYP1yza6YBu z5pvcPHLift7hYiwv9WIVXaFJ6YDt61lK604wKfhjgQ16uuOHV3WdGM0LuNk2YRaRr pX+jb5hgwIS6Q== From: Giulio Benetti To: Broadcom internal kernel review list , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Florian Fainelli , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Giulio Benetti , Jim Reinhart , James Autry , Matthew Maron Subject: [PATCH] net: phy: broadcom: add support for BCM5221 phy Date: Fri, 11 Aug 2023 23:53:22 +0200 Message-Id: <20230811215322.8679-1-giulio.benetti@benettiengineering.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfNDKmphGz4qnBWbzJRlED2AkkE0sAmkq+e+n2OZih68PFVNiooO28McspQwHO+nqr5ZeFH+4raGnERqeit6xQMtDc9IXvckGqbSQWI6oF+TV/scRqhbF MOSG5jrvLNEXZcgRdvKQ/tgt+aVsg14y91PqVPnkgmKZ2weDF+AkoqmueqEyMUdzqjEIPx9rdOFCTKQjhddO3RtvnbisJRwzTFfpHAP0GhmyKleN+bDMHPyv bLl8PbfF8raGVDilL4Ubr4DJFUO8yBt5/EUeJu6L3fff3p9bcmYeBH8MNf6f+1G6EbseyellWUoMX4A3CJNUQOSAqvF/1khAcOnRua1fKWV1wBEhdTnt/+tw HOHZi+R7UmYGurrFPJK+ZfvrXfImdacmjYIuSMrXrHcoP+OSXZ/dyggR7F9vqjpDctB4kGOJEyFRHpxUAvuGMTUhDaBwTHEkSp28y+/Nyp7a8hTrFW6/bHNO GC/bgT7uQOxZfPuWRQCkuXFlDZvywM2FoeI8BfQ96r+zPN6b72GunLt6AL65TjhljCbXbopGLwgVjEG3EOl7IjYdr1UMH/vk+j6mp4473WNSp2hqYtgIH0oK ns+vnhaN/2xjWa+F9N0rzWJEgEK136vQ2V/JQwdx2YYYOhesqEzFAl5tPX+GXQdSJbcZ/Q47DqotIDynLeZThWzlOka1G4pz4Kt67UPg3C2CTCVIPgCRPlLB 0So5HQPU8cU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds the BCM5221 PHY support by reusing brcm_fet_config_intr() and brcm_fet_handle_interrupt() and implementing config_init()/suspend()/resume(). Sponsored by: Tekvox Inc. Cc: Jim Reinhart Cc: James Autry Cc: Matthew Maron Signed-off-by: Giulio Benetti --- drivers/net/phy/broadcom.c | 144 +++++++++++++++++++++++++++++++++++++ include/linux/brcmphy.h | 8 +++ 2 files changed, 152 insertions(+) diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 59cae0d808aa..99f6c0485f01 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -754,6 +754,84 @@ static int brcm_fet_config_init(struct phy_device *phy= dev) return err; } =20 +static int bcm5221_config_init(struct phy_device *phydev) +{ + int reg, err, err2, brcmtest; + + /* Reset the PHY to bring it to a known state. */ + err =3D phy_write(phydev, MII_BMCR, BMCR_RESET); + if (err < 0) + return err; + + /* The datasheet indicates the PHY needs up to 1us to complete a reset, + * build some slack here. + */ + usleep_range(1000, 2000); + + /* The PHY requires 65 MDC clock cycles to complete a write operation + * and turnaround the line properly. + * + * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac) + * may flag the lack of turn-around as a read failure. This is + * particularly true with this combination since the MDIO controller + * only used 64 MDC cycles. This is not a critical failure in this + * specific case and it has no functional impact otherwise, so we let + * that one go through. If there is a genuine bus error, the next read + * of MII_BRCM_FET_INTREG will error out. + */ + err =3D phy_read(phydev, MII_BMCR); + if (err < 0 && err !=3D -EIO) + return err; + + reg =3D phy_read(phydev, MII_BRCM_FET_INTREG); + if (reg < 0) + return reg; + + /* Unmask events we are interested in and mask interrupts globally. */ + reg =3D MII_BRCM_FET_IR_ENABLE | + MII_BRCM_FET_IR_MASK; + + err =3D phy_write(phydev, MII_BRCM_FET_INTREG, reg); + if (err < 0) + return err; + + /* Enable auto MDIX */ + err =3D phy_clear_bits(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_DIS); + if (err < 0) + return err; + + /* Enable shadow register access */ + brcmtest =3D phy_read(phydev, MII_BRCM_FET_BRCMTEST); + if (brcmtest < 0) + return brcmtest; + + reg =3D brcmtest | MII_BRCM_FET_BT_SRE; + + err =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); + if (err < 0) + return err; + + /* Exit low power mode */ + err =3D phy_clear_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, + BCM5221_SHDW_AM4_FORCE_LPM); + if (err < 0) + goto done; + + if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { + /* Enable auto power down */ + err =3D phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, + MII_BRCM_FET_SHDW_AS2_APDE); + } + +done: + /* Disable shadow register access */ + err2 =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); + if (!err) + err =3D err2; + + return err; +} + static int brcm_fet_ack_interrupt(struct phy_device *phydev) { int reg; @@ -882,6 +960,61 @@ static int bcm54xx_phy_set_wol(struct phy_device *phyd= ev, return 0; } =20 +static int bcm5221_suspend(struct phy_device *phydev) +{ + int reg, err, err2, brcmtest; + + /* Enable shadow register access */ + brcmtest =3D phy_read(phydev, MII_BRCM_FET_BRCMTEST); + if (brcmtest < 0) + return brcmtest; + + reg =3D brcmtest | MII_BRCM_FET_BT_SRE; + + err =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); + if (err < 0) + return err; + + /* Force Low Power Mode with clock enabled */ + err =3D phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, + BCM5221_SHDW_AM4_EN_CLK_LPM | + BCM5221_SHDW_AM4_FORCE_LPM); + + /* Disable shadow register access */ + err2 =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); + if (!err) + err =3D err2; + + return err; +} + +static int bcm5221_resume(struct phy_device *phydev) +{ + int reg, err, err2, brcmtest; + + /* Enable shadow register access */ + brcmtest =3D phy_read(phydev, MII_BRCM_FET_BRCMTEST); + if (brcmtest < 0) + return brcmtest; + + reg =3D brcmtest | MII_BRCM_FET_BT_SRE; + + err =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); + if (err < 0) + return err; + + /* Exit Low Power Mode with clock enabled */ + err =3D phy_clear_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, + BCM5221_SHDW_AM4_FORCE_LPM); + + /* Disable shadow register access */ + err2 =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); + if (!err) + err =3D err2; + + return err; +} + static int bcm54xx_phy_probe(struct phy_device *phydev) { struct bcm54xx_phy_priv *priv; @@ -1208,6 +1341,16 @@ static struct phy_driver broadcom_drivers[] =3D { .handle_interrupt =3D brcm_fet_handle_interrupt, .suspend =3D brcm_fet_suspend, .resume =3D brcm_fet_config_init, +}, { + .phy_id =3D PHY_ID_BCM5221, + .phy_id_mask =3D 0xfffffff0, + .name =3D "Broadcom BCM5221", + /* PHY_BASIC_FEATURES */ + .config_init =3D bcm5221_config_init, + .config_intr =3D brcm_fet_config_intr, + .handle_interrupt =3D brcm_fet_handle_interrupt, + .suspend =3D bcm5221_suspend, + .resume =3D bcm5221_resume, }, { .phy_id =3D PHY_ID_BCM5395, .phy_id_mask =3D 0xfffffff0, @@ -1288,6 +1431,7 @@ static struct mdio_device_id __maybe_unused broadcom_= tbl[] =3D { { PHY_ID_BCM53125, 0xfffffff0 }, { PHY_ID_BCM53128, 0xfffffff0 }, { PHY_ID_BCM89610, 0xfffffff0 }, + { PHY_ID_BCM5221, 0xfffffff0 }, { } }; =20 diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 5d732f48f787..3d7786cc997d 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h @@ -12,6 +12,7 @@ #define PHY_ID_BCM50610 0x0143bd60 #define PHY_ID_BCM50610M 0x0143bd70 #define PHY_ID_BCM5241 0x0143bc30 +#define PHY_ID_BCM5221 0x004061e0 #define PHY_ID_BCMAC131 0x0143bc70 #define PHY_ID_BCM5481 0x0143bca0 #define PHY_ID_BCM5395 0x0143bcf0 @@ -330,6 +331,13 @@ =20 #define BCM54XX_WOL_INT_STATUS (MII_BCM54XX_EXP_SEL_WOL + 0x94) =20 +/* BCM5221 Registers */ +#define BCM5221_AEGSR 0x1C +#define BCM5221_AEGSR_MDIX_DIS BIT(11) + +#define BCM5221_SHDW_AM4_EN_CLK_LPM BIT(2) +#define BCM5221_SHDW_AM4_FORCE_LPM BIT(1) + /*************************************************************************= ****/ /* Fast Ethernet Transceiver definitions. */ /*************************************************************************= ****/ --=20 2.34.1