From nobody Fri Dec 19 05:04:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C12D5C001DE for ; Fri, 11 Aug 2023 19:20:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235914AbjHKTUx (ORCPT ); Fri, 11 Aug 2023 15:20:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235846AbjHKTUw (ORCPT ); Fri, 11 Aug 2023 15:20:52 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AA1A2709; Fri, 11 Aug 2023 12:20:48 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37BJKdB7061257; Fri, 11 Aug 2023 14:20:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691781639; bh=zaVqdZ0PN88/N4qBEFQ/am+8JFRVJ1v/TxbIXRAGn7I=; h=From:To:Subject:Date:In-Reply-To:References; b=RXFG2yTVMQhgvt0YxuYJ7Yjf3PsP/EEjPfvocWVQTyMp6mPvZg05pCN2G0y8iAL59 a6gqulcGMv8cOtG2FYQhRndd4UpfRKIs1AHmawIJT2LupluUHU4gIH6RGZXa6XCAKi i0VOzOiFN2O8yu1fgKGJouGthU7ViZk2wPupGGSM= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37BJKdY1088296 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 11 Aug 2023 14:20:39 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 11 Aug 2023 14:20:38 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 11 Aug 2023 14:20:38 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37BJKUFw017018; Fri, 11 Aug 2023 14:20:35 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla , Dasnavis Sabiya Subject: [PATCH v5 1/3] arm64: dts: ti: k3-j784s4: Add phase tags marking Date: Sat, 12 Aug 2023 00:50:28 +0530 Message-ID: <20230811192030.3480616-2-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230811192030.3480616-1-a-nandan@ti.com> References: <20230811192030.3480616-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. On TI K3 J784S4 SoC, only secure_proxy_mcu and secure_proxy_sa3 nodes are exclusively used by R5 bootloader, rest of the dts nodes with bootph-* are used by later boot stages also. And secure_proxy_mcu and secure_proxy_sa3 are disabled in kernel device tree, and will be only enabled in R5 bootloader device tree. So, bootph-pre-ram for secure_proxy_mcu and secure_proxy_sa3 will be added in R5 bootloader device tree only. Add bootph-all for all other nodes that are used in the bootloader on K3 J784S4 SoC, and bootph-pre-ram is not needed specifically for any node in kernel dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++ 3 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index a04c44708a09..65eca0990300 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -670,6 +670,7 @@ main_sdhci1: mmc@4fb0000 { }; =20 main_navss: bus@30000000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -705,6 +706,7 @@ main_udmass_inta: msi-controller@33d00000 { }; =20 secure_proxy_main: mailbox@32c00000 { + bootph-all; compatible =3D "ti,am654-secure-proxy"; #mbox-cells =3D <1>; reg-names =3D "target_data", "rt", "scfg"; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 740ee794d7b9..a394bef093b6 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -7,6 +7,7 @@ =20 &cbass_mcu_wakeup { sms: system-controller@44083000 { + bootph-all; compatible =3D "ti,k2g-sci"; ti,host-id =3D <12>; =20 @@ -19,22 +20,26 @@ sms: system-controller@44083000 { reg =3D <0x00 0x44083000 0x00 0x1000>; =20 k3_pds: power-controller { + bootph-all; compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; }; =20 k3_clks: clock-controller { + bootph-all; compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; }; =20 k3_reset: reset-controller { + bootph-all; compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; }; }; =20 chipid@43000014 { + bootph-all; compatible =3D "ti,am654-chipid"; reg =3D <0x00 0x43000014 0x00 0x4>; }; @@ -161,6 +166,7 @@ mcu_timer0: timer@40400000 { }; =20 mcu_timer1: timer@40410000 { + bootph-all; compatible =3D "ti,am654-timer"; reg =3D <0x00 0x40410000 0x00 0x400>; interrupts =3D ; @@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 { }; =20 mcu_navss: bus@28380000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -451,6 +458,7 @@ mcu_navss: bus@28380000 { dma-ranges; =20 mcu_ringacc: ringacc@2b800000 { + bootph-all; compatible =3D "ti,am654-navss-ringacc"; reg =3D <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, @@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 { }; =20 mcu_udmap: dma-controller@285c0000 { + bootph-all; compatible =3D "ti,j721e-navss-mcu-udmap"; reg =3D <0x00 0x285c0000 0x00 0x100>, <0x00 0x2a800000 0x00 0x40000>, diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti= /k3-j784s4.dtsi index 8b5974d92e33..4398c3a463e1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -228,6 +228,7 @@ pmu: pmu { }; =20 cbass_main: bus@100000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -263,6 +264,7 @@ cbass_main: bus@100000 { <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; =20 cbass_mcu_wakeup: bus@28380000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; --=20 2.34.1 From nobody Fri Dec 19 05:04:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5E5FC001DE for ; Fri, 11 Aug 2023 19:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235264AbjHKTU4 (ORCPT ); Fri, 11 Aug 2023 15:20:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235846AbjHKTUy (ORCPT ); Fri, 11 Aug 2023 15:20:54 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB6822709; Fri, 11 Aug 2023 12:20:52 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37BJKgH1072131; Fri, 11 Aug 2023 14:20:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691781642; bh=Ju0s913AAU7dCWvKwIm1CQKjCFcI+x8OrGmLQ7LruXs=; h=From:To:Subject:Date:In-Reply-To:References; b=yEC+SEaNxHAZjhieF0GSsZaecY1vAoHQ+thbdQiOLfIDRHvvvOdJX8uqVbWStHCv1 dCruNQMgXAMA+xkvHyvgRqXUYE/z8OdKseM566/5l5t4qOBpujRsJqTY0ZArTIAkh5 w39+9HI84BYd5nXnHYMZYiEXP6V2hgN4yP3A+B7U= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37BJKgd2002252 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 11 Aug 2023 14:20:42 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 11 Aug 2023 14:20:42 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 11 Aug 2023 14:20:42 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37BJKUFx017018; Fri, 11 Aug 2023 14:20:39 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla , Dasnavis Sabiya Subject: [PATCH v5 2/3] arm64: dts: ti: k3-j784s4-evm: Add phase tags marking Date: Sat, 12 Aug 2023 00:50:29 +0530 Message-ID: <20230811192030.3480616-3-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230811192030.3480616-1-a-nandan@ti.com> References: <20230811192030.3480616-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. wkup_i2c0, mcu_uart0, main_uart8, fss, ospi0, ospi1, main_sdhci0 and main_sdhci1 are required for bootloader operation on TI K3 J784S4 EVM. These IPs along with pinmuxes need to be marked for all bootloader phases, hence add bootph-all to these nodes in kernel dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index edc1009b2d1e..8f3d9d61cd05 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,9 @@ vdd_sd_dv: regulator-TLV71033 { }; =20 &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -269,6 +271,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0= _SDA */ }; =20 main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -289,7 +292,9 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.G= PIO0_8 */ }; =20 &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0= _CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0= _RTSn */ @@ -299,6 +304,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UA= RT0_TXD */ }; =20 wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -306,6 +312,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C= 0_SDA */ }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0= _CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART= 0_RTSn */ @@ -366,7 +373,9 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC= 1_AIN7 */ }; =20 &wkup_pmx0 { + bootph-all; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -384,7 +393,9 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSP= I0_DQS */ }; =20 &wkup_pmx1 { + bootph-all; mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ @@ -392,6 +403,7 @@ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OS= PI0_RESET_OUT0 */ }; =20 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ @@ -413,6 +425,7 @@ &wkup_uart0 { }; =20 &wkup_i2c0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_i2c0_pins_default>; @@ -426,12 +439,14 @@ eeprom@50 { }; =20 &mcu_uart0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; }; =20 &main_uart8 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart8_pins_default>; @@ -442,15 +457,18 @@ &ufs_wrapper { }; =20 &fss { + bootph-all; status =3D "okay"; }; =20 &ospi0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; =20 flash@0 { + bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <8>; @@ -498,6 +516,7 @@ partition@800000 { }; =20 partition@3fc0000 { + bootph-all; label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; }; @@ -506,11 +525,13 @@ partition@3fc0000 { }; =20 &ospi1 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; =20 flash@0 { + bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <1>; @@ -558,6 +579,7 @@ partition@800000 { }; =20 partition@3fc0000 { + bootph-all; label =3D "qspi.phypattern"; reg =3D <0x3fc0000 0x40000>; }; @@ -602,6 +624,7 @@ exp2: gpio@22 { }; =20 &main_sdhci0 { + bootph-all; /* eMMC */ status =3D "okay"; non-removable; @@ -610,6 +633,7 @@ &main_sdhci0 { }; =20 &main_sdhci1 { + bootph-all; /* SD card */ status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; --=20 2.34.1 From nobody Fri Dec 19 05:04:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D44C6C04A6A for ; Fri, 11 Aug 2023 19:21:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236591AbjHKTVE (ORCPT ); Fri, 11 Aug 2023 15:21:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236356AbjHKTU5 (ORCPT ); Fri, 11 Aug 2023 15:20:57 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0B6030F5; Fri, 11 Aug 2023 12:20:54 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37BJKkdl076713; Fri, 11 Aug 2023 14:20:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691781646; bh=NMZJFqRptjOGyYxfyMicO73PRliWXF8UGL1ScHO5ztg=; h=From:To:Subject:Date:In-Reply-To:References; b=wl8j6LkkSvqbDMgGkJaSrMeETyrRm7OFTl1VdeDKKungKNADXFLoZ8DwfFZddmKfv 3uHwtQU7w5aaRq/cO+RQsewa1uL4RmriSHKxvpC4DnA1+hSVQza/0PGy5QUNyYas1t 2H2AVfwHGPYGK5f0AdovlaXHAK4wxk214aaEBc2A= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37BJKkpm088342 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 11 Aug 2023 14:20:46 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 11 Aug 2023 14:20:46 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 11 Aug 2023 14:20:45 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37BJKUG0017018; Fri, 11 Aug 2023 14:20:42 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla , Dasnavis Sabiya Subject: [PATCH v5 3/3] arm64: dts: ti: k3-am69-sk: Add phase tags marking Date: Sat, 12 Aug 2023 00:50:30 +0530 Message-ID: <20230811192030.3480616-4-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230811192030.3480616-1-a-nandan@ti.com> References: <20230811192030.3480616-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. wkup_i2c0, mcu_uart0, main_uart8, main_sdhci0 and main_sdhci1 are required for bootloader operation on TI K3 AM69-SK EVM. These IPs along with pinmuxes need to be marked for all bootloader phases, hence add bootph-all to these nodes in kernel dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index d282c2c633c1..06993709111e 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -110,7 +110,9 @@ vdd_sd_dv: regulator-tlv71033 { }; =20 &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ @@ -125,6 +127,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0= _SDA */ }; =20 main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -164,7 +167,9 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.G= PIO0_1 */ }; =20 &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0= _CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0= _RTSn */ @@ -174,6 +179,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UA= RT0_TXD */ }; =20 wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -181,6 +187,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C= 0_SDA */ }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0= _RXD */ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART= 0_TXD */ @@ -249,6 +256,7 @@ &wkup_uart0 { }; =20 &wkup_i2c0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_i2c0_pins_default>; @@ -268,6 +276,7 @@ &wkup_gpio0 { }; =20 &mcu_uart0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; @@ -281,6 +290,7 @@ &mcu_i2c0 { }; =20 &main_uart8 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart8_pins_default>; @@ -307,6 +317,7 @@ exp1: gpio@21 { }; =20 &main_sdhci0 { + bootph-all; /* eMMC */ status =3D "okay"; non-removable; @@ -315,6 +326,7 @@ &main_sdhci0 { }; =20 &main_sdhci1 { + bootph-all; /* SD card */ status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; --=20 2.34.1