From nobody Fri Sep 12 07:29:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57FA8C41513 for ; Fri, 11 Aug 2023 19:01:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235573AbjHKTBM (ORCPT ); Fri, 11 Aug 2023 15:01:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233953AbjHKTBJ (ORCPT ); Fri, 11 Aug 2023 15:01:09 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAB1530CF; Fri, 11 Aug 2023 12:01:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691780469; x=1723316469; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JvC5ybwWd2s2QwBOcdZZsCQYPiTGu+dFmBHjemTdC1g=; b=ETD7oddRuH80MOGWTzgTcw/aFSQdzCaLVcKbQaMHHrwuJMvq1QhEAh5J ulkZLFdGhSfO6DpQiFFn7sPviik4OuR3jajwc+pdGEECRBi+SJ+SulwVS unoxzQ68XufeX2AwPgA7WxAonsc0ZwhjUUuWfKoVuaOlCYvdmsrIMUMrI b4/JBttf7VRQeR94wtru9etd05Wk0NerVdP2SRKT+MMju9QiMYpJFSCdl LLAPhlg+IVYesj2CMMM+H8EK7AJg+mksX4t0b1u3QwgQmWZOYP7EtBveG SgIHK3Y2qj3jTYLZibcIap+B7cTaYilwAd1GV+wppDMu0HIyF1a91zG97 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10799"; a="402718877" X-IronPort-AV: E=Sophos;i="6.01,166,1684825200"; d="scan'208";a="402718877" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2023 12:00:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10799"; a="802768053" X-IronPort-AV: E=Sophos;i="6.01,166,1684825200"; d="scan'208";a="802768053" Received: from pglc00052.png.intel.com ([10.221.207.72]) by fmsmga004.fm.intel.com with ESMTP; 11 Aug 2023 12:00:44 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next v2 1/2] dt-bindings: net: snps,dwmac: Tx queues with coe Date: Sat, 12 Aug 2023 03:00:31 +0800 Message-Id: <20230811190032.13391-2-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20230811190032.13391-1-rohan.g.thomas@intel.com> References: <20230810150328.19704-1-rohan.g.thomas@intel.com> <20230811190032.13391-1-rohan.g.thomas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt-bindings for the number of tx queues with coe support. Some dwmac IPs support tx queues only for a few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index ddf9522a5dc2..0c6431c10cf9 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -313,6 +313,9 @@ properties: snps,tx-queues-to-use: $ref: /schemas/types.yaml#/definitions/uint32 description: number of TX queues to be used in the driver + snps,tx-queues-with-coe: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of TX queues that support TX checksum offloadi= ng snps,tx-sched-wrr: type: boolean description: Weighted Round Robin --=20 2.19.0 From nobody Fri Sep 12 07:29:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37B9AC04A6A for ; Fri, 11 Aug 2023 19:01:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235697AbjHKTBc (ORCPT ); Fri, 11 Aug 2023 15:01:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235234AbjHKTB2 (ORCPT ); Fri, 11 Aug 2023 15:01:28 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01DC730F3; Fri, 11 Aug 2023 12:01:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691780487; x=1723316487; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k+MHekhYBs3WdAqPDc1G+2v4ip6Z4JNaBx70Obb3qiI=; b=jeRh9VS82BzcnYcVqQMrKBI9UHSWlOM0ZuWBtAYMo9L9g0hJLv7p/tKP VswrYqSNQPB3DaiMK8DDOelh+HITh5edYV80j5kVek9ernOkfwgAZ7bXs XmaxJnN6vhvWP8kGWBX809b+sRErAsmy8NGDHI41ooGTUWrl7G13fWH+u mWeIGt5lmmc//vrDmxGPC9+jbsMAvcWpFiGDxPkpdNaglUTbEikMPVJkn NmvAxGjz+G/4n/ID36vCA87k4l5S2CY6awVVok8/Nkru1YZDWF1leBJi6 3ralR0LtYdeM1rBvgAmmh1vrKT7NvziykwlvFbIFLbn1YLp2dBbcOoh47 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10799"; a="402719006" X-IronPort-AV: E=Sophos;i="6.01,166,1684825200"; d="scan'208";a="402719006" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2023 12:00:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10799"; a="802768096" X-IronPort-AV: E=Sophos;i="6.01,166,1684825200"; d="scan'208";a="802768096" Received: from pglc00052.png.intel.com ([10.221.207.72]) by fmsmga004.fm.intel.com with ESMTP; 11 Aug 2023 12:00:50 -0700 From: Rohan G Thomas To: "David S . Miller" , Alexandre Torgue , Jose Abreu , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas Subject: [PATCH net-next v2 2/2] net: stmmac: Tx coe sw fallback Date: Sat, 12 Aug 2023 03:00:32 +0800 Message-Id: <20230811190032.13391-3-rohan.g.thomas@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20230811190032.13391-1-rohan.g.thomas@intel.com> References: <20230810150328.19704-1-rohan.g.thomas@intel.com> <20230811190032.13391-1-rohan.g.thomas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add sw fallback of tx checksum calculation for those tx queues that don't support tx checksum offloading. Because, some DWMAC IPs support tx checksum offloading only for a few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 19 +++++++++++++++++++ .../ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++++ include/linux/stmmac.h | 1 + 4 files changed, 26 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/eth= ernet/stmicro/stmmac/stmmac.h index 3401e888a9f6..f526bcaaaf64 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -219,6 +219,8 @@ struct stmmac_priv { int hwts_tx_en; bool tx_path_in_lpi_mode; bool tso; + bool tx_q_coe_lmt; + u32 tx_q_with_coe; int sph; int sph_cap; u32 sarc_type; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index fcab363d8dfa..cb8d2c159832 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4409,6 +4409,17 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, = struct net_device *dev) WARN_ON(tx_q->tx_skbuff[first_entry]); =20 csum_insertion =3D (skb->ip_summed =3D=3D CHECKSUM_PARTIAL); + /* Some DWMAC IPs support tx coe only for a few initial tx queues, + * starting from tx queue 0. So checksum offloading for those queues + * that don't support tx coe needs to fallback to software checksum + * calculation. + */ + if (csum_insertion && priv->tx_q_coe_lmt && + queue >=3D priv->tx_q_with_coe) { + if (unlikely(skb_checksum_help(skb))) + goto dma_map_err; + csum_insertion =3D !csum_insertion; + } =20 if (likely(priv->extend_desc)) desc =3D (struct dma_desc *)(tx_q->dma_etx + entry); @@ -7386,6 +7397,14 @@ int stmmac_dvr_probe(struct device *device, dev_info(priv->device, "SPH feature enabled\n"); } =20 + if (priv->plat->tx_coe && + priv->plat->tx_queues_with_coe < priv->plat->tx_queues_to_use) { + priv->tx_q_coe_lmt =3D true; + priv->tx_q_with_coe =3D priv->plat->tx_queues_with_coe; + dev_info(priv->device, "TX COE limited to %u tx queues\n", + priv->tx_q_with_coe); + } + /* Ideally our host DMA address width is the same as for the * device. However, it may differ and then we have to use our * host DMA width for allocation and the device DMA width for diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/driver= s/net/ethernet/stmicro/stmmac/stmmac_platform.c index be8e79c7aa34..0138b7c9c7ab 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -225,6 +225,10 @@ static int stmmac_mtl_setup(struct platform_device *pd= ev, &plat->tx_queues_to_use)) plat->tx_queues_to_use =3D 1; =20 + if (of_property_read_u32(tx_node, "snps,tx-queues-with-coe", + &plat->tx_queues_with_coe)) + plat->tx_queues_with_coe =3D plat->tx_queues_to_use; + if (of_property_read_bool(tx_node, "snps,tx-sched-wrr")) plat->tx_sched_algorithm =3D MTL_TX_ALGORITHM_WRR; else if (of_property_read_bool(tx_node, "snps,tx-sched-wfq")) diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 652404c03944..795c10d19c1c 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -252,6 +252,7 @@ struct plat_stmmacenet_data { u32 host_dma_width; u32 rx_queues_to_use; u32 tx_queues_to_use; + u32 tx_queues_with_coe; u8 rx_sched_algorithm; u8 tx_sched_algorithm; struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; --=20 2.19.0