From nobody Mon Feb 9 09:33:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4778CC001DE for ; Thu, 10 Aug 2023 18:43:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236071AbjHJSnb (ORCPT ); Thu, 10 Aug 2023 14:43:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235835AbjHJSnZ (ORCPT ); Thu, 10 Aug 2023 14:43:25 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E6252706; Thu, 10 Aug 2023 11:43:24 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37AIhHps121416; Thu, 10 Aug 2023 13:43:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691692997; bh=NcLSLiYp6xIRmNfFraZG8gPx5ogmtaYPBvsa7EFF1uc=; h=From:To:Subject:Date:In-Reply-To:References; b=RpaKuSea/sn322qTkQrhIjRuGR0t6FKjJuttjdXZwd/qDVRuDm2MXoaZZ6WVhyLsc 1QkmrWTKzmczn+TVF4jIhkfAY+ysGfYpZ1L966FagHiW8kh/FZwdECKg8ajQGeBSn/ Su70kJt7HnX7vyxgnFe36t+psFG17t5mKVySxVKM= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37AIhHX4110201 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Aug 2023 13:43:17 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 10 Aug 2023 13:43:17 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 10 Aug 2023 13:43:17 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37AIh2P2025724; Thu, 10 Aug 2023 13:43:14 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla , Dasnavis Sabiya Subject: [PATCH v3 3/3] arm64: dts: ti: k3-am69-sk: Add bootph-all property Date: Fri, 11 Aug 2023 00:13:02 +0530 Message-ID: <20230810184302.3097829-4-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810184302.3097829-1-a-nandan@ti.com> References: <20230810184302.3097829-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bootph-all property for all the nodes that are used in SPL stage along with later boot stages. These bootph-all property will be synced later to u-boot k3-am69 dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index d282c2c633c1..2302d55c3fe7 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -110,7 +110,9 @@ vdd_sd_dv: regulator-tlv71033 { }; =20 &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ @@ -125,6 +127,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0= _SDA */ }; =20 main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -164,7 +167,9 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.G= PIO0_1 */ }; =20 &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0= _CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0= _RTSn */ @@ -174,6 +179,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UA= RT0_TXD */ }; =20 wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -181,6 +187,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C= 0_SDA */ }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0= _RXD */ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART= 0_TXD */ @@ -242,6 +249,7 @@ J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO= 0_49 */ }; =20 &wkup_uart0 { + bootph-all; /* Firmware usage */ status =3D "reserved"; pinctrl-names =3D "default"; @@ -249,6 +257,7 @@ &wkup_uart0 { }; =20 &wkup_i2c0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_i2c0_pins_default>; @@ -268,6 +277,7 @@ &wkup_gpio0 { }; =20 &mcu_uart0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; @@ -281,6 +291,7 @@ &mcu_i2c0 { }; =20 &main_uart8 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart8_pins_default>; @@ -307,6 +318,7 @@ exp1: gpio@21 { }; =20 &main_sdhci0 { + bootph-all; /* eMMC */ status =3D "okay"; non-removable; @@ -315,6 +327,7 @@ &main_sdhci0 { }; =20 &main_sdhci1 { + bootph-all; /* SD card */ status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; --=20 2.34.1