From nobody Mon Feb 9 06:00:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C47FC04A6A for ; Thu, 10 Aug 2023 18:43:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235896AbjHJSnY (ORCPT ); Thu, 10 Aug 2023 14:43:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235789AbjHJSnT (ORCPT ); Thu, 10 Aug 2023 14:43:19 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CC732719; Thu, 10 Aug 2023 11:43:18 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37AIhAlL130401; Thu, 10 Aug 2023 13:43:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691692990; bh=G/Ilz1BwP64dns4t4KrEEVpriH9lFWJB8XpQO40AeS4=; h=From:To:Subject:Date:In-Reply-To:References; b=gXzIhtIouURysfiD0q4yiNca/yZEDN963kaFMseijbN+HWGKPjV2vl1J/TZbWl54y teEbeRodf6+mwl6abJZ0IKnSas2h6qQq7P/TEKEy0GDxXtNejx+5SXgt3rHTyIkRxD eKsRt7hqihTl+Z/Ys7PtK0LsdhdiL8CFv1tIRPak= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37AIhAvt031723 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Aug 2023 13:43:10 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 10 Aug 2023 13:43:10 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 10 Aug 2023 13:43:09 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37AIh2P0025724; Thu, 10 Aug 2023 13:43:06 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla , Dasnavis Sabiya Subject: [PATCH v3 1/3] arm64: dts: ti: k3-j784s4: Add bootph-all property Date: Fri, 11 Aug 2023 00:13:00 +0530 Message-ID: <20230810184302.3097829-2-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810184302.3097829-1-a-nandan@ti.com> References: <20230810184302.3097829-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" bootph-all phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to overcome u-boot dts challenges. Add bootph-all property for all the nodes that are also used in SPL stage along with later boot stages. These bootph-all properties will be synced later to u-boot j784s4 dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++ 3 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index a04c44708a09..65eca0990300 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -670,6 +670,7 @@ main_sdhci1: mmc@4fb0000 { }; =20 main_navss: bus@30000000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -705,6 +706,7 @@ main_udmass_inta: msi-controller@33d00000 { }; =20 secure_proxy_main: mailbox@32c00000 { + bootph-all; compatible =3D "ti,am654-secure-proxy"; #mbox-cells =3D <1>; reg-names =3D "target_data", "rt", "scfg"; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 740ee794d7b9..a394bef093b6 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -7,6 +7,7 @@ =20 &cbass_mcu_wakeup { sms: system-controller@44083000 { + bootph-all; compatible =3D "ti,k2g-sci"; ti,host-id =3D <12>; =20 @@ -19,22 +20,26 @@ sms: system-controller@44083000 { reg =3D <0x00 0x44083000 0x00 0x1000>; =20 k3_pds: power-controller { + bootph-all; compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; }; =20 k3_clks: clock-controller { + bootph-all; compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; }; =20 k3_reset: reset-controller { + bootph-all; compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; }; }; =20 chipid@43000014 { + bootph-all; compatible =3D "ti,am654-chipid"; reg =3D <0x00 0x43000014 0x00 0x4>; }; @@ -161,6 +166,7 @@ mcu_timer0: timer@40400000 { }; =20 mcu_timer1: timer@40410000 { + bootph-all; compatible =3D "ti,am654-timer"; reg =3D <0x00 0x40410000 0x00 0x400>; interrupts =3D ; @@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 { }; =20 mcu_navss: bus@28380000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -451,6 +458,7 @@ mcu_navss: bus@28380000 { dma-ranges; =20 mcu_ringacc: ringacc@2b800000 { + bootph-all; compatible =3D "ti,am654-navss-ringacc"; reg =3D <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, @@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 { }; =20 mcu_udmap: dma-controller@285c0000 { + bootph-all; compatible =3D "ti,j721e-navss-mcu-udmap"; reg =3D <0x00 0x285c0000 0x00 0x100>, <0x00 0x2a800000 0x00 0x40000>, diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti= /k3-j784s4.dtsi index 8b5974d92e33..4398c3a463e1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -228,6 +228,7 @@ pmu: pmu { }; =20 cbass_main: bus@100000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -263,6 +264,7 @@ cbass_main: bus@100000 { <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; =20 cbass_mcu_wakeup: bus@28380000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; --=20 2.34.1 From nobody Mon Feb 9 06:00:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63EE2C001DE for ; Thu, 10 Aug 2023 18:43:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236012AbjHJSn3 (ORCPT ); Thu, 10 Aug 2023 14:43:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235890AbjHJSnX (ORCPT ); Thu, 10 Aug 2023 14:43:23 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6351926B7; Thu, 10 Aug 2023 11:43:22 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37AIhE6V130408; Thu, 10 Aug 2023 13:43:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691692994; bh=FLhchQ2m+WzhpqN55+mc2NN5USfwYopLY3T+X5JxIUA=; h=From:To:Subject:Date:In-Reply-To:References; b=sTE7JrDaD5DEyv3Ty3tM78q0N4Z288D35/AlD6uBkAJYHs2Ptbgfv/9ImYzlxBCvH oYxUAtwtdZDmnJ4Bi1s/JmREB0QZZizxUWCYitUukjXORPJ6exEVUm+seAqNEZ/rBd Nr5ImBr1SPySsCvLaO/QoZ7oRWDFXV6Rc9GaAim4= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37AIhEs5031759 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Aug 2023 13:43:14 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 10 Aug 2023 13:43:13 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 10 Aug 2023 13:43:13 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37AIh2P1025724; Thu, 10 Aug 2023 13:43:10 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla , Dasnavis Sabiya Subject: [PATCH v3 2/3] arm64: dts: ti: k3-j784s4-evm: Add bootph-all property Date: Fri, 11 Aug 2023 00:13:01 +0530 Message-ID: <20230810184302.3097829-3-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810184302.3097829-1-a-nandan@ti.com> References: <20230810184302.3097829-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bootph-all property for all the nodes that are used in SPL stage along with later boot stages. These bootph-all properties will be synced later to u-boot j784s4 dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index edc1009b2d1e..47d41d60e49a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,9 @@ vdd_sd_dv: regulator-TLV71033 { }; =20 &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -269,6 +271,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0= _SDA */ }; =20 main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -289,7 +292,9 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.G= PIO0_8 */ }; =20 &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0= _CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0= _RTSn */ @@ -299,6 +304,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UA= RT0_TXD */ }; =20 wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -306,6 +312,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C= 0_SDA */ }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0= _CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART= 0_RTSn */ @@ -366,7 +373,9 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC= 1_AIN7 */ }; =20 &wkup_pmx0 { + bootph-all; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -384,7 +393,9 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSP= I0_DQS */ }; =20 &wkup_pmx1 { + bootph-all; mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ @@ -392,6 +403,7 @@ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OS= PI0_RESET_OUT0 */ }; =20 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ @@ -406,6 +418,7 @@ J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSP= I1_LBCLKO */ }; =20 &wkup_uart0 { + bootph-all; /* Firmware usage */ status =3D "reserved"; pinctrl-names =3D "default"; @@ -413,6 +426,7 @@ &wkup_uart0 { }; =20 &wkup_i2c0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_i2c0_pins_default>; @@ -426,12 +440,14 @@ eeprom@50 { }; =20 &mcu_uart0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; }; =20 &main_uart8 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart8_pins_default>; @@ -442,15 +458,18 @@ &ufs_wrapper { }; =20 &fss { + bootph-all; status =3D "okay"; }; =20 &ospi0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_def= ault>; =20 flash@0 { + bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <8>; @@ -498,6 +517,7 @@ partition@800000 { }; =20 partition@3fc0000 { + bootph-all; label =3D "ospi.phypattern"; reg =3D <0x3fc0000 0x40000>; }; @@ -506,11 +526,13 @@ partition@3fc0000 { }; =20 &ospi1 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; =20 flash@0 { + bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0x0>; spi-tx-bus-width =3D <1>; @@ -558,6 +580,7 @@ partition@800000 { }; =20 partition@3fc0000 { + bootph-all; label =3D "qspi.phypattern"; reg =3D <0x3fc0000 0x40000>; }; @@ -602,6 +625,7 @@ exp2: gpio@22 { }; =20 &main_sdhci0 { + bootph-all; /* eMMC */ status =3D "okay"; non-removable; @@ -610,6 +634,7 @@ &main_sdhci0 { }; =20 &main_sdhci1 { + bootph-all; /* SD card */ status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; --=20 2.34.1 From nobody Mon Feb 9 06:00:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4778CC001DE for ; Thu, 10 Aug 2023 18:43:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236071AbjHJSnb (ORCPT ); Thu, 10 Aug 2023 14:43:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235835AbjHJSnZ (ORCPT ); Thu, 10 Aug 2023 14:43:25 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E6252706; Thu, 10 Aug 2023 11:43:24 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37AIhHps121416; Thu, 10 Aug 2023 13:43:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691692997; bh=NcLSLiYp6xIRmNfFraZG8gPx5ogmtaYPBvsa7EFF1uc=; h=From:To:Subject:Date:In-Reply-To:References; b=RpaKuSea/sn322qTkQrhIjRuGR0t6FKjJuttjdXZwd/qDVRuDm2MXoaZZ6WVhyLsc 1QkmrWTKzmczn+TVF4jIhkfAY+ysGfYpZ1L966FagHiW8kh/FZwdECKg8ajQGeBSn/ Su70kJt7HnX7vyxgnFe36t+psFG17t5mKVySxVKM= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37AIhHX4110201 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Aug 2023 13:43:17 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 10 Aug 2023 13:43:17 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 10 Aug 2023 13:43:17 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37AIh2P2025724; Thu, 10 Aug 2023 13:43:14 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla , Dasnavis Sabiya Subject: [PATCH v3 3/3] arm64: dts: ti: k3-am69-sk: Add bootph-all property Date: Fri, 11 Aug 2023 00:13:02 +0530 Message-ID: <20230810184302.3097829-4-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810184302.3097829-1-a-nandan@ti.com> References: <20230810184302.3097829-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bootph-all property for all the nodes that are used in SPL stage along with later boot stages. These bootph-all property will be synced later to u-boot k3-am69 dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index d282c2c633c1..2302d55c3fe7 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -110,7 +110,9 @@ vdd_sd_dv: regulator-tlv71033 { }; =20 &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ @@ -125,6 +127,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0= _SDA */ }; =20 main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -164,7 +167,9 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.G= PIO0_1 */ }; =20 &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0= _CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0= _RTSn */ @@ -174,6 +179,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UA= RT0_TXD */ }; =20 wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins =3D < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -181,6 +187,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C= 0_SDA */ }; =20 mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0= _RXD */ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART= 0_TXD */ @@ -242,6 +249,7 @@ J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO= 0_49 */ }; =20 &wkup_uart0 { + bootph-all; /* Firmware usage */ status =3D "reserved"; pinctrl-names =3D "default"; @@ -249,6 +257,7 @@ &wkup_uart0 { }; =20 &wkup_i2c0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_i2c0_pins_default>; @@ -268,6 +277,7 @@ &wkup_gpio0 { }; =20 &mcu_uart0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_uart0_pins_default>; @@ -281,6 +291,7 @@ &mcu_i2c0 { }; =20 &main_uart8 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart8_pins_default>; @@ -307,6 +318,7 @@ exp1: gpio@21 { }; =20 &main_sdhci0 { + bootph-all; /* eMMC */ status =3D "okay"; non-removable; @@ -315,6 +327,7 @@ &main_sdhci0 { }; =20 &main_sdhci1 { + bootph-all; /* SD card */ status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; --=20 2.34.1