From nobody Sun Feb 8 23:25:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C574C001DE for ; Thu, 10 Aug 2023 18:38:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235895AbjHJSix (ORCPT ); Thu, 10 Aug 2023 14:38:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235722AbjHJSiV (ORCPT ); Thu, 10 Aug 2023 14:38:21 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95BC92D76 for ; Thu, 10 Aug 2023 11:38:04 -0700 (PDT) Message-ID: <20230810160805.934494281@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1691692671; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RyAZdhYUiy48Y/XZU7T04DGYjgBzGOlb8fG6vAh+kH8=; b=objlsPC5h9djIldT3K9DGzT6gg0Gle0YRmjhie3pkoZHJ2J+liU8y+mBf3odMvKlaCy5UI Y6+thqLLndVAKigGdlGRI5Baokm5s9+H+SO9Q9akkF+UzY74KD1CP6K4fkWlqazTlPSWc9 ixvambj9dX8vLV/+ghEs8p2bzTofBgsDRc93C1EfBVpXuIc2UNXYyGQexDqaAlbV9/G5CR XGJ556PQWbWZVehUtfUZyUIapN4+fXVbZWmV1M6Aqkz2y4hjTmOGg7h0wityLnG5qQ19qF Ectzb7jJvOvohZH3H3kCIzf3b7TzJTNq24Pg6DF6Jd3YpFX+AdqGvcNrpFKVrg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1691692671; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RyAZdhYUiy48Y/XZU7T04DGYjgBzGOlb8fG6vAh+kH8=; b=aNLvWxACY/b8sKvBkd5MAE6FupxaDbd0VrSDoAmdtpxcs4HLLKIrJiwdEyiKY/BjIQ/eXW 9LztDo1ftqSkDlBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj , Arjan van de Ven Subject: [patch 17/30] x86/microcode/intel: Unify microcode apply() functions References: <20230810153317.850017756@linutronix.de> MIME-Version: 1.0 Date: Thu, 10 Aug 2023 20:37:51 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Deduplicate the early and late apply() functions. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 106 +++++++++++------------------= ----- 1 file changed, 36 insertions(+), 70 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -325,12 +325,11 @@ static inline void print_ucode(int old_r } #endif =20 -static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci, = bool early) +static enum ucode_state apply_microcode(struct ucode_cpu_info *uci, struct= microcode_intel *mc, + u32 *cur_rev) { - struct microcode_intel *mc; - u32 rev, old_rev; + u32 rev; =20 - mc =3D uci->mc; if (!mc) return UCODE_NFOUND; =20 @@ -339,14 +338,12 @@ static enum ucode_state apply_microcode_ * operation - when the other hyperthread has updated the microcode * already. */ - rev =3D intel_get_microcode_revision(); - if (rev >=3D mc->hdr.rev) { - uci->cpu_sig.rev =3D rev; + *cur_rev =3D intel_get_microcode_revision(); + if (*cur_rev >=3D mc->hdr.rev) { + uci->cpu_sig.rev =3D *cur_rev; return UCODE_OK; } =20 - old_rev =3D rev; - /* * Writeback and invalidate caches before updating microcode to avoid * internal issues depending on what the microcode is updating. @@ -361,13 +358,23 @@ static enum ucode_state apply_microcode_ return UCODE_ERROR; =20 uci->cpu_sig.rev =3D rev; + return UCODE_UPDATED; +} =20 - if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); - else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci, = bool early) +{ + struct microcode_intel *mc =3D uci->mc; + enum ucode_state ret; + u32 cur_rev; =20 - return UCODE_UPDATED; + ret =3D apply_microcode(uci, mc, &cur_rev); + if (ret =3D=3D UCODE_UPDATED) { + if (early) + print_ucode(cur_rev, uci->cpu_sig.rev, mc->hdr.date); + else + print_ucode_info(cur_rev, uci->cpu_sig.rev, mc->hdr.date); + } + return ret; } =20 static __init bool load_builtin_intel_microcode(struct cpio_data *cp) @@ -508,70 +515,29 @@ static int collect_cpu_info(int cpu_num, return 0; } =20 -static enum ucode_state apply_microcode_intel(int cpu) +static enum ucode_state apply_microcode_late(int cpu) { struct ucode_cpu_info *uci =3D ucode_cpu_info + cpu; - struct cpuinfo_x86 *c =3D &cpu_data(cpu); - bool bsp =3D c->cpu_index =3D=3D boot_cpu_data.cpu_index; - struct microcode_intel *mc; + struct microcode_intel *mc =3D ucode_patch_late; enum ucode_state ret; - static int prev_rev; - u32 rev; - - /* We should bind the task to the CPU */ - if (WARN_ON(raw_smp_processor_id() !=3D cpu)) - return UCODE_ERROR; - - mc =3D ucode_patch_late; - if (!mc) - return UCODE_NFOUND; + u32 cur_rev; =20 - /* - * Save us the MSR write below - which is a particular expensive - * operation - when the other hyperthread has updated the microcode - * already. - */ - rev =3D intel_get_microcode_revision(); - if (rev >=3D mc->hdr.rev) { - ret =3D UCODE_OK; - goto out; - } - - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - - /* write microcode via MSR 0x79 */ - wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); - - rev =3D intel_get_microcode_revision(); - - if (rev !=3D mc->hdr.rev) { - pr_err("CPU%d update to revision 0x%x failed\n", - cpu, mc->hdr.rev); + if (WARN_ON_ONCE(smp_processor_id() !=3D cpu)) return UCODE_ERROR; - } =20 - if (bsp && rev !=3D prev_rev) { - pr_info("updated to revision 0x%x, date =3D %04x-%02x-%02x\n", - rev, - mc->hdr.date & 0xffff, - mc->hdr.date >> 24, + ret =3D apply_microcode(uci, mc, &cur_rev); + if (ret !=3D UCODE_UPDATED && ret !=3D UCODE_OK) + return ret; + + if (!cpu && uci->cpu_sig.rev !=3D cur_rev) { + pr_info("Updated to revision 0x%x, date =3D %04x-%02x-%02x\n", + uci->cpu_sig.rev, mc->hdr.date & 0xffff, mc->hdr.date >> 24, (mc->hdr.date >> 16) & 0xff); - prev_rev =3D rev; } =20 - ret =3D UCODE_UPDATED; - -out: - uci->cpu_sig.rev =3D rev; - c->microcode =3D rev; - - /* Update boot_cpu_data's revision too, if we're on the BSP: */ - if (bsp) - boot_cpu_data.microcode =3D rev; + cpu_data(cpu).microcode =3D uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode =3D uci->cpu_sig.rev; =20 return ret; } @@ -718,7 +684,7 @@ static void finalize_late_load(int resul static struct microcode_ops microcode_intel_ops =3D { .request_microcode_fw =3D request_microcode_fw, .collect_cpu_info =3D collect_cpu_info, - .apply_microcode =3D apply_microcode_intel, + .apply_microcode =3D apply_microcode_late, .finalize_late_load =3D finalize_late_load, };