From nobody Mon Feb 9 16:08:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1F7EC04A6A for ; Thu, 10 Aug 2023 16:13:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236667AbjHJQNh (ORCPT ); Thu, 10 Aug 2023 12:13:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236765AbjHJQNM (ORCPT ); Thu, 10 Aug 2023 12:13:12 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88AB54216 for ; Thu, 10 Aug 2023 09:04:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=oaPPgI4MashoQdDxkkKwWaQcDqhEIAnnmpGRJpRzwzI=; b=QXkGrPaQKwo1SsNQ9e0LLubWkg OlghZ1URClqKPyPJyg0h73Rxp6PLiVmIfRASw3DHovCPuli6+33SLv43XcLj49L3YctvIBUZasiuT dM82KFLKypPcg78P7z/x/XR3yfINSYFfu7x7YrWC+RsxpnPRN79iApfFDvTBwRAYnhiqCWehp9dRw GW69NX1oLOIshRFy7eQbm6Z+eu0PhdglorRYAkqhgG9rw6ZWbTPNI3TPPgpenzZIuU41O8/QH6nxk mtNtwj0Z3l7Cexltmvt4zbHz9nZmVl62zxtzkIyxxEFwF3ZzAbqbTi+7VzOuUZTSWdmUnu03ffxBa 9drFb0Gg==; Received: from [38.44.68.151] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1qU89B-00GjYD-8X; Thu, 10 Aug 2023 18:04:25 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Pekka Paalanen , Simon Ser , kernel-dev@igalia.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 31/34] drm/amd/display: set stream gamut remap matrix to MPC for DCN301 Date: Thu, 10 Aug 2023 15:03:11 -0100 Message-Id: <20230810160314.48225-32-mwen@igalia.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230810160314.48225-1-mwen@igalia.com> References: <20230810160314.48225-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" dc->caps.color.mpc.gamut_remap says there is a post-blending color block for gamut remap matrix for DCN3 HW family and newer versions. However, those drivers still follow DCN10 programming that remap stream gamut_remap_matrix to DPP (pre-blending). To enable pre-blending and post-blending gamut_remap matrix supports at the same time, set stream gamut_remap to MPC and plane gamut_remap to DPP for DCN301 that support both. It was tested using IGT KMS color tests for DRM CRTC CTM property and it preserves test results. Signed-off-by: Melissa Wen --- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 37 +++++++++++++++++++ .../drm/amd/display/dc/dcn30/dcn30_hwseq.h | 3 ++ .../drm/amd/display/dc/dcn301/dcn301_init.c | 2 +- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/g= pu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 4cd4ae07d73d..4fb4e9ec03f1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -186,6 +186,43 @@ bool dcn30_set_input_transfer_func(struct dc *dc, return result; } =20 +void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx) +{ + int i =3D 0; + struct dpp_grph_csc_adjustment dpp_adjust; + struct mpc_grph_gamut_adjustment mpc_adjust; + int mpcc_id =3D pipe_ctx->plane_res.hubp->inst; + struct mpc *mpc =3D pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; + + memset(&dpp_adjust, 0, sizeof(dpp_adjust)); + dpp_adjust.gamut_adjust_type =3D GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; + + if (pipe_ctx->plane_state && + pipe_ctx->plane_state->gamut_remap_matrix.enable_remap =3D=3D true) { + dpp_adjust.gamut_adjust_type =3D GRAPHICS_GAMUT_ADJUST_TYPE_SW; + for (i =3D 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) + dpp_adjust.temperature_matrix[i] =3D + pipe_ctx->plane_state->gamut_remap_matrix.matrix[i]; + } + + pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.d= pp, + &dpp_adjust); + + memset(&mpc_adjust, 0, sizeof(mpc_adjust)); + mpc_adjust.gamut_adjust_type =3D GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; + + if (pipe_ctx->top_pipe =3D=3D NULL) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap =3D=3D true) { + mpc_adjust.gamut_adjust_type =3D GRAPHICS_GAMUT_ADJUST_TYPE_SW; + for (i =3D 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) + mpc_adjust.temperature_matrix[i] =3D + pipe_ctx->stream->gamut_remap_matrix.matrix[i]; + } + } + + mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust); +} + bool dcn30_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/g= pu/drm/amd/display/dc/dcn30/dcn30_hwseq.h index a24a8e33a3d2..cb34ca932a5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h @@ -58,6 +58,9 @@ bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx, bool dcn30_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); + +void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx); + bool dcn30_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/= gpu/drm/amd/display/dc/dcn301/dcn301_init.c index 257df8660b4c..81fd50ee97c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c @@ -33,7 +33,7 @@ #include "dcn301_init.h" =20 static const struct hw_sequencer_funcs dcn301_funcs =3D { - .program_gamut_remap =3D dcn10_program_gamut_remap, + .program_gamut_remap =3D dcn30_program_gamut_remap, .init_hw =3D dcn10_init_hw, .power_down_on_boot =3D dcn10_power_down_on_boot, .apply_ctx_to_hw =3D dce110_apply_ctx_to_hw, --=20 2.40.1