From nobody Fri Sep 12 07:27:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0544FC001DB for ; Thu, 10 Aug 2023 04:54:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232867AbjHJEyO (ORCPT ); Thu, 10 Aug 2023 00:54:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232754AbjHJEyH (ORCPT ); Thu, 10 Aug 2023 00:54:07 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB6081BCF; Wed, 9 Aug 2023 21:54:06 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37A4rtBb062694; Wed, 9 Aug 2023 23:53:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691643236; bh=JGl6dzMpYY2nyy9SYBWqCT8CMjtq9mc1Hd1NlneIwtM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yiFaeSFszIXf6C6iwC/JfGQ6dAfnz/ej4PPvhLlDn2V5ywUpNuCMF5UmygxixvmBq 4iZE+gaMU0mSauRZkEZKmmiHj2ezgcd48JObv5nWXWBAMfTkdtlizK8XFzVPkWLj2G P71ATuXkH1vVVIvsvfqeTKkVCr/luMt0vYspvzUY= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37A4rt0u001558 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 23:53:55 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 23:53:55 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 23:53:55 -0500 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37A4ricn118558; Wed, 9 Aug 2023 23:53:53 -0500 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , Subject: [PATCH 3/3] arm64: dts: ti: Add support for the AM62P5-SK Date: Thu, 10 Aug 2023 10:23:14 +0530 Message-ID: <20230810045314.2676833-4-vigneshr@ti.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230810045314.2676833-1-vigneshr@ti.com> References: <20230810045314.2676833-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bryan Brattlof Add basic support for the AM62P5-SK platform with UART and ramdisk as rootfs. Schematics is at https://www.ti.com/lit/zip/sprr487 Signed-off-by: Bryan Brattlof Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 3 + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 169 ++++++++++++++++++++++++ 2 files changed, 172 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 437a3d7e8e3a..5a09cad74c44 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -23,6 +23,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-lp-sk.dtb # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-sk.dtb =20 +# Boards with AM62Px SoC +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-sk.dtb + # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-phyboard-electra-rdk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts new file mode 100644 index 000000000000..b0882211448e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5-SK + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr487 + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" + +/ { + compatible =3D "ti,am62p5-sk", "ti,am62p5"; + model =3D "Texas Instruments AM62P5 SK"; + + aliases { + serial0 =3D &wkup_uart0; + serial2 =3D &main_uart0; + serial3 =3D &main_uart1; + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + memory@80000000 { + /* 8G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type =3D "memory"; + bootph-pre-ram; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg =3D <0x00 0x9e780000 0x00 0x80000>; + alignment =3D <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment =3D <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; +}; + +&cbass_main { + bootph-pre-ram; +}; + +&main_pmx0 { + status =3D "okay"; + bootph-pre-ram; + + main_uart0_pins_default: main-uart0-default-pins { + bootph-pre-ram; + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */ + AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + bootph-pre-ram; + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */ + AM62PX_IOPAD(0x198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2 */ + AM62PX_IOPAD(0x1ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR */ + AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR */ + >; + }; +}; + +&main_timer0 { + bootph-pre-ram; +}; + +&main_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; + status =3D "okay"; + bootph-pre-ram; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart1_pins_default>; + status =3D "reserved"; + bootph-pre-ram; +}; + +&cbass_mcu { + bootph-pre-ram; +}; + +&mcu_pmx0 { + status =3D "okay"; + bootph-pre-ram; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-pre-ram; + pinctrl-single,pins =3D < + AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + }; +}; + +&cbass_wakeup { + bootph-pre-ram; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; + status =3D "reserved"; + bootph-pre-ram; +}; + +&wkup_conf { + bootph-pre-ram; +}; + +&chipid { + bootph-pre-ram; +}; + +&dmss { + bootph-pre-ram; +}; + +&dmsc { + bootph-pre-ram; +}; + +&k3_pds { + bootph-pre-ram; +}; + +&k3_clks { + bootph-pre-ram; +}; + +&k3_reset { + bootph-pre-ram; +}; + +&secure_proxy_main { + bootph-pre-ram; +}; --=20 2.41.0