From nobody Fri Sep 12 05:25:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A3D1C001DB for ; Thu, 10 Aug 2023 04:54:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232845AbjHJEyL (ORCPT ); Thu, 10 Aug 2023 00:54:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229540AbjHJEyF (ORCPT ); Thu, 10 Aug 2023 00:54:05 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33E952112; Wed, 9 Aug 2023 21:54:05 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37A4roDx001791; Wed, 9 Aug 2023 23:53:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691643230; bh=aaY5lYBohR7ppyNpVFuO9tX3DXd6P6y6g/maS6QMAm0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=faaux129yxYAhuZqtSwvF1nIPWiARQNNRbjIzlESRuh4TA4xesH7GRpokjlK9ni8Y kkMmMgENyLzZ91/snn48oXRDyKb4qLdQiQe7CyZlBBZjJ880IOaBE2Al32ot70sYAU ZaASck08zB/I63VtuKnH9FwGT9H0gJxmCguwTK3A= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37A4roKI001526 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 23:53:50 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 23:53:50 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 23:53:50 -0500 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37A4ricl118558; Wed, 9 Aug 2023 23:53:47 -0500 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , Subject: [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs Date: Thu, 10 Aug 2023 10:23:12 +0530 Message-ID: <20230810045314.2676833-2-vigneshr@ti.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230810045314.2676833-1-vigneshr@ti.com> References: <20230810045314.2676833-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bryan Brattlof Add bindings for TI's AM62P5 family of devices. Signed-off-by: Bryan Brattlof Signed-off-by: Vignesh Raghavendra Acked-by: Conor Dooley Reviewed-by: Dhruva Gole --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index 5ca6af492507..93b2774cc0a9 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 =20 + - description: K3 AM62P5 SoC + items: + - enum: + - ti,am62p5-sk + - const: ti,am62p5 + - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra items: - const: phytec,am625-phyboard-lyra-rdk --=20 2.41.0 From nobody Fri Sep 12 05:25:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07CA7C001DB for ; Thu, 10 Aug 2023 04:54:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232880AbjHJEyR (ORCPT ); Thu, 10 Aug 2023 00:54:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232779AbjHJEyI (ORCPT ); Thu, 10 Aug 2023 00:54:08 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 665D02111; Wed, 9 Aug 2023 21:54:07 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37A4rrHF001802; Wed, 9 Aug 2023 23:53:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691643233; bh=x2X+9CKIbWcMISW3YfdSrgB5TmMqf9/ql5GTHADXaJs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NWZ8o2qlnldpM/CY7oTM2Vxp8vKuRCRW13dREWI9N/Q1G9J63Rk9mHKLbnlwaGudz jkqE0RKNcjSeUj0uwUwZQuzhxp85V+iVsRsyC+/7d/4dNZAsno1cVQwMQYXC3eU7pN WDhOhMuIs0aL6eHz32KCbeg2Vg8SfYLDqDDeocGI= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37A4rrD3001541 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 23:53:53 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 23:53:52 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 23:53:52 -0500 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37A4ricm118558; Wed, 9 Aug 2023 23:53:50 -0500 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , Subject: [PATCH 2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs Date: Thu, 10 Aug 2023 10:23:13 +0530 Message-ID: <20230810045314.2676833-3-vigneshr@ti.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230810045314.2676833-1-vigneshr@ti.com> References: <20230810045314.2676833-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bryan Brattlof The AM62Px is an extension of the existing Sitara AM62x low-cost family of application processors built for Automotive and Linux Application development. Scalable Arm Cortex-A53 performance and embedded features, such as: multi high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automation and industrial application, including automotive digital instrumentation, automotive displays, industrial HMI, and more. Some highlights of AM62P SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortext-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One 3D GPU up to 50 GLFOPS * H.264/H.265 Video Encode/Decode. * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. For those interested, more details about this SoC can be found in the Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 Signed-off-by: Bryan Brattlof Signed-off-by: Vignesh Raghavendra Acked-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 129 ++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi | 16 +++ arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 30 +++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 109 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 107 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 + 6 files changed, 394 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62p-main.dtsi new file mode 100644 index 000000000000..3ce70be634b9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P main domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible =3D "mmio-sram"; + reg =3D <0x00 0x70000000 0x00 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible =3D "arm,gic-v3"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts =3D ; + + gic_its: msi-controller@1820000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its =3D <0x1000000 0x400000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + dmss: bus@48000000 { + compatible =3D "simple-mfd"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges; + ranges =3D <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + + ti,sci-dev-id =3D <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible =3D "ti,am654-secure-proxy"; + #mbox-cells =3D <1>; + reg-names =3D "target_data", "rt", "scfg"; + reg =3D <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names =3D "rx_012"; + interrupts =3D ; + }; + }; + + dmsc: system-controller@44043000 { + compatible =3D "ti,k2g-sci"; + ti,host-id =3D <12>; + mbox-names =3D "rx", "tx"; + mboxes =3D <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names =3D "debug_messages"; + reg =3D <0x00 0x44043000 0x00 0xfe0>; + + k3_pds: power-controller { + compatible =3D "ti,sci-pm-domain"; + #power-domain-cells =3D <2>; + }; + + k3_clks: clock-controller { + compatible =3D "ti,k2g-sci-clk"; + #clock-cells =3D <2>; + }; + + k3_reset: reset-controller { + compatible =3D "ti,sci-reset"; + #reset-cells =3D <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible =3D "pinctrl-single"; + reg =3D <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + status =3D "disabled"; + }; + + main_timer0: timer@2400000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2400000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&k3_clks 36 2>; + clock-names =3D "fck"; + assigned-clocks =3D <&k3_clks 36 2>; + assigned-clock-parents =3D <&k3_clks 36 3>; + power-domains =3D <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_uart0: serial@2800000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02800000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 146 0>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + main_uart1: serial@2810000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02810000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 152 0>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62p-mcu.dtsi new file mode 100644 index 000000000000..bd6e8c12a1e8 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P mcu domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible =3D "pinctrl-single"; + reg =3D <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + status =3D "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-wakeup.dtsi new file mode 100644 index 000000000000..da8430222948 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P wakeup domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: bus@43000000 { + compatible =3D "simple-bus"; + reg =3D <0x00 0x43000000 0x00 0x20000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + compatible =3D "ti,am654-chipid"; + reg =3D <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x2b300000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 114 0>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/= k3-am62p.dtsi new file mode 100644 index 000000000000..305dda92ae7f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5 SoC family + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model =3D "Texas Instruments K3 AM62P5 SoC"; + compatible =3D "ti,am62p5"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + psci: psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + cbass_main: bus@f0000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + ranges =3D <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MM= Rs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace= */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace= */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router = */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral= window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second periphera= l window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral= window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core w= indow */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core w= indow */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data = */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy confi= g */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral Windo= w */ + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Windo= w */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; /* WKUP CTRL MMR */ + + cbass_mcu: bus@4000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Periph= eral Window */ + }; + + cbass_wakeup: bus@b00000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Wind= ow */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; /* WKUP CTRL MMR */ + }; + }; +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62p-main.dtsi" +#include "k3-am62p-mcu.dtsi" +#include "k3-am62p-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti= /k3-am62p5.dtsi new file mode 100644 index 000000000000..50147bb63e03 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5 SoC family (quad core) + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * TRM: https://www.ti.com/lit/pdf/spruj83 + */ + +/dts-v1/; + +#include "k3-am62p.dtsi" + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x002>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x003>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + clocks =3D <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <2>; + cache-size =3D <0x80000>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index 6004e0967ec5..2a4e0e084d69 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -41,6 +41,9 @@ #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) +#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode= )) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxm= ode)) =20 --=20 2.41.0 From nobody Fri Sep 12 05:25:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0544FC001DB for ; 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Wed, 9 Aug 2023 23:53:55 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 23:53:55 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 23:53:55 -0500 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37A4ricn118558; Wed, 9 Aug 2023 23:53:53 -0500 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , Subject: [PATCH 3/3] arm64: dts: ti: Add support for the AM62P5-SK Date: Thu, 10 Aug 2023 10:23:14 +0530 Message-ID: <20230810045314.2676833-4-vigneshr@ti.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230810045314.2676833-1-vigneshr@ti.com> References: <20230810045314.2676833-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bryan Brattlof Add basic support for the AM62P5-SK platform with UART and ramdisk as rootfs. Schematics is at https://www.ti.com/lit/zip/sprr487 Signed-off-by: Bryan Brattlof Signed-off-by: Vignesh Raghavendra Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/Makefile | 3 + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 169 ++++++++++++++++++++++++ 2 files changed, 172 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 437a3d7e8e3a..5a09cad74c44 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -23,6 +23,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-lp-sk.dtb # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-sk.dtb =20 +# Boards with AM62Px SoC +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-sk.dtb + # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-phyboard-electra-rdk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts new file mode 100644 index 000000000000..b0882211448e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5-SK + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr487 + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" + +/ { + compatible =3D "ti,am62p5-sk", "ti,am62p5"; + model =3D "Texas Instruments AM62P5 SK"; + + aliases { + serial0 =3D &wkup_uart0; + serial2 =3D &main_uart0; + serial3 =3D &main_uart1; + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + memory@80000000 { + /* 8G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type =3D "memory"; + bootph-pre-ram; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg =3D <0x00 0x9e780000 0x00 0x80000>; + alignment =3D <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment =3D <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; +}; + +&cbass_main { + bootph-pre-ram; +}; + +&main_pmx0 { + status =3D "okay"; + bootph-pre-ram; + + main_uart0_pins_default: main-uart0-default-pins { + bootph-pre-ram; + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */ + AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + bootph-pre-ram; + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */ + AM62PX_IOPAD(0x198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2 */ + AM62PX_IOPAD(0x1ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR */ + AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR */ + >; + }; +}; + +&main_timer0 { + bootph-pre-ram; +}; + +&main_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; + status =3D "okay"; + bootph-pre-ram; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart1_pins_default>; + status =3D "reserved"; + bootph-pre-ram; +}; + +&cbass_mcu { + bootph-pre-ram; +}; + +&mcu_pmx0 { + status =3D "okay"; + bootph-pre-ram; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-pre-ram; + pinctrl-single,pins =3D < + AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + }; +}; + +&cbass_wakeup { + bootph-pre-ram; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; + status =3D "reserved"; + bootph-pre-ram; +}; + +&wkup_conf { + bootph-pre-ram; +}; + +&chipid { + bootph-pre-ram; +}; + +&dmss { + bootph-pre-ram; +}; + +&dmsc { + bootph-pre-ram; +}; + +&k3_pds { + bootph-pre-ram; +}; + +&k3_clks { + bootph-pre-ram; +}; + +&k3_reset { + bootph-pre-ram; +}; + +&secure_proxy_main { + bootph-pre-ram; +}; --=20 2.41.0