From nobody Fri Sep 12 01:35:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40C69C0015E for ; Thu, 10 Aug 2023 00:38:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230233AbjHJAi4 (ORCPT ); Wed, 9 Aug 2023 20:38:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230323AbjHJAie (ORCPT ); Wed, 9 Aug 2023 20:38:34 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5A741BD9; Wed, 9 Aug 2023 17:38:33 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37A0cM5p014065; Wed, 9 Aug 2023 19:38:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691627902; bh=MPePiyyaNVFVGlR+k2OlpPTbPEi+XbugTULZIOz3KZI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zLrejJmxbUYFWAer0Cz06/S3eIdSYh8dGA6wdGTNNeUZvBWOXo0Q8KorsQb72BW9E Z2ugUQvb1Ro/8kpLfbn3zEBhQHElDhB2FCNzfy2d4FWfe8jP2NZ2XDpHX+cAj5Qps+ +qZXtG80sZ/OLaXC6gBvtXF3qkzx4oQsSpWcDQrc= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37A0cMxv078386 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 19:38:22 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 19:38:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 19:38:21 -0500 Received: from lelv0327.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37A0cGFA014775; Wed, 9 Aug 2023 19:38:20 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v3 07/13] arm64: dts: ti: k3-am64: Enable OSPI nodes at the board level Date: Wed, 9 Aug 2023 19:38:08 -0500 Message-ID: <20230810003814.85450-8-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230810003814.85450-1-afd@ti.com> References: <20230810003814.85450-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 + arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 + arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index 4e3e450e4e4c8..ed1b63b9c1c5f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -794,6 +794,7 @@ ospi0: spi@fc40000 { assigned-clock-parents =3D <&k3_clks 75 7>; assigned-clock-rates =3D <166666666>; power-domains =3D <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index 5606d775153d4..1c2c8f0daca9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -181,6 +181,7 @@ i2c_som_rtc: rtc@52 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index d84e7ee160328..b4a1f73d4fb17 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -520,6 +520,7 @@ &tscadc0 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 963d796a3a970..af06ccd466802 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -518,6 +518,7 @@ &tscadc0 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index 5e9012107afab..6229849b5d968 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -180,6 +180,7 @@ &main_r5fss1_core1 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins>; =20 --=20 2.39.2