From nobody Sun Feb 8 02:56:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4BCDC001E0 for ; Wed, 9 Aug 2023 19:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232016AbjHITrH (ORCPT ); Wed, 9 Aug 2023 15:47:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229488AbjHITrG (ORCPT ); Wed, 9 Aug 2023 15:47:06 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D13AF10DC; Wed, 9 Aug 2023 12:47:05 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jkvc9082645; Wed, 9 Aug 2023 14:46:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610417; bh=lYYkJgSjotdn9z630Q0bdw52E8CRoYe6AJCa/q+uOtg=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=kFe8H2xU/CfP87buBNNpE3+4M4y7LYnDUWDU50TE3MvwJ2Aa3z0u9blC5f9S3TLZB BxcHbKn8VWtkN5WvDDElqeDr1ubcsPlnl8wYDTImGdzbjQ8yogjyZz60BHS96Oipxg jvgI3vTyabatY3DT1RksSrrBFBylgsSlT5WqUSWo= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379JkvmN024692 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:46:57 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:46:57 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:46:56 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379JkuWW022680; Wed, 9 Aug 2023 14:46:56 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:19 +0530 Subject: [PATCH v6 1/7] arm64: dts: ti: k3-j7200-som-p0: Add TP6594 family PMICs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20230810-tps6594-v6-1-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5070; i=j-luthra@ti.com; h=from:subject:message-id; bh=x9uvfuO+UnW37axEg5ZLexDGBu/GJiHMCE5eHVtsQg8=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0tdVUGbjwsXBezXNhpVIJyqTtI5r6DrqO1c IEyEznoOquJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtLQAKCRBD3pH5JJpx RaioEAChIIHejBkgMxWkKccAuoWGM24wQMfDwj+9QOMpr0EcWvCxZi7qtrmDchYkGfgk8zFXwMq 8HEvBN+KDWzTfv7Y9ltzKjT4qmrc2iakEN7yDUCH9GWbqZMWPfFaqDS4/374+cy0IdMXJoByhEf C1BvxgfwefL5AYMOcZ9ly23isLxa95YuhY5HGP8npqCwz328QsEo0h6oJTGE7bfCM5nLnbGyQKC UGwW8BX27uB7G5ijhky7dvYcPwLPBRXJrceZDIGka6w3bU3hv4mRyDWxO9OGsWGp4bf1Bd3U+/E IeglY43xgd4TxHi1ncXVoQvODnGXzj10f/3CfYo0ITsM6MZI51diOZpUNfyeVsbxTuyW6tRYYYG aqTXJsDn+7BCUjNxr98eGl28eX0C19kkP4BlZGU/gB5/+5Tab3gOOjI7Yaq2Xwotgc/Ud6FB7Rf EVqb5gm2DEuOb4u+fEbpbEIBb05cxeWCdJjiFaaW4XFPu0m63pjuCIxKaeqzvU45IibXzR8uPZG etmj5DZ4AhiiBA9/uAT59A+vAEx6XEHI/+bE0pVP/VWdmAF12so8RyhI8rDeJr26GAVeRb/i7Nk 5RBy6bWolBxkzhjBz/1ixVGNWbRXocI0DSbOJtg3nR/+5AhwIL7KXThQDVbIMKTFogV4HfnSWe9 Pf+hUzHg/+6USRA== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Esteban Blanc This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 157 ++++++++++++++++++++++++= ++++ 1 file changed, 157 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j7200-som-p0.dtsi index b37f4f88ece4..51ed611585dd 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -127,6 +127,14 @@ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) W= KUP_I2C0_SDA */ }; }; =20 +&wkup_pmx3 { + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins =3D < @@ -264,6 +272,155 @@ eeprom@50 { compatible =3D "atmel,24c256"; reg =3D <0x50>; }; + + tps659414: pmic@48 { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x48>; + ti,primary-pmic; + system-power-controller; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <84 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells =3D <2>; + + buck1-supply =3D <&vsys_3v3>; + buck2-supply =3D <&vsys_3v3>; + buck3-supply =3D <&vsys_3v3>; + buck4-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + bucka1: buck1 { + regulator-name =3D "vda_mcu_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka2: buck2 { + regulator-name =3D "vdd_mcuio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name =3D "vdd_mcu_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name =3D "vdd_ddr_1v1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name =3D "vdd_phyio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name =3D "vdd1_lpddr4_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name =3D "vda_dll_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name =3D "vdd_wk_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name =3D "vda_pll_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + lp876441: pmic@4c { + compatible =3D "ti,lp8764-q1"; + reg =3D <0x4c>; + system-power-controller; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <84 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells =3D <2>; + + buck1-supply =3D <&vsys_3v3>; + buck2-supply =3D <&vsys_3v3>; + buck3-supply =3D <&vsys_3v3>; + buck4-supply =3D <&vsys_3v3>; + + regulators: regulators { + buckb1: buck1 { + regulator-name =3D "vdd_cpu_avs"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <900000>; + regulator-always-on; + regulator-boot-on; + }; + + buckb2: buck2 { + regulator-name =3D "vdd_ram_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb3: buck3 { + regulator-name =3D "vdd_core_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb4: buck4 { + regulator-name =3D "vdd_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; =20 &ospi0 { --=20 2.41.0 From nobody Sun Feb 8 02:56:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34E8AC04A94 for ; Wed, 9 Aug 2023 19:47:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233075AbjHITrM (ORCPT ); Wed, 9 Aug 2023 15:47:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229488AbjHITrJ (ORCPT ); Wed, 9 Aug 2023 15:47:09 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42C5310E0; Wed, 9 Aug 2023 12:47:08 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379JkwDl011908; Wed, 9 Aug 2023 14:46:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610418; bh=QC3zGGEWVNPoOuYVH11z0Jd/+0lyJRPhg2I9vTAORm8=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=b3MSMF8kleyxZiPo9x4GlsafrHwkfd3+Ufnq2KlJVTo0e3/ptrHmsJZJCmLAy5xr+ AFEwThDyiTGWusgCkePrn/OLZGoSwtGvxODolpo3qvDF2sT7A5cajvst60KOlRP78r euwSBhALriXuVNZ0ytgT8JVPSsYiJynj4Eu8Be8M= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379JkwAN069548 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:46:58 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:46:58 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:46:58 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jkv07065120; Wed, 9 Aug 2023 14:46:58 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:20 +0530 Subject: [PATCH v6 2/7] arm64: dts: ti: k3-j721s2-som-p0: Add TP6594 family PMICs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20230810-tps6594-v6-2-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6089; i=j-luthra@ti.com; h=from:subject:message-id; bh=ZnNtOITeK/mZkX9caV/brC8y6tgnxXhJkwV81yr7UOo=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0uouykMJFVfP7JnxFf6LHA3DNgJF1YHL26d /GNoBnC6eCJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtLgAKCRBD3pH5JJpx RYSRD/0QujTd4dY/I/4Z+ijtm8V9WtGHHYsZvFsdsVzY7OFBHWhvFHWuD9OLwQet2htwtSyrDSm +R32resE1MY7gPWh/76YISVxS0clCQY6SrzvQX7cgR56LjOLgO2XfWewjiLbHlKNnc9ZfT2EUuo NmAPKFFLx/XcUniTmV7zuagFNXcMGl6gDeH5bbxpqWtOss+DBkWq3+W+BR3IW62A45selJeTTtH z21xwRghPhikLt7V9aSRH7f2Gn/vd5uCtjXA6Sj5WJU60s6i/sl8jE09nAdrOMMql9V8aIxCpfo 92LD8GeUokWtayWllkTzzwL4vgSi7h8jHHlQUW9zqN2lav++juugEC/GNvfsB3RU2T2iiIufZVb bx8ms4Y8fEyneLUObq2jkujoBQeZtv6kZP0VWpqYpOzueMsIpr9d7Wy6F21kCI0kMghuos0ioli hWxIx1ETgAXBl2eHoca5JoSfSO2ltVTGpquWtaWLcDLPhpdYSDF4Q2/bZEwMpAuozeAZyo2eYbx QZTrx4kY466whuN12u4LabjY3R7u5GvCycqQgv2b7shOozwmK6lF0952ZllxF20bfWWUwMbkM2K owEZwBzfWTJ7g8U+x0ZoJRpZP9r1+0J+mSgnw73PxKV/KFfD1uxYJLahkVJ8VnT+/GjAg4xMXrf 3FxmnU0iSuTyTng== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Esteban Blanc This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 199 +++++++++++++++++++++++= ++++ 1 file changed, 199 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index a4006f328027..94b6162aba21 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -70,6 +70,15 @@ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI= 0_LBCLKO */ }; }; =20 +&wkup_pmx1 { + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; +}; + &wkup_pmx2 { wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins =3D < @@ -106,6 +115,196 @@ eeprom@50 { compatible =3D "atmel,24c256"; reg =3D <0x50>; }; + + tps659411: pmic@48 { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x48>; + ti,primary-pmic; + system-power-controller; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells =3D <2>; + + buck1234-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + bucka1234: buck1234 { + regulator-name =3D "vdd_cpu_avs"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name =3D "vdd_mcu_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name =3D "vdd_mcuwk_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name =3D "vdd_mcu_gpioret_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name =3D "vdd_mcuio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name =3D "vda_mcu_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659414: pmic@4c { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x4c>; + system-power-controller; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells =3D <2>; + + buck1-supply =3D <&vsys_3v3>; + buck2-supply =3D <&vsys_3v3>; + buck3-supply =3D <&vsys_3v3>; + buck4-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + buckb1: buck1 { + regulator-name =3D "vdd_io_1v8_reg"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buckb2: buck2 { + regulator-name =3D "vdd_fpd_1v1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb3: buck3 { + regulator-name =3D "vdd_phy_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb4: buck4 { + regulator-name =3D "vdd_ddr_1v1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb5: buck5 { + regulator-name =3D "vdd_ram_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob1: ldo1 { + regulator-name =3D "vdd_wk_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob2: ldo2 { + regulator-name =3D "vdd_gpioret_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob3: ldo3 { + regulator-name =3D "vda_dll_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob4: ldo4 { + regulator-name =3D "vda_pll_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + lp876411: pmic@58 { + compatible =3D "ti,lp8764-q1"; + reg =3D <0x58>; + system-power-controller; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells =3D <2>; + + buck1234-supply =3D <&vsys_3v3>; + + regulators { + buckc1234: buck1234 { + regulator-name =3D "vdd_core_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; =20 &main_i2c0 { --=20 2.41.0 From nobody Sun Feb 8 02:56:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5D23C0015E for ; Wed, 9 Aug 2023 19:47:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234082AbjHITrX (ORCPT ); Wed, 9 Aug 2023 15:47:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232461AbjHITrL (ORCPT ); Wed, 9 Aug 2023 15:47:11 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E472A2100; Wed, 9 Aug 2023 12:47:09 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl1JI011922; Wed, 9 Aug 2023 14:47:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610421; bh=7088h8X7s0covVaq45Tpol1RjrF9Tnavd64QUD8UpnQ=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=TEjpWaFQrQDHtJ/a+N6Q3htNwX4ZUVxNHWftq0MPG4AcAAGbuuczRBJt0P09TeN30 IPQxhvK+OZCJbbqwXzVz06h3pBbJJsZPp7g4LuoMefyvKyjzxLlcL5blJ9nZ1IMNYf Q4m/nBqPL7kBknpDEVERMZv2iXF7QjDKKe82MZJM= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379Jl1ia032227 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:47:01 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:46:59 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:46:59 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jkx9J050920; Wed, 9 Aug 2023 14:46:59 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:21 +0530 Subject: [PATCH v6 3/7] arm64: dts: ti: k3-j721e-som-p0: Add TP6594 family PMICs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20230810-tps6594-v6-3-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5390; i=j-luthra@ti.com; h=from:subject:message-id; bh=6ytm+I/61w+Cti00xxMFIg2KdbZYmvKL4QcyqU6u35s=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0vpEUVKqyXFl2Ea8bz6sTNT1Kz5fbmxUbCM C3z7jHenmCJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtLwAKCRBD3pH5JJpx RaSpD/9ZW1fJczTYS5slQX7xSU/hkE138uYPvBkYfK9pODSx1NJDhXSx9dwrIyLJyuH+A3Lq1yl J1yt+Qb/7MvZ0imJ8p+owZydQBHvfDSHYzyvO+AKNwFrr8sqKJT51MW+lXWuaXBDNTMROeNCo0z cQRN+Zgc7wZIr+IQakqdZKk8Osa6hVY9c+eGw2EyFVV/MT5f3uw5Wm5Dx0vt79RN+sLYKsXenix Fj1ASxuECIFgGp0Q04RPuaN/tEaxb4MXUF7e6aB1ETg/Uomi8MYZvJGA3LDao0rTOjh1So6dfnm m6aZvZrZ3hj3JMO7N8O6t2J7e+5nHuvYvoIhXefvNW7IG0fmKtcf48XdS/AHmh4x3kBKzNMPNDd zs6qnlxhMx2rRf5zKK1NEzxH7faVEU5iPeMirKhlrnEUeWoCu1Tl5FXKV4+yifGpTM0l7XP60pp PuIQssf8rf3FShSPRBC9FKgMHwm0qdln+y85Z36fjmavPZacF2ipWEiwBYPS9//mJ1u0vSAYUWD BTzvULDt/ENg8Zr38BBbV93VbCH1bsMEjqZJJZ/+fggqtluzDX0OUpkcrbtjnkqJramigmY/25o wyhcpUh+AI/GraeGo/hC+jEqasKilo3jY9yOI5zFzJqndbLDqctm61+KXXE8iooNBJ7vXjUxr/R s6uFz2kUA0Yycpw== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jerome Neanne This patch adds support for TPS6594 PMIC family on wakup I2C0 bus. Theses devices provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Jerome Neanne Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 163 ++++++++++++++++++++++++= ++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j721e-som-p0.dtsi index e90e43202546..21f350cd9a45 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -152,6 +152,12 @@ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) W= KUP_I2C0_SDA */ >; }; =20 + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */ + >; + }; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins =3D < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ @@ -199,6 +205,163 @@ eeprom@50 { compatible =3D "atmel,24c256"; reg =3D <0x50>; }; + + tps659413: pmic@48 { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x48>; + system-power-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <9 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells =3D <2>; + + buck12-supply =3D <&vsys_3v3>; + buck3-supply =3D <&vsys_3v3>; + buck4-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name =3D "vdd_cpu_avs"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name =3D "vdd_mcu_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name =3D "vdd_ddr_1v1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name =3D "vdd_phyio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name =3D "vdd1_lpddr4_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name =3D "vdd_mcuio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name =3D "vdda_dll_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name =3D "vda_mcu_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659411: pmic@4c { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x4c>; + system-power-controller; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <9 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells =3D <2>; + + buck1234-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + buckb1234: buck1234 { + regulator-name =3D "vdd_core_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb5: buck5 { + regulator-name =3D "vdd_ram_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob1: ldo1 { + regulator-name =3D "vdd_sd_dv"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob2: ldo2 { + regulator-name =3D "vdd_usb_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob3: ldo3 { + regulator-name =3D "vdd_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob4: ldo4 { + regulator-name =3D "vda_pll_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; =20 &ospi0 { --=20 2.41.0 From nobody Sun Feb 8 02:56:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A7D0C001E0 for ; Wed, 9 Aug 2023 19:47:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234009AbjHITrU (ORCPT ); Wed, 9 Aug 2023 15:47:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232647AbjHITrL (ORCPT ); Wed, 9 Aug 2023 15:47:11 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFEED2106; Wed, 9 Aug 2023 12:47:09 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl1fT086082; Wed, 9 Aug 2023 14:47:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610421; bh=BYl4jJDg+IGtJlaRNFfsbCRVFe+QoB6JeXudogyJCag=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=SgjUWYfeZ++YAzDEcTRzeC+Wqb3G3B7I8C+fieLXUSz3u4Jr/fQb4rJ22kpSK7cll ZEIZPvPaVJn9pvltvttNxUAjwLO3XVeCn+Fuw13qcK5ttlD6AYsiQErjOZdbdbPegR 147S42aXDYGR6C+4vG36UkwqDBwXe34JUG0N8gWw= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379Jl1mu032236 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:47:01 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:47:01 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:47:01 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl0Uk065166; Wed, 9 Aug 2023 14:47:00 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:22 +0530 Subject: [PATCH v6 4/7] arm64: dts: ti: k3-j784s4: Fix interrupt ranges for wkup & main gpio MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20230810-tps6594-v6-4-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1749; i=j-luthra@ti.com; h=from:subject:message-id; bh=pmr8txSe1Pu1GvCkSBqddn+aqWc9cRutSnhOiL2s9iw=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0weAntwJxXUXg42ifMuN5WYbCqgiJkj0SzQ OmI5lKfXl+JAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtMAAKCRBD3pH5JJpx RRFQD/wMaIfpOdrXHlhQjBqNBdY8rCYcxRaaCOUb1hrQWXLh1Qbm0J2lT1eH6dak6F6KyH94Cj7 0YLfHHV4Dx6TDZrL/mkGDiEE4WthEvUggj2pFcihjU+semYUskCdRq6XXkCKprw9b607p4LLRnd smcUGAqdFLH0969LLPBvRs3IJwmXsoLFbm0n5K+d01YC6UqFQBC1ivLi0TvhHOlu6NBeCAabiFG uduf9J9AZgh9/1Z72eGMs7Ae0hvmoB0MO8Ye1EArhpKSoIqbRifI8qThrwPAwhzG9WUW60tzlNC 4MuxWtUXYSs4xWXFJYzezRg1TpOzrRy3VEvpfmt5PmvOMdzrwgNBb9/PVFDX6XUECofDhjZVEKa ZUvP5ws0g/tUWCx6tj66+NJynbgqLdXQu9weAcBogv2J3jnuRZhMF2Mh7ARZTAe5FKtFjKTQSZ7 mxhk94UYNSZBkmutq88Ku247CSMijhpcKNn3ByHfSu+7u0hv2eo2WTglr5DzcbfDnenmF/Gs6df y4tyOgvc8RZScZLOM/6Zu/qIYqo2yBH7eWTlbegNKdmPjWB+4uaBpRv7KgmYZDUF97tWJxKP2i9 bxxfa1NlDg6fw0okBJ2eJnOajzqBUXqpAEigieY8Ka2k5PQh7+uguMQ8puDCHG4OTg8/srdeqWK WpVDrDLnZQwyK1Q== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Apelete Seketeli This patch fixes the interrupt range for wakeup and main domain gpio interrupt routers. They were wrongly subtracted by 32 instead of following what is defined in the interrupt map in the TRM (Table 9-35). Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Link: https://www.ti.com/lit/ug/spruj52c/spruj52c.pdf Signed-off-by: Apelete Seketeli Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index a04c44708a09..013cf4ed98d8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -60,7 +60,7 @@ main_gpio_intr: interrupt-controller@a00000 { #interrupt-cells =3D <1>; ti,sci =3D <&sms>; ti,sci-dev-id =3D <10>; - ti,interrupt-ranges =3D <8 360 56>; + ti,interrupt-ranges =3D <8 392 56>; }; =20 main_pmx0: pinctrl@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 740ee794d7b9..77a45f97e28b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -107,7 +107,7 @@ wkup_gpio_intr: interrupt-controller@42200000 { #interrupt-cells =3D <1>; ti,sci =3D <&sms>; ti,sci-dev-id =3D <177>; - ti,interrupt-ranges =3D <16 928 16>; + ti,interrupt-ranges =3D <16 960 16>; }; =20 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ --=20 2.41.0 From nobody Sun Feb 8 02:56:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4C9AC0015E for ; Wed, 9 Aug 2023 19:47:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229986AbjHITrS (ORCPT ); Wed, 9 Aug 2023 15:47:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232296AbjHITrL (ORCPT ); Wed, 9 Aug 2023 15:47:11 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF9442103; Wed, 9 Aug 2023 12:47:09 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl3Vi086091; Wed, 9 Aug 2023 14:47:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610423; bh=6fIXIj7qWgkDWfpcBuKTTLH04m4gxyfxt/eZ75zcXrg=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=x6slZVut+O71P8sAAzHLLSRiOlpyzUCUCsDhStBOs6IZCUFIo2xphTs9OFJaZgRPl OrKSk+5tPEaZj/h9nRUHu620hsDSSZSAhh7r7yjeikl2aoC1iWVEDRE1PeBN/EhmgW xOTGoa5ALVBQDTXZlgquvmO9S3xPEMTxlG3XP9ck= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379Jl2UJ039608 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:47:02 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:47:02 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:47:02 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl1GB051008; Wed, 9 Aug 2023 14:47:02 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:23 +0530 Subject: [PATCH v6 5/7] arm64: dts: ti: k3-j784s4-evm: Add support for TPS6594 PMIC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20230810-tps6594-v6-5-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3881; i=j-luthra@ti.com; h=from:subject:message-id; bh=RMpsPB4XdwxaSFr7ajZF4M8Jg1mgkdClDXv9BHS97K0=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0yI0b0V64Pkg7YYv/gAU0gb8IRHMFa0mWxX KjoqPLaiwmJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtMgAKCRBD3pH5JJpx RSpoEACJTY929b3uE2+v6J/JZe+VgZ2SHWYi/QYDjqXUFiXmQn3hJ/c+WDtk+F3x6hQXpfUFnOH 4x+9JYMZSCii+pQIhuk9VJykEaZXrS3Hshxl/1hSOU/gEdUuUR50W6rwbWJqJh2LV24VbW3ALw9 bsOwmGvmHjUS2HgyCye+O+54V2weUAK6t7HdZrpYq8BOA+e9HBWxnxUBBhtrCAnXZCyVcpYYm8q mcO/qo01AAhEb82kYu3kfoNej524uL+h71TNFF36cHOJX2ncK3wMkl09zuf8APgFUJer5OZEDEH 1yBlvInzYDLN8S736EIEKsEyyq+TxddKsOgXmMcFp8vzMYKdRJpyuUz1gq8hCbxCpWrsfhSURgo Lvlaed8/odknKnlZ8RaHRqitFdckXoQV65n74yNEWFmuomaylvMdYQRqflD4D2qZKIvvpavkbBw w3lNZGSuO+8UwLmFucSka6BMUZWZEUSywt9mye1E8AXrsaLqhzrvJr5FxAms7/WZV5twlM/nIWi AkJrbTQf/r0EYCU3TcYHhAENLG+8Uq6ON2XMZLvpFYpHVRITx34kiLUDtv0sIUXV+kRlEPB6n3M MRtdPAm29Sr8QqOyhiO3AEr1CzRej4iVYFDFe5o0rhDb7pYp6YyvIw/KdQsAP8woS/gmQc0Emwg PapBPTnmjNlvTIw== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jerome Neanne This patch adds support for TPS6593 PMIC on wkup I2C0 bus. This device provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Jerome Neanne Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 104 +++++++++++++++++++++++++++= ++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index edc1009b2d1e..29202ef40f78 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -251,6 +251,10 @@ vdd_sd_dv: regulator-TLV71033 { }; }; =20 +&wkup_gpio0 { + status =3D "okay"; +}; + &main_pmx0 { main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins =3D < @@ -365,6 +369,17 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_AD= C1_AIN7 */ }; }; =20 +&wkup_pmx1 { + status =3D "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) + >; + }; +}; + &wkup_pmx0 { mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins =3D < @@ -423,6 +438,95 @@ eeprom@50 { compatible =3D "atmel,24c256"; reg =3D <0x50>; }; + + tps659413: pmic@48 { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x48>; + system-power-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells =3D <2>; + + buck12-supply =3D <&vsys_3v3>; + buck3-supply =3D <&vsys_3v3>; + buck4-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + bucka12: buck12 { + regulator-name =3D "vdd_ddr_1v1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name =3D "vdd_ram_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name =3D "vdd_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name =3D "vdd_mcu_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name =3D "vdd_mcuio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name =3D "vdd_mcuio_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name =3D "vds_dll_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name =3D "vda_mcu_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; =20 &mcu_uart0 { --=20 2.41.0 From nobody Sun Feb 8 02:56:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32D95C0015E for ; Wed, 9 Aug 2023 19:47:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232846AbjHITr1 (ORCPT ); Wed, 9 Aug 2023 15:47:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232704AbjHITrL (ORCPT ); Wed, 9 Aug 2023 15:47:11 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E937F2108; Wed, 9 Aug 2023 12:47:10 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl4MH086096; Wed, 9 Aug 2023 14:47:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610424; bh=VB+r5z/W4Lii6r8oAhIOL+FU2R1kBLQG0ya0jHBEvqo=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=BmvMDoMbrm7T9OErrushRI3WeMZeOgH0a3zUU5lA4FPVpR+e3rNoRmW2LZgVCEKFC OegnVm7XhU4tkAImP0n49/6Ug3bVdMZ6X8+w/aCdT29TPDi0s96ZMTJgKmwTpQQy48 JCMg55Mhvsj9jlkbasZu4U4KqtgJJjS6KdSlMSnI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379Jl4uH032322 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:47:04 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:47:04 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:47:04 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl3wV065302; Wed, 9 Aug 2023 14:47:03 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:24 +0530 Subject: [PATCH v6 6/7] arm64: dts: ti: k3-am62a7-sk: Add support for TPS6593 PMIC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20230810-tps6594-v6-6-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3367; i=j-luthra@ti.com; h=from:subject:message-id; bh=9kPfYgmoW8UezAiz/SVq0i+GIR4xFjfYwAcDxuvSWTU=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+0zYKTlEL1CDDWVt0zWsjeYIJkHGG61cjbVk WOGlAIYYaqJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtMwAKCRBD3pH5JJpx RVDdD/4u78YxoHpO5m6eZLEcHcxXzM7zNsPVhuQ6Gq9s15G+AdEGIsGlnLmuydruGPoXKIMAf00 iwX17TVzzymQVw8ij/3cyObRdpSa1c6hDkGp573PYpN0LP0jJu4EIRG8gTg4G5qH/IPuR9fmvv7 6zfr5N3fj2u5IzwTjh1TcWYxmuW5c+lP7jUasNbPgnf1Bmshp7wAq/Y7U7QapvA+rdzIvn4NdU1 yxT4QzGX+anYKczLIDaDMU70vw5ZJU43Zfi0+p7nwQmQWqrMCM77q4EAEoXqONXpQVm5OYFfzth 471LauanBulhmp0TNVYNkHV4npBZWhIScsm/TyAWcvjNU6IeHFs7vvSeu5s4zGwc1WQy8fw5GqT wy13ypP1kTL07mlU/6aKaeq9P3YD3sJPqjXiPbaZEPVMXIkj34ghXHH5m4vjIqX4gzUfBX2mcZC KXJBbzXovfDDZ3FYR6xyVWKwBtAnRVbIc9ZVnJ+D4mfpl77nHs8fbdy+lDBjAojztQGSDOgtXsl 5dOM5s7LKqWbbPZ3yKIptEZPKRD3Sx7/Cy/TwS53IwjTRGLhxOEfUM21dfxurqP5Y5VOMahB+ut 7LEzpbnA+JgPDvnJX/qLZMYd0QdLZyiSWaLnZ+nZCiQLL+KsXwkEYXcs9zNBlQTajaxCVdmTsp6 F9+VaX22ys/R3Pw== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Julien Panis This patch adds support for TPS6593 PMIC on main I2C0 bus. This device provides regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Julien Panis Signed-off-by: Esteban Blanc Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 95 +++++++++++++++++++++++++++++= ++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index cff283c75f8e..2616acab8c0e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -221,6 +221,20 @@ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_C= TL */ }; }; =20 +&mcu_pmx0 { + status =3D "okay"; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ + >; + }; +}; + +&mcu_gpio0 { + status =3D "okay"; +}; + &main_i2c0 { status =3D "okay"; pinctrl-names =3D "default"; @@ -244,6 +258,87 @@ usb_con_hs: endpoint { }; }; }; + + tps659312: pmic@48 { + compatible =3D "ti,tps6593-q1"; + reg =3D <0x48>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells =3D <2>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&mcu_gpio0>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + + buck123-supply =3D <&vcc_3v3_sys>; + buck4-supply =3D <&vcc_3v3_sys>; + buck5-supply =3D <&vcc_3v3_sys>; + ldo1-supply =3D <&vcc_3v3_sys>; + ldo2-supply =3D <&vcc_3v3_sys>; + ldo3-supply =3D <&buck5>; + ldo4-supply =3D <&vcc_3v3_sys>; + + regulators { + buck123: buck123 { + regulator-name =3D "vcc_core"; + regulator-min-microvolt =3D <715000>; + regulator-max-microvolt =3D <895000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name =3D "vcc_1v1"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: buck5 { + regulator-name =3D "vcc_1v8_sys"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name =3D "vddshv5_sdio"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name =3D "vpp_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name =3D "vcc_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: ldo4 { + regulator-name =3D "vdda_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; =20 &main_i2c1 { --=20 2.41.0 From nobody Sun Feb 8 02:56:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46CB8C001B0 for ; Wed, 9 Aug 2023 19:47:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234130AbjHITr3 (ORCPT ); Wed, 9 Aug 2023 15:47:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232289AbjHITrL (ORCPT ); Wed, 9 Aug 2023 15:47:11 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 809042109; Wed, 9 Aug 2023 12:47:11 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl5Yu082664; Wed, 9 Aug 2023 14:47:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691610425; bh=FbAbSqwRAV98u35zcv0xFNhxf2gVaiT10GEUTg0GYws=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=ZovuTH6TuMLeFOC58Dx5PWbSWe055s2QXfHmtkzggX23S1m9TmeNI/fYn4xzMwgqf 7t8ZMJsnAfCN/7962OK1Z/f58DZbAHP9dsLt5la/4k+VulVqESkDrK6Q1/Sn2OvU+t bdkOu7Bc8fyhqxco+SY1BpASgOs7Hxgqc16GSzvY= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379Jl5qL032343 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 14:47:05 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 14:47:05 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 14:47:05 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Jl49g051091; Wed, 9 Aug 2023 14:47:05 -0500 From: Jai Luthra Date: Thu, 10 Aug 2023 01:16:25 +0530 Subject: [PATCH v6 7/7] arm64: defconfig: Enable TPS6593 PMIC for SK-AM62A MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20230810-tps6594-v6-7-2b2e2399e2ef@ti.com> References: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> In-Reply-To: <20230810-tps6594-v6-0-2b2e2399e2ef@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Apurva Nandan CC: , , , Esteban Blanc , , , , , , Vaishnav Achath , Hari Nagalla , Devarsh Thakkar X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=867; i=j-luthra@ti.com; h=from:subject:message-id; bh=hroXKt4UiC2VoiKH6paD4EdlOF8Nc0+Xt9cB4nm60x4=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBk0+00JaLbfPIxMLpqeSZF0hLU3vHBruDLjjEPv dNSRY9aJ4WJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZNPtNAAKCRBD3pH5JJpx RS3CEACLETmwIr+wlznCO3XXAWR0N+fpcJLXE9Soj2+E6mZ1/Fy4yuc1Jcl2PLIJN/kP0JqQpfP 5JeuF3TkHXQDSuvJNeg01B15CSlY/6D6GlI7caJoVbMamHsXucz38zRsngIYoW+p5XLIxIFp9jR lXma/sByjD2XJE+Urzfq8LKmfVmimbNT2tg/xbp8ZfFqIEKa7A2sDlG/crpEKrp6CF8c7EMvrdh xfDfaktkJ8NfuvPoWM8eypT4GdgPgXu/1U0dV5gNhLhgUOLxpCdrrWQSM+AQwbD8faXdJAiRI8i RzECa3qEUr2PN99OxH0kXGqaQ/whgBeZBGNtM1ja00R7nEHHwubgAiuLzdN/T/tKjpmN+DgUNey D2D6j28uMKSy5Id4c7kCej3m+h3e2kLKEV6mMESOXljp7AMvXDC+W96aJ4sNUxo/7Yf0c2e7z7T oyooX+ueRpK3XUTxIchHDair7NpMc08I1ghC7H5LoCvilQNlEha4+WloMdrZGUo/ql7d6JhfsFK ELWYv9+LsNada+k3vJnYGWTRHdlQySVvcXnKcFBjn+kkccVXmSb3XLZO/Vs4JqiZWYAWHjsT5Uz CMbHIHfBksoBOyWYoVoV1j20o3DO+GaCrs1OlnrREDRKdTkk8jymIn69g1ML/Bn3Ja2DLpOald0 b4vF0mEcVf4pIVA== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SK-AM62A-LP uses TPS6593x PMIC (interfaced over I2C) to power the SoC and various other peripherals on the board [1]. Specifically, the audio codec (TLV320AIC3106) on the board relies on the PMIC for the DVDD (1.8V) supply. [1]: https://www.ti.com/lit/zip/sprr459 Reviewed-by: Devarsh Thakkar Signed-off-by: Jai Luthra --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bf13d5c46578..9f7697caa5ca 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -719,6 +719,7 @@ CONFIG_MFD_SEC_CORE=3Dy CONFIG_MFD_SL28CPLD=3Dy CONFIG_RZ_MTU3=3Dy CONFIG_MFD_TPS65219=3Dy +CONFIG_MFD_TPS6594_I2C=3Dm CONFIG_MFD_TI_AM335X_TSCADC=3Dm CONFIG_MFD_ROHM_BD718XX=3Dy CONFIG_MFD_WCD934X=3Dm --=20 2.41.0