From nobody Fri Sep 12 03:08:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0776AEB64DD for ; Wed, 9 Aug 2023 12:50:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232605AbjHIMuf (ORCPT ); Wed, 9 Aug 2023 08:50:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232341AbjHIMua (ORCPT ); Wed, 9 Aug 2023 08:50:30 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C7281FCC for ; Wed, 9 Aug 2023 05:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691585430; x=1723121430; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rp/t14IpXr23atoHWSRr0mV1PUySUm2ThGD6KeIHYNg=; b=aOU5dluLB49aDHzt1doTDqbuW6HejTiq+iElgfQnlgsQc19+SRvMQvJw 6rMg9vNnGm4RKV70ElfuM+Ptao1WbpOlhtwbB1xWaC+ktzEgR/A71sPEJ I/PYN2mmOpFDvMkntVEMcKTHxCsiIN/BbMmbDDAx5jP5138dQ1uP4AkeM e45JZ4+AQ6HTjS5xoGHL9gXfBEeMqBIkJerMrksgATtLoiU5hS+FUn/zn rHCtc65p8HuBx3KZ4F4D0EhIRdquHrwRl1HIM5wNCMviydREp/EUb+Iwc eRcCEnhwzPhuWApTzHbSVB+mHGpbk/tR/Lgr5QOLsj6AFzfDCCCNj10z9 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374821687" X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="374821687" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2023 05:50:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="855521688" X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="855521688" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orsmga004.jf.intel.com with ESMTP; 09 Aug 2023 05:50:28 -0700 From: Lu Baolu To: Joerg Roedel Cc: YueHaibing , Yanfei Xu , Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 03/13] iommu/vt-d: Add domain_flush_pasid_iotlb() Date: Wed, 9 Aug 2023 20:47:56 +0800 Message-Id: <20230809124806.45516-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809124806.45516-1-baolu.lu@linux.intel.com> References: <20230809124806.45516-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The VT-d spec requires to use PASID-based-IOTLB invalidation descriptor to invalidate IOTLB and the paging-structure caches for a first-stage page table. Add a generic helper to do this. RID2PASID is used if the domain has been attached to a physical device, otherwise real PASIDs that the domain has been attached to will be used. The 'real' PASID attachment is handled in the subsequent change. Signed-off-by: Lu Baolu Signed-off-by: Jacob Pan Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20230802212427.1497170-4-jacob.jun.pan@linu= x.intel.com --- drivers/iommu/intel/iommu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 89013a2913af..bb8316fec1aa 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1467,6 +1467,18 @@ static void iommu_flush_dev_iotlb(struct dmar_domain= *domain, spin_unlock_irqrestore(&domain->lock, flags); } =20 +static void domain_flush_pasid_iotlb(struct intel_iommu *iommu, + struct dmar_domain *domain, u64 addr, + unsigned long npages, bool ih) +{ + u16 did =3D domain_id_iommu(domain, iommu); + unsigned long flags; + + spin_lock_irqsave(&domain->lock, flags); + qi_flush_piotlb(iommu, did, IOMMU_NO_PASID, addr, npages, ih); + spin_unlock_irqrestore(&domain->lock, flags); +} + static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, struct dmar_domain *domain, unsigned long pfn, unsigned int pages, @@ -1484,7 +1496,7 @@ static void iommu_flush_iotlb_psi(struct intel_iommu = *iommu, ih =3D 1 << 6; =20 if (domain->use_first_level) { - qi_flush_piotlb(iommu, did, IOMMU_NO_PASID, addr, pages, ih); + domain_flush_pasid_iotlb(iommu, domain, addr, pages, ih); } else { unsigned long bitmask =3D aligned_pages - 1; =20 @@ -1554,7 +1566,7 @@ static void intel_flush_iotlb_all(struct iommu_domain= *domain) u16 did =3D domain_id_iommu(dmar_domain, iommu); =20 if (dmar_domain->use_first_level) - qi_flush_piotlb(iommu, did, IOMMU_NO_PASID, 0, -1, 0); + domain_flush_pasid_iotlb(iommu, dmar_domain, 0, -1, 0); else iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); --=20 2.34.1