From nobody Fri Sep 12 03:07:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 407CFC0015E for ; Wed, 9 Aug 2023 12:51:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232253AbjHIMvU (ORCPT ); Wed, 9 Aug 2023 08:51:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232740AbjHIMvB (ORCPT ); Wed, 9 Aug 2023 08:51:01 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 997A72135 for ; Wed, 9 Aug 2023 05:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691585445; x=1723121445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gc8uxTUf70zvnrXq1dYbH5QztxWkn/Z6QZCZ9eNeV0U=; b=fxrc00g2xn3P4Z3DfKLqPRsSKOjRqQvnOut2M/rWpMPLHw5bM5NavCyH fRlWTiNnxrpPmx41t3nMSmZqHGJCO9kBPEKziDjWd5Jc4pltn5rwSIFpv UZTNleIMS7vJnPCL+IoOa4J38/VbwvzOSmp+gj4EAteG4DnkHEWXF2sze wbLq6TadB2NZ6FYiQnyn5ScqiLdg61agrpNpGQO6kclZ0OymY3EYb6BIc KulHe1dmrJGm/ENOdNNveR6UfsWqZEDx7lC6SjjoaMJtUPrC0/evu1/Ha /8HxvuWVnw7koWFGaMGON9VLcYFb7tj7mqMQJizrcKN4Zk2JhFgYje9uw Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374821763" X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="374821763" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2023 05:50:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="855521861" X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="855521861" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orsmga004.jf.intel.com with ESMTP; 09 Aug 2023 05:50:43 -0700 From: Lu Baolu To: Joerg Roedel Cc: YueHaibing , Yanfei Xu , Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 11/13] iommu/vt-d: Fix to flush cache of PASID directory table Date: Wed, 9 Aug 2023 20:48:04 +0800 Message-Id: <20230809124806.45516-12-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809124806.45516-1-baolu.lu@linux.intel.com> References: <20230809124806.45516-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yanfei Xu Even the PCI devices don't support pasid capability, PASID table is mandatory for a PCI device in scalable mode. However flushing cache of pasid directory table for these devices are not taken after pasid table is allocated as the "size" of table is zero. Fix it by calculating the size by page order. Found this when reading the code, no real problem encountered for now. Fixes: 194b3348bdbb ("iommu/vt-d: Fix PASID directory pointer coherency") Suggested-by: Lu Baolu Signed-off-by: Yanfei Xu Link: https://lore.kernel.org/r/20230616081045.721873-1-yanfei.xu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/pasid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 23dca3bc319d..8f92b92f3d2a 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -129,7 +129,7 @@ int intel_pasid_alloc_table(struct device *dev) info->pasid_table =3D pasid_table; =20 if (!ecap_coherent(info->iommu->ecap)) - clflush_cache_range(pasid_table->table, size); + clflush_cache_range(pasid_table->table, (1 << order) * PAGE_SIZE); =20 return 0; } --=20 2.34.1