From nobody Thu Sep 11 21:22:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7C3AEB64DD for ; Wed, 9 Aug 2023 08:46:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231995AbjHIIqh (ORCPT ); Wed, 9 Aug 2023 04:46:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229587AbjHIIq1 (ORCPT ); Wed, 9 Aug 2023 04:46:27 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B24A81BFB; Wed, 9 Aug 2023 01:46:26 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3798k4EK069890; Wed, 9 Aug 2023 03:46:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691570764; bh=YuNRm8iBp9tWulKkNMVL7zphZImvQaMiWpe5dLEcqRg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GsQ1IaAMgTrw3jt0rY8idGxv7iq2NrOwbV0m/7DhHJEfyk/lW/k8P+tsC7pJ/3C+l IyoiuLkcpfRpVuhHWKbCayOq+5faDmtvzsLLiDZYOSFvAZx4m0RjShaJIPQf6JNBG9 /g8WAyXpKeVBnbWUbH9BTfXVv6XH0xn3kZcnVYmI= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3798k37d067214 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 03:46:04 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 03:46:03 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 03:46:03 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3798k2WU112313; Wed, 9 Aug 2023 03:46:03 -0500 From: Aradhya Bhatia To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Catalin Marinas , Conor Dooley , Will Deacon , Francesco Dolcini CC: Devicetree List , Linux Kernel List , Linux ARM Kernel List , Tomi Valkeinen , Rahul T R , Devarsh Thakkar , Jai Luthra , Jayesh Choudhary , Aradhya Bhatia Subject: [PATCH v5 2/6] arm64: dts: ti: k3-am62-main: Add node for DSS Date: Wed, 9 Aug 2023 14:15:55 +0530 Message-ID: <20230809084559.17322-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230809084559.17322-1-a-bhatia1@ti.com> References: <20230809084559.17322-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Display SubSystem (DSS) DT node for the AM625 SoC. The DSS supports one each of video pipeline (vid) and video-lite pipeline (vidl1). It outputs OLDI signals on one video port (VP1) and DPI signals on another (VP2). The video ports are connected to the pipelines via 2 identical overlay managers (ovr1 and ovr2). Also add the DT node for DSS clock divider. This is a fixed-factor-clock and does not have any register. This comes into effect whenenver OLDI display is used. The input to this divider is a serial clock used by OLDI TXes. The divider divides the input clock by 7, and provides the pixel clock to VP1. Signed-off-by: Aradhya Bhatia --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 25 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62.dtsi | 8 ++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index ef90b2bc81eb..7ce39c91a2af 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -717,6 +717,31 @@ cpts@3d000 { }; }; =20 + dss: dss@30200000 { + compatible =3D "ti,am625-dss"; + reg =3D <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + reg-names =3D "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + power-domains =3D <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 186 6>, + <&dss_vp1_clk>, + <&k3_clks 186 2>; + clock-names =3D "fck", "vp1", "vp2"; + interrupts =3D ; + status =3D "disabled"; + + dss_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + hwspinlock: spinlock@2a000000 { compatible =3D "ti,am64-hwspinlock"; reg =3D <0x00 0x2a000000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k= 3-am62.dtsi index 5e72c445f37a..11f14eef2d44 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -102,6 +102,14 @@ cbass_wakeup: bus@b00000 { }; }; =20 + dss_vp1_clk: clock-divider-oldi { + compatible =3D "fixed-factor-clock"; + clocks =3D <&k3_clks 186 0>; + #clock-cells =3D <0>; + clock-div =3D <7>; + clock-mult =3D <1>; + }; + #include "k3-am62-thermal.dtsi" }; =20 --=20 2.40.1