From nobody Fri Sep 12 01:17:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 590E7C001E0 for ; Wed, 9 Aug 2023 08:19:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231134AbjHIITP (ORCPT ); Wed, 9 Aug 2023 04:19:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230481AbjHIITN (ORCPT ); Wed, 9 Aug 2023 04:19:13 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCF11170B for ; Wed, 9 Aug 2023 01:19:12 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-686ea67195dso4769249b3a.2 for ; Wed, 09 Aug 2023 01:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691569152; x=1692173952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/olz3+pT5vGvwMXGNPW6pUJny4Ruwz46zxkrZbI5uIk=; b=jrHUjZszg5aGthu3ZzuRR0j78xTaWrwJpMn+vkNQr9IJXSakR4x5Ei6YuIp+pJBl0x UNOiXLU3ceDbWiBviK/yfh8Qdz3vxlgYE1JF6+mzFKzKN5k1FvVI/qYfKcm7TFj1h5WV P7/Da4xm8nmh69i7JnsA+wrU++NQOaD4uf2GXGc6IFVrnkBLCRextjiGgMDIeEJC5jO1 sStB4HpxqjEaTSac41m8tNH9PImtWQm7T1InfKdnLT+LbzQcOaPZowLZ1w05kBlTEwZ4 PmwNpC99+17i7mfnGxf53IFmzIf1SB+Ic/cCjYLeXeZ1OVeipjxpu9cHtwgoNPVbaFxt 8Ysw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691569152; x=1692173952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/olz3+pT5vGvwMXGNPW6pUJny4Ruwz46zxkrZbI5uIk=; b=P3ecAgJfeaT6YeZc3b6z7Fqu0NCVdhW0Q7vTrO6aepA8qLy8ksb7bBe/v/8bzlEj5u SiRwXMJWcjhyzwi1UkjOMhCl1sc/9e5saD6T00PTt3uICD2AGTAHXEY5O1YWg0sJTpn8 4w51YX5gWkOeTRh0H8OxuPFgNAfrRvs9YGp5VWHLBxjtwTSutgBte9wHnNQkeFRpUGTy jsOPRkF+R/BurRdYnjn78YCLYKjy/OkU67tS1gUimAiv3Log9ovxtxIxt7D8iBIAFrwL 1Cuc5Hd/qiwIaccdJ97EdGNvP0Czz5VR34XzQSr1IyqmC0rPtyoKVUE4H0xClGgemZVd s6fA== X-Gm-Message-State: AOJu0YxWy7kVuFfiIL/mtfiy11JKqtyZdjTs6LasYzQN0pBNiMBvI0B1 FVnTYm5lwVdAet/S14k6YmSJ X-Google-Smtp-Source: AGHT+IGb/j2HSoijwa29RVJtTy6775ilCzzT+Qk8BKibKLGP8453uYMb168de6FT/MJQOAVUiKpziA== X-Received: by 2002:a05:6a20:cea2:b0:13b:9a09:674b with SMTP id if34-20020a056a20cea200b0013b9a09674bmr1594955pzb.36.1691569152270; Wed, 09 Aug 2023 01:19:12 -0700 (PDT) Received: from localhost.localdomain ([117.207.25.122]) by smtp.gmail.com with ESMTPSA id v13-20020a62a50d000000b00686ee7ba3easm9331881pfm.216.2023.08.09.01.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 01:19:11 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, gustavo.pimentel@synopsys.com, jingoohan1@gmail.com, andersson@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/2] PCI: dwc: Add host_post_init() callback Date: Wed, 9 Aug 2023 13:48:39 +0530 Message-Id: <20230809081840.16034-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230809081840.16034-1-manivannan.sadhasivam@linaro.org> References: <20230809081840.16034-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This callback can be used by the platform drivers to do configuration once all the devices are scanned. Like changing LNKCTL of all downstream devices to enable ASPM etc... Signed-off-by: Manivannan Sadhasivam Tested-by: Steev Klimaszewski --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index cf61733bf78d..5ad42cdc2325 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -505,6 +505,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (ret) goto err_stop_link; =20 + if (pp->ops->host_post_init) + pp->ops->host_post_init(pp); + return 0; =20 err_stop_link: diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 615660640801..e595ae9456da 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -291,6 +291,7 @@ enum dw_pcie_core_rst { struct dw_pcie_host_ops { int (*host_init)(struct dw_pcie_rp *pp); void (*host_deinit)(struct dw_pcie_rp *pp); + void (*host_post_init)(struct dw_pcie_rp *pp); int (*msi_host_init)(struct dw_pcie_rp *pp); }; =20 --=20 2.25.1 From nobody Fri Sep 12 01:17:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F085FC001E0 for ; Wed, 9 Aug 2023 08:19:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230481AbjHIITX (ORCPT ); Wed, 9 Aug 2023 04:19:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229702AbjHIITU (ORCPT ); Wed, 9 Aug 2023 04:19:20 -0400 Received: from mail-oa1-x29.google.com (mail-oa1-x29.google.com [IPv6:2001:4860:4864:20::29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88CC010FF for ; Wed, 9 Aug 2023 01:19:19 -0700 (PDT) Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-1bbaa549c82so5176792fac.0 for ; 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charset="utf-8" ASPM is supported by Qcom host controllers/bridges on most of the recent platforms and so the devices tested so far. But for enabling ASPM by default (without Kconfig/cmdline/sysfs), BIOS has to enable ASPM on both host bridge and downstream devices during boot. Unfortunately, none of the BIOS available on Qcom platforms enables ASPM. Due to this, the platforms making use of Qcom SoCs draw high power during runtime. To fix this power issue, users/distros have to enable ASPM using configs such as (Kconfig/cmdline/sysfs) or the BIOS has to start enabling ASPM. The latter may happen in the future, but that won't address the issue on current platforms. Also, asking users/distros to enable a feature to get the power management right would provide an unpleasant out-of-the-box experience. So the apt solution is to enable ASPM in the controller driver itself. And this is being accomplished by calling pci_enable_link_state() in the newly introduced host_post_init() callback for all the devices connected to the bus. This function enables all supported link low power states for both host bridge and the downstream devices. Due to limited testing, ASPM is only enabled for platforms making use of ops_1_9_0 callbacks. Signed-off-by: Manivannan Sadhasivam Tested-by: Steev Klimaszewski --- drivers/pci/controller/dwc/pcie-qcom.c | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index cee4e400a695..ef843328a9a0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -219,6 +219,7 @@ struct qcom_pcie_ops { int (*get_resources)(struct qcom_pcie *pcie); int (*init)(struct qcom_pcie *pcie); int (*post_init)(struct qcom_pcie *pcie); + void (*host_post_init)(struct qcom_pcie *pcie); void (*deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); @@ -964,6 +965,22 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie = *pcie) return 0; } =20 +static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata) +{ + /* Downstream devices need to be in D0 state before enabling PCI PM subst= ates */ + pci_set_power_state(pdev, PCI_D0); + pci_enable_link_state(pdev, PCIE_LINK_STATE_ALL); + + return 0; +} + +static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) +{ + struct dw_pcie_rp *pp =3D &pcie->pci->pp; + + pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL); +} + static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res =3D &pcie->res.v2_7_0; @@ -1216,9 +1233,19 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp = *pp) pcie->cfg->ops->deinit(pcie); } =20 +static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + + if (pcie->cfg->ops->host_post_init) + pcie->cfg->ops->host_post_init(pcie); +} + static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .host_init =3D qcom_pcie_host_init, .host_deinit =3D qcom_pcie_host_deinit, + .host_post_init =3D qcom_pcie_host_post_init, }; =20 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ @@ -1280,6 +1307,7 @@ static const struct qcom_pcie_ops ops_1_9_0 =3D { .get_resources =3D qcom_pcie_get_resources_2_7_0, .init =3D qcom_pcie_init_2_7_0, .post_init =3D qcom_pcie_post_init_2_7_0, + .host_post_init =3D qcom_pcie_host_post_init_2_7_0, .deinit =3D qcom_pcie_deinit_2_7_0, .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, .config_sid =3D qcom_pcie_config_sid_1_9_0, --=20 2.25.1