From nobody Fri Sep 12 01:20:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0669CC04A6A for ; Tue, 8 Aug 2023 18:12:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235242AbjHHSMT (ORCPT ); Tue, 8 Aug 2023 14:12:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232978AbjHHSLt (ORCPT ); Tue, 8 Aug 2023 14:11:49 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D3601CCD1 for ; Tue, 8 Aug 2023 10:15:23 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-d4df4a2c5dcso3678467276.2 for ; Tue, 08 Aug 2023 10:15:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1691514923; x=1692119723; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Ji+KvWMSPU13IOJE1ECy0uRVoBb1CoTsgnSq9EJiMl4=; b=ym9qCHeScR0OLLCVdAY7O/DXY2TRIlrcOmyDEISMZZIeIzQfOCzZLHSMomWa3+Cldk zev7CBW18/iNpXN3DCS19YQIHL9QmF+xzcQJygxrYQCltZorA0yIb/4SvaejksQmMqz0 u/GtT1fn8sZUjEmDOWZdn1Tl5gAV/cjS+mO/UMwblBOJNl3u2Ej53SoRHtKLSJgFyaLy kgWbEgM1GKcUXQ1+qHS9jYbLD4NUYW0zk9gL1X3BUmbPkcXMF8yTvmOERFYpKv/z+q5n 0OR6KVBuibdmhDXtpcMJUvHkinFX3IvTEEHmiQe3i6YjXCx0Nwt338u0STxvpMJiIqt7 2B/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691514923; x=1692119723; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Ji+KvWMSPU13IOJE1ECy0uRVoBb1CoTsgnSq9EJiMl4=; b=CTsYEtNcrc8GfYU3uxL69SXu0nzZ7jXdZ8OwbpFKxOFtYqjuoYH8ZZCxSsdHqycJJn iwDbkqhUQYHmIGoRg6GwknVXGhi8CIW9MBK9gkQD/wBsOwq04A1L9JEZ95oqzLEjrH7K rjt+55gQ1Kh0XyJu4zVo6H4D34vrzqNsApl1fFnzq3Diw5/zmg3zOuwdIGwXxXHweytz 7TPcMWEP+yp5FCuFeyHgCCOUjYxD91O49GJcVQKXjMHorFi2mZyx5iBJ9UC6cFhudmXY oflK3zpeTKJFwdEegUfR3k7j+oa52Gn7rsWUwuN8inIFa6tf7i+FpPrIbQD09CpEI6bE QX/A== X-Gm-Message-State: AOJu0YyBMoyiHPoRBLQcd/yQCAdOZpEOA7LCZV9edN2XNkDEsm3KHug5 tvEt3FtcpF/gRW8qN33XyW0x9aWTlGKB X-Google-Smtp-Source: AGHT+IHt5QHghXaylFKNfLer4WGR0+VM6KhaaVFTpoIFq6He2ljJmpiLadJ0Xfg78wXFFtWUWt4BuuCx4N8g X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:986a:71d7:3b1e:ac1d]) (user=mshavit job=sendgmr) by 2002:a05:6902:1345:b0:d5d:6bfe:76d6 with SMTP id g5-20020a056902134500b00d5d6bfe76d6mr3212ybu.8.1691514922902; Tue, 08 Aug 2023 10:15:22 -0700 (PDT) Date: Wed, 9 Aug 2023 01:12:02 +0800 In-Reply-To: <20230808171446.2187795-1-mshavit@google.com> Mime-Version: 1.0 References: <20230808171446.2187795-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.640.ga95def55d0-goog Message-ID: <20230809011204.v5.6.Ice063dcf87d1b777a72e008d9e3406d2bcf6d876@changeid> Subject: [PATCH v5 6/9] iommu/arm-smmu-v3: Move CD table to arm_smmu_master From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With this change, each master will now own its own CD table instead of sharing one with other masters attached to the same domain. Attaching a stage 1 domain installs CD entries into the master's CD table. SVA writes its CD entries into each master's CD table if the domain is shared across masters. Reviewed-by: Jason Gunthorpe Signed-off-by: Michael Shavit --- Changes in v5: - Clear the 0th CD entry when the domain is detached. Not clearing it caused a bug in arm_smmu_write_ctx_desc which doesn't expect the entry to already be set. Changes in v4: - Added comment about the cd_table's dependency on the iommu core's group mutex. - Narrowed the range of code for which the domain's init_mutex is held on attach since it now only protects the arm_smmu_domain_finalise call. Changes in v2: - Allocate CD table when it's first needed instead of on probe. Changes in v1: - The master's CD table allocation was previously split to a different commit. This change now atomically allocates the new CD table, uses it, and removes the old one. drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 92 ++++++++++----------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +- 2 files changed, 49 insertions(+), 50 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 34bd7815aeb8e..3f32f9a191a5f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1025,7 +1025,7 @@ static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_ma= ster *master, u32 ssid) unsigned int idx; struct arm_smmu_l1_ctx_desc *l1_desc; struct arm_smmu_device *smmu =3D master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; =20 if (!cdcfg->l1_desc) return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; @@ -1062,7 +1062,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *m= aster, int ssid, u64 val; bool cd_live; __le64 *cdptr; - struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cd_table =3D &master->cd_table; =20 if (WARN_ON(ssid >=3D (1 << cd_table->max_cds_bits))) return -E2BIG; @@ -1125,14 +1125,13 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master = *master, int ssid, return 0; } =20 -static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master *master) +static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master) { int ret; size_t l1size; size_t max_contexts; struct arm_smmu_device *smmu =3D master->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; =20 cdcfg->stall_enabled =3D master->stall_enabled; cdcfg->max_cds_bits =3D master->ssid_bits; @@ -1174,12 +1173,12 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu= _domain *smmu_domain, return ret; } =20 -static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) +static void arm_smmu_free_cd_tables(struct arm_smmu_master *master) { int i; size_t size, l1size; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_ctx_desc_cfg *cdcfg =3D &smmu_domain->cd_table; + struct arm_smmu_device *smmu =3D master->smmu; + struct arm_smmu_ctx_desc_cfg *cdcfg =3D &master->cd_table; =20 if (cdcfg->l1_desc) { size =3D CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3); @@ -1287,7 +1286,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, if (smmu_domain) { switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: - cd_table =3D &smmu_domain->cd_table; + cd_table =3D &master->cd_table; break; case ARM_SMMU_DOMAIN_S2: case ARM_SMMU_DOMAIN_NESTED: @@ -2077,14 +2076,10 @@ static void arm_smmu_domain_free(struct iommu_domai= n *domain) =20 free_io_pgtable_ops(smmu_domain->pgtbl_ops); =20 - /* Free the CD and ASID, if we allocated them */ + /* Free the ASID or VMID */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - struct arm_smmu_ctx_desc_cfg *cd_table =3D &smmu_domain->cd_table; - /* Prevent SVA from touching the CD while we're freeing it */ mutex_lock(&arm_smmu_asid_lock); - if (cd_table->cdtab) - arm_smmu_free_cd_tables(smmu_domain); arm_smmu_free_asid(&smmu_domain->cd); mutex_unlock(&arm_smmu_asid_lock); } else { @@ -2096,7 +2091,7 @@ static void arm_smmu_domain_free(struct iommu_domain = *domain) kfree(smmu_domain); } =20 -static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, +static int arm_smmu_domain_finalise_cd(struct arm_smmu_domain *smmu_domain, struct arm_smmu_master *master, struct io_pgtable_cfg *pgtbl_cfg) { @@ -2115,10 +2110,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_sm= mu_domain *smmu_domain, if (ret) goto out_unlock; =20 - ret =3D arm_smmu_alloc_cd_tables(smmu_domain, master); - if (ret) - goto out_free_asid; - cd->asid =3D (u16)asid; cd->ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; cd->tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | @@ -2130,17 +2121,9 @@ static int arm_smmu_domain_finalise_s1(struct arm_sm= mu_domain *smmu_domain, CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; cd->mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; =20 - ret =3D arm_smmu_write_ctx_desc(master, 0, cd); - if (ret) - goto out_free_cd_tables; - mutex_unlock(&arm_smmu_asid_lock); return 0; =20 -out_free_cd_tables: - arm_smmu_free_cd_tables(smmu_domain); -out_free_asid: - arm_smmu_free_asid(cd); out_unlock: mutex_unlock(&arm_smmu_asid_lock); return ret; @@ -2203,7 +2186,7 @@ static int arm_smmu_domain_finalise(struct iommu_doma= in *domain, ias =3D min_t(unsigned long, ias, VA_BITS); oas =3D smmu->ias; fmt =3D ARM_64_LPAE_S1; - finalise_stage_fn =3D arm_smmu_domain_finalise_s1; + finalise_stage_fn =3D arm_smmu_domain_finalise_cd; break; case ARM_SMMU_DOMAIN_NESTED: case ARM_SMMU_DOMAIN_S2: @@ -2402,6 +2385,16 @@ static void arm_smmu_detach_dev(struct arm_smmu_mast= er *master) master->domain =3D NULL; master->ats_enabled =3D false; arm_smmu_install_ste_for_dev(master); + /* + * The table is uninstalled before clearing the CD to prevent an + * unnecessary sync in arm_smmu_write_ctx_desc. Although clearing the + * CD entry isn't strictly required to detach the domain since the + * table is uninstalled anyway, it's more proper and helps avoid + * confusion in the call to arm_smmu_write_ctx_desc on the next attach + * (which expects the entry to be empty). + */ + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && master->cd_table.cdta= b) + arm_smmu_write_ctx_desc(master, 0, NULL); } =20 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device = *dev) @@ -2436,22 +2429,14 @@ static int arm_smmu_attach_dev(struct iommu_domain = *domain, struct device *dev) if (!smmu_domain->smmu) { smmu_domain->smmu =3D smmu; ret =3D arm_smmu_domain_finalise(domain, master); - if (ret) { + if (ret) smmu_domain->smmu =3D NULL; - goto out_unlock; - } - } else if (smmu_domain->smmu !=3D smmu) { - ret =3D -EINVAL; - goto out_unlock; - } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && - master->ssid_bits !=3D smmu_domain->cd_table.max_cds_bits) { + } else if (smmu_domain->smmu !=3D smmu) ret =3D -EINVAL; - goto out_unlock; - } else if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1 && - smmu_domain->cd_table.stall_enabled !=3D master->stall_enabled) { - ret =3D -EINVAL; - goto out_unlock; - } + + mutex_unlock(&smmu_domain->init_mutex); + if (ret) + return ret; =20 master->domain =3D smmu_domain; =20 @@ -2465,6 +2450,22 @@ static int arm_smmu_attach_dev(struct iommu_domain *= domain, struct device *dev) if (smmu_domain->stage !=3D ARM_SMMU_DOMAIN_BYPASS) master->ats_enabled =3D arm_smmu_ats_supported(master); =20 + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { + if (!master->cd_table.cdtab) { + ret =3D arm_smmu_alloc_cd_tables(master); + if (ret) { + master->domain =3D NULL; + return ret; + } + } + + ret =3D arm_smmu_write_ctx_desc(master, 0, &smmu_domain->cd); + if (ret) { + master->domain =3D NULL; + return ret; + } + } + arm_smmu_install_ste_for_dev(master); =20 spin_lock_irqsave(&smmu_domain->devices_lock, flags); @@ -2472,10 +2473,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *= domain, struct device *dev) spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 arm_smmu_enable_ats(master); - -out_unlock: - mutex_unlock(&smmu_domain->init_mutex); - return ret; + return 0; } =20 static int arm_smmu_map_pages(struct iommu_domain *domain, unsigned long i= ova, @@ -2719,6 +2717,8 @@ static void arm_smmu_release_device(struct device *de= v) arm_smmu_detach_dev(master); arm_smmu_disable_pasid(master); arm_smmu_remove_master(master); + if (master->cd_table.cdtab_dma) + arm_smmu_free_cd_tables(master); kfree(master); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 6066a09c01996..1f3b370257779 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -694,6 +694,8 @@ struct arm_smmu_master { struct arm_smmu_domain *domain; struct list_head domain_head; struct arm_smmu_stream *streams; + /* Locked by the iommu core using the group mutex */ + struct arm_smmu_ctx_desc_cfg cd_table; unsigned int num_streams; bool ats_enabled; bool stall_enabled; @@ -720,11 +722,8 @@ struct arm_smmu_domain { =20 enum arm_smmu_domain_stage stage; union { - struct { struct arm_smmu_ctx_desc cd; - struct arm_smmu_ctx_desc_cfg cd_table; - }; - struct arm_smmu_s2_cfg s2_cfg; + struct arm_smmu_s2_cfg s2_cfg; }; =20 struct iommu_domain domain; --=20 2.41.0.640.ga95def55d0-goog