From nobody Tue Dec 16 09:01:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91DDEC001B0 for ; Tue, 8 Aug 2023 19:14:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233144AbjHHTOw (ORCPT ); Tue, 8 Aug 2023 15:14:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235489AbjHHTOO (ORCPT ); Tue, 8 Aug 2023 15:14:14 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BD6C37C8D; Tue, 8 Aug 2023 09:37:20 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378DZCMq081705; Tue, 8 Aug 2023 08:35:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691501712; bh=Jdf9IIbbApx2Gwl+ovKKLjLw4eP+gnLXtqOc4/6W/Eo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Zm+zUV3f8Ls3evDM/Zs08bqZpz9WpVaPMl6nMBtwp2RR3/kNuawyPc6Y54R1GXQfP yWukXE/F9bubKTZ5nx9RRNVlIv1h5rbIFozhJNm6YxLZMbTMVNhMKGWsz07RlHrgar +GUZzud10UtZphS0D/pP4Bq91J4ji12UEV9OYO2I= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 378DZC0K113479 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Aug 2023 08:35:12 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:11 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:11 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Q2053163; Tue, 8 Aug 2023 08:35:11 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 10/13] arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level Date: Tue, 8 Aug 2023 08:34:54 -0500 Message-ID: <20230808133457.25060-11-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 17 +++-------------- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 3 files changed, 9 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index dee9056f56051..cee2b4b0eb87d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -240,27 +240,16 @@ &main_uart3 { pinctrl-0 =3D <&main_uart3_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; +&main_gpio0 { + status =3D "okay"; }; =20 &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_gpio_pins_default>; }; =20 -&wkup_gpio1 { - status =3D "disabled"; -}; - &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 5d7542ba41b93..6a776f3bbcb19 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -832,6 +832,7 @@ main_gpio0: gpio@600000 { power-domains =3D <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 105 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio2: gpio@610000 { @@ -849,6 +850,7 @@ main_gpio2: gpio@610000 { power-domains =3D <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 107 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio4: gpio@620000 { @@ -866,6 +868,7 @@ main_gpio4: gpio@620000 { power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 109 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio6: gpio@630000 { @@ -883,6 +886,7 @@ main_gpio6: gpio@630000 { power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 111 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_spi0: spi@2100000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 571eb0e2eac92..5ae7320efad7b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 { power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 113 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_gpio1: gpio@42100000 { @@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 { power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 114 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 mcu_navss: bus@28380000 { --=20 2.39.2