From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CC3CC001B0 for ; Tue, 8 Aug 2023 17:48:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235028AbjHHRsi (ORCPT ); Tue, 8 Aug 2023 13:48:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233941AbjHHRsH (ORCPT ); Tue, 8 Aug 2023 13:48:07 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1AD28A7C; Tue, 8 Aug 2023 09:21:22 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ7YM099651; Tue, 8 Aug 2023 08:35:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691501707; bh=ii78j4No8lcqtrUHJW2m2flXO5hcFSHcWifBBAtfUPA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yNU0UUYyvRgVDCytL7HEr6UkimqiiEQQwAnpKPUaJM6MO10Eiqq0kSf9THWN0q3yl Z56AXcF/7RddXQdHwvUOIyqAul3kq+BagucS/pIWWKhS2ZNuN4PlnwhaHya9l7k3vy wIJuuej9h1e0fVWzotcr4DdDttqcU/H7SRvxKeLk= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 378DZ7uJ103150 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Aug 2023 08:35:07 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:05 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:05 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Pr053163; Tue, 8 Aug 2023 08:35:05 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 01/13] arm64: dts: ti: k3-j721e: Enable SDHCI nodes at the board level Date: Tue, 8 Aug 2023 08:34:45 -0500 Message-ID: <20230808133457.25060-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SDHCI nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 7 ++----- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 7 ++----- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 11 +---------- 4 files changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 66aac145e7530..64eed76bbb7a3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -563,6 +563,7 @@ &main_uart0 { =20 &main_sdhci0 { /* eMMC */ + status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; @@ -570,6 +571,7 @@ &main_sdhci0 { =20 &main_sdhci1 { /* SD Card */ + status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv_alt>; pinctrl-names =3D "default"; @@ -578,11 +580,6 @@ &main_sdhci1 { disable-wp; }; =20 -&main_sdhci2 { - /* Unused */ - status =3D "disabled"; -}; - &ospi0 { /* Unused */ status =3D "disabled"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c1cbbae761827..e9b84d2c64b26 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -504,6 +504,7 @@ &wkup_gpio1 { =20 &main_sdhci0 { /* eMMC */ + status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; @@ -511,6 +512,7 @@ &main_sdhci0 { =20 &main_sdhci1 { /* SD/MMC */ + status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv_alt>; pinctrl-names =3D "default"; @@ -519,11 +521,6 @@ &main_sdhci1 { disable-wp; }; =20 -&main_sdhci2 { - /* Unused */ - status =3D "disabled"; -}; - &usb_serdes_mux { idle-states =3D <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 3acd55ffd4ffc..0ca31186b9b74 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1478,6 +1478,7 @@ main_sdhci0: mmc@4f80000 { ti,itap-del-sel-ddr52 =3D <0x3>; ti,trm-icp =3D <0x8>; dma-coherent; + status =3D "disabled"; }; =20 main_sdhci1: mmc@4fb0000 { @@ -1505,6 +1506,7 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; dma-coherent; sdhci-caps-mask =3D <0x2 0x0>; + status =3D "disabled"; }; =20 main_sdhci2: mmc@4f98000 { @@ -1532,6 +1534,7 @@ main_sdhci2: mmc@4f98000 { ti,clkbuf-sel =3D <0x7>; dma-coherent; sdhci-caps-mask =3D <0x2 0x0>; + status =3D "disabled"; }; =20 usbss0: cdns-usb@4104000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 0ee4f38ec8f03..bd1bd1b746056 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -582,13 +582,9 @@ &main_uart1 { pinctrl-0 =3D <&main_uart1_pins_default>; }; =20 -&main_sdhci0 { - /* Unused */ - status =3D "disabled"; -}; - &main_sdhci1 { /* SD Card */ + status =3D "okay"; vmmc-supply =3D <&vdd_mmc1>; vqmmc-supply =3D <&vdd_sd_dv_alt>; pinctrl-names =3D "default"; @@ -597,11 +593,6 @@ &main_sdhci1 { disable-wp; }; =20 -&main_sdhci2 { - /* Unused */ - status =3D "disabled"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F28DC41513 for ; Tue, 8 Aug 2023 19:14:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235461AbjHHTOE (ORCPT ); Tue, 8 Aug 2023 15:14:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234166AbjHHTNq (ORCPT ); Tue, 8 Aug 2023 15:13:46 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A51FC36008; Tue, 8 Aug 2023 09:36:26 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ6im081673; 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Tue, 8 Aug 2023 08:35:06 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Ps053163; Tue, 8 Aug 2023 08:35:05 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 02/13] arm64: dts: ti: k3-j7200: Enable SDHCI nodes at the board level Date: Tue, 8 Aug 2023 08:34:46 -0500 Message-ID: <20230808133457.25060-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SDHCI nodes defined in the top-level J7200 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 92a5414911729..dee9056f56051 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -326,6 +326,7 @@ exp3: gpio@20 { =20 &main_sdhci0 { /* eMMC */ + status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; @@ -333,6 +334,7 @@ &main_sdhci0 { =20 &main_sdhci1 { /* SD card */ + status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; pinctrl-names =3D "default"; vmmc-supply =3D <&vdd_mmc1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 6eaade5aeb423..5d7542ba41b93 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -654,6 +654,7 @@ main_sdhci0: mmc@4f80000 { mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status =3D "disabled"; }; =20 main_sdhci1: mmc@4fb0000 { @@ -677,6 +678,7 @@ main_sdhci1: mmc@4fb0000 { ti,clkbuf-sel =3D <0x7>; ti,trm-icp =3D <0x8>; dma-coherent; + status =3D "disabled"; }; =20 serdes_wiz0: wiz@5060000 { --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9940BC001DB for ; Tue, 8 Aug 2023 17:05:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229955AbjHHRFC (ORCPT ); Tue, 8 Aug 2023 13:05:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229564AbjHHRET (ORCPT ); Tue, 8 Aug 2023 13:04:19 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AABC95C0D0; Tue, 8 Aug 2023 09:01:55 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ7NM025819; Tue, 8 Aug 2023 08:35:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691501707; bh=4LT4963dRldzKkRdy4xE8Yzrplmp7dcMCoa3bbbam/M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cY729KmL/1x6LHmDHB+yGdlaX4++QUepAYjuLHrzH9FugXyi/Wvp3zUZfHcDr/u5m RHzLSPBuSFPIcWOy5GLTpdOqkqlCcsufa0+TT+oVGiu2+geW9sHNEnFoTo2dQkhUx0 wiLrv1pUPRkDr9lw6GVRNF/20WQ56uQP5nQQXBi8= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 378DZ7Q6004682 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Aug 2023 08:35:07 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:07 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:07 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Pt053163; Tue, 8 Aug 2023 08:35:06 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 03/13] arm64: dts: ti: k3-j721s2: Enable SDHCI nodes at the board level Date: Tue, 8 Aug 2023 08:34:47 -0500 Message-ID: <20230808133457.25060-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SDHCI nodes defined in the top-level J721s2 SoC dtsi files are incomplete and will not be functional unless they are extended. As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 6 +----- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++ 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index e6e4133d1e9b9..5fd06cd26b479 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -475,13 +475,9 @@ exp2: gpio@20 { }; }; =20 -&main_sdhci0 { - /* Unused */ - status =3D "disabled"; -}; - &main_sdhci1 { /* SD card */ + status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; pinctrl-names =3D "default"; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e81ef8a7a8a26..7794063b77c8a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -366,6 +366,7 @@ exp2: gpio@22 { =20 &main_sdhci0 { /* eMMC */ + status =3D "okay"; non-removable; ti,driver-strength-ohm =3D <50>; disable-wp; @@ -373,6 +374,7 @@ &main_sdhci0 { =20 &main_sdhci1 { /* SD card */ + status =3D "okay"; pinctrl-0 =3D <&main_mmc1_pins_default>; pinctrl-names =3D "default"; disable-wp; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index dc7920a352373..0e0092fa7b9fb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -737,6 +737,7 @@ main_sdhci0: mmc@4f80000 { mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status =3D "disabled"; }; =20 main_sdhci1: mmc@4fb0000 { @@ -766,6 +767,7 @@ main_sdhci1: mmc@4fb0000 { dma-coherent; /* Masking support for SDR104 capability */ sdhci-caps-mask =3D <0x00000003 0x00000000>; + status =3D "disabled"; }; =20 main_navss: bus@30000000 { --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B54BBC001DE for ; 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Tue, 8 Aug 2023 08:35:08 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:07 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:07 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Pu053163; Tue, 8 Aug 2023 08:35:07 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 04/13] arm64: dts: ti: k3-am65: Enable OSPI nodes at the board level Date: Tue, 8 Aug 2023 08:34:48 -0500 Message-ID: <20230808133457.25060-5-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index e26bd988e5224..6041862d5aa75 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -593,6 +593,7 @@ adc { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 7b1f94a89eca8..2c9c20a9d9179 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -295,6 +295,7 @@ ospi0: spi@47040000 { power-domains =3D <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; =20 ospi1: spi@47050000 { @@ -309,6 +310,7 @@ ospi1: spi@47050000 { power-domains =3D <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index 734b051c97000..aac243bacfeea 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -530,6 +530,7 @@ &mcu_r5fss0_core1 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A055C04A6A for ; Tue, 8 Aug 2023 20:45:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234082AbjHHUpp (ORCPT ); Tue, 8 Aug 2023 16:45:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232759AbjHHUpd (ORCPT ); Tue, 8 Aug 2023 16:45:33 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76865F3A10; Tue, 8 Aug 2023 09:37:06 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ8AE081682; Tue, 8 Aug 2023 08:35:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691501708; bh=fQ/532nBdHyDyg7gVLVsTIcGiqz0ZCTnjYpgJNoX93k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZD+qiHqtPtDYxBm/yEkmNt/uF3HaHm2KpWoM7wUiw8JDlhTNYorIgg0sgIaaO3ytH /oLTEHE1eK25OhMIAdIW9HjBTDlyST7OO5SyM9lHg1RaGlN1P8USMoyqfGcMJlq1Ft dankptUHXIFqJYtTrQk9iQUnVtbAVTe8tIOkdTSQ= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 378DZ8DL028282 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Aug 2023 08:35:08 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:08 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:08 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Pv053163; Tue, 8 Aug 2023 08:35:07 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 05/13] arm64: dts: ti: k3-j721e: Enable OSPI nodes at the board level Date: Tue, 8 Aug 2023 08:34:49 -0500 Message-ID: <20230808133457.25060-6-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 10 ---------- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 6 +----- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 1 + 4 files changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 64eed76bbb7a3..0b89977351c98 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -580,16 +580,6 @@ &main_sdhci1 { disable-wp; }; =20 -&ospi0 { - /* Unused */ - status =3D "disabled"; -}; - -&ospi1 { - /* Unused */ - status =3D "disabled"; -}; - &main_i2c0 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index c1b6f8d7d1898..0c01bdd9656f1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -378,6 +378,7 @@ ospi0: spi@47040000 { power-domains =3D <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; =20 ospi1: spi@47050000 { @@ -392,6 +393,7 @@ ospi1: spi@47050000 { power-domains =3D <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index bd1bd1b746056..4cd5346f2dd59 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -594,6 +594,7 @@ &main_sdhci1 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 @@ -657,11 +658,6 @@ partition@3fc0000 { }; }; =20 -&ospi1 { - /* Unused */ - status =3D "disabled"; -}; - &main_i2c0 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j721e-som-p0.dtsi index e90e43202546e..928d3a8ad2d09 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -202,6 +202,7 @@ eeprom@50 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0319EC001B0 for ; Tue, 8 Aug 2023 17:03:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231266AbjHHRDX (ORCPT ); Tue, 8 Aug 2023 13:03:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233601AbjHHRC3 (ORCPT ); Tue, 8 Aug 2023 13:02:29 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EE755FF1; Tue, 8 Aug 2023 09:01:22 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ9xU025824; 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Tue, 8 Aug 2023 08:35:08 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Pw053163; Tue, 8 Aug 2023 08:35:08 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 06/13] arm64: dts: ti: k3-j7200: Enable OSPI nodes at the board level Date: Tue, 8 Aug 2023 08:34:50 -0500 Message-ID: <20230808133457.25060-7-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index ee7860913c387..571eb0e2eac92 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -544,6 +544,7 @@ ospi0: spi@47040000 { power-domains =3D <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <1>; #size-cells =3D <0>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j7200-som-p0.dtsi index b37f4f88ece4f..5a300d4c8ba03 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -267,6 +267,7 @@ eeprom@50 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; =20 --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B6D5C001B0 for ; Tue, 8 Aug 2023 18:43:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233437AbjHHSnO (ORCPT ); Tue, 8 Aug 2023 14:43:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231565AbjHHSme (ORCPT ); Tue, 8 Aug 2023 14:42:34 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F7C114274; Tue, 8 Aug 2023 09:36:38 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378DZAEV081691; Tue, 8 Aug 2023 08:35:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691501710; bh=Gec+PlfxvHyoRA3dEj4AxO6X7XqqUtC2GWCVDqHinbU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hhCRI64cmzB3sDuEvcQzQD9iaJGkFHmTyj4mIjCqfWnhGLbmHRJqqNJq5tc6HQ/zV X/PCaJ3+vyGVnRoMvkB79rd6PepLjWtA4DxS2KPIiPVa4nBcEojIr4w51xH50XRNO3 lFuWJBFdvRLUyZPmnAJ2n3YNOtH8V69icjaHqbHY= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 378DZA0f004701 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Aug 2023 08:35:10 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:09 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:09 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Px053163; Tue, 8 Aug 2023 08:35:09 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 07/13] arm64: dts: ti: k3-am64: Enable OSPI nodes at the board level Date: Tue, 8 Aug 2023 08:34:51 -0500 Message-ID: <20230808133457.25060-8-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 + arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index 4e3e450e4e4c8..ed1b63b9c1c5f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -794,6 +794,7 @@ ospi0: spi@fc40000 { assigned-clock-parents =3D <&k3_clks 75 7>; assigned-clock-rates =3D <166666666>; power-domains =3D <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index 5606d775153d4..1c2c8f0daca9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -181,6 +181,7 @@ i2c_som_rtc: rtc@52 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index d84e7ee160328..b4a1f73d4fb17 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -520,6 +520,7 @@ &tscadc0 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 963d796a3a970..af06ccd466802 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -518,6 +518,7 @@ &tscadc0 { }; =20 &ospi0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; =20 --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C3BAC07E8D for ; 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Tue, 8 Aug 2023 08:35:10 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:10 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:10 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Q0053163; Tue, 8 Aug 2023 08:35:09 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 08/13] arm64: dts: ti: k3-j721e: Enable GPIO nodes at the board level Date: Tue, 8 Aug 2023 08:34:52 -0500 Message-ID: <20230808133457.25060-9-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GPIO nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 41 +++---------------- .../dts/ti/k3-j721e-common-proc-board.dts | 33 ++++----------- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 + arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 30 ++------------ 5 files changed, 27 insertions(+), 87 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 0b89977351c98..f06e7bda46f01 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -647,52 +647,23 @@ eeprom@50 { }; }; =20 -&main_gpio2 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio3 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio4 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio5 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio6 { - /* Unused */ - status =3D "disabled"; -}; - -&main_gpio7 { - /* Unused */ - status =3D "disabled"; -}; - &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, <&mikro_bus_pins_default>; }; =20 -&wkup_gpio1 { - /* Unused */ - status =3D "disabled"; -}; - &main_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; }; =20 +&main_gpio1 { + status =3D "okay"; +}; + &usb_serdes_mux { idle-states =3D <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index e9b84d2c64b26..824874a7dcb95 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -469,37 +469,18 @@ &main_uart4 { pinctrl-0 =3D <&main_uart4_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio3 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio5 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; -}; - -&main_gpio7 { - status =3D "disabled"; -}; - &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_gpio_pins_default>; }; =20 -&wkup_gpio1 { - status =3D "disabled"; +&main_gpio0 { + status =3D "okay"; +}; + +&main_gpio1 { + status =3D "okay"; }; =20 &main_sdhci0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 0ca31186b9b74..7f663d9280b57 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1339,6 +1339,7 @@ main_gpio0: gpio@600000 { power-domains =3D <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 105 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio1: gpio@601000 { @@ -1355,6 +1356,7 @@ main_gpio1: gpio@601000 { power-domains =3D <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 106 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio2: gpio@610000 { @@ -1372,6 +1374,7 @@ main_gpio2: gpio@610000 { power-domains =3D <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 107 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio3: gpio@611000 { @@ -1388,6 +1391,7 @@ main_gpio3: gpio@611000 { power-domains =3D <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 108 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio4: gpio@620000 { @@ -1405,6 +1409,7 @@ main_gpio4: gpio@620000 { power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 109 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio5: gpio@621000 { @@ -1421,6 +1426,7 @@ main_gpio5: gpio@621000 { power-domains =3D <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 110 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio6: gpio@630000 { @@ -1438,6 +1444,7 @@ main_gpio6: gpio@630000 { power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 111 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio7: gpio@631000 { @@ -1454,6 +1461,7 @@ main_gpio7: gpio@631000 { power-domains =3D <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 112 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_sdhci0: mmc@4f80000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 0c01bdd9656f1..4d107eee9b341 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -281,6 +281,7 @@ wkup_gpio0: gpio@42110000 { power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 113 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_gpio1: gpio@42100000 { @@ -297,6 +298,7 @@ wkup_gpio1: gpio@42100000 { power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 114 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 mcu_i2c0: i2c@40b00000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 4cd5346f2dd59..ed4994d264f26 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -731,41 +731,19 @@ &main_i2c5 { }; =20 &main_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&rpi_header_gpio0_pins_default>; }; =20 &main_gpio1 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&rpi_header_gpio1_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio3 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio5 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; -}; - -&main_gpio7 { - status =3D "disabled"; -}; - -&wkup_gpio1 { - status =3D "disabled"; +&wkup_gpio0 { + status =3D "okay"; }; =20 &usb_serdes_mux { --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23C64C04A6A for ; Tue, 8 Aug 2023 17:49:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235017AbjHHRtM (ORCPT ); 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Tue, 8 Aug 2023 08:35:12 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:11 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:11 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Q1053163; Tue, 8 Aug 2023 08:35:10 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 09/13] arm64: dts: ti: k3-j721s2: Enable GPIO nodes at the board level Date: Tue, 8 Aug 2023 08:34:53 -0500 Message-ID: <20230808133457.25060-10-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GPIO nodes defined in the top-level J721s2 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 18 ++---------------- .../dts/ti/k3-j721s2-common-proc-board.dts | 16 ++++------------ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 4 ++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 4 files changed, 12 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 5fd06cd26b479..5df5946687b34 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -382,31 +382,17 @@ J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_= GPIO0_49 */ }; =20 &main_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&rpi_header_gpio0_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; -}; - &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpi= o0_pins1_default>; }; =20 -&wkup_gpio1 { - status =3D "disabled"; -}; - &wkup_uart0 { status =3D "reserved"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 7794063b77c8a..c6b85bbf9a179 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -299,20 +299,12 @@ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_O= SPI1_LBCLKO */ }; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; +&main_gpio0 { + status =3D "okay"; }; =20 -&wkup_gpio1 { - status =3D "disabled"; +&wkup_gpio0 { + status =3D "okay"; }; =20 &wkup_uart0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 0e0092fa7b9fb..e60f7e18b07dd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -579,6 +579,7 @@ main_gpio0: gpio@600000 { power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 111 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio2: gpio@610000 { @@ -595,6 +596,7 @@ main_gpio2: gpio@610000 { power-domains =3D <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 112 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio4: gpio@620000 { @@ -611,6 +613,7 @@ main_gpio4: gpio@620000 { power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 113 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio6: gpio@630000 { @@ -627,6 +630,7 @@ main_gpio6: gpio@630000 { power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 114 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_i2c0: i2c@2000000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 736ec5fa0ea28..3557f3338377d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -323,6 +323,7 @@ wkup_gpio0: gpio@42110000 { power-domains =3D <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 115 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_gpio1: gpio@42100000 { @@ -339,6 +340,7 @@ wkup_gpio1: gpio@42100000 { power-domains =3D <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 116 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_i2c0: i2c@42120000 { --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91DDEC001B0 for ; Tue, 8 Aug 2023 19:14:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233144AbjHHTOw (ORCPT ); Tue, 8 Aug 2023 15:14:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235489AbjHHTOO (ORCPT ); Tue, 8 Aug 2023 15:14:14 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BD6C37C8D; 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Tue, 8 Aug 2023 08:35:11 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Q2053163; Tue, 8 Aug 2023 08:35:11 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 10/13] arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level Date: Tue, 8 Aug 2023 08:34:54 -0500 Message-ID: <20230808133457.25060-11-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information. Disable the GPIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 17 +++-------------- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 3 files changed, 9 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index dee9056f56051..cee2b4b0eb87d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -240,27 +240,16 @@ &main_uart3 { pinctrl-0 =3D <&main_uart3_pins_default>; }; =20 -&main_gpio2 { - status =3D "disabled"; -}; - -&main_gpio4 { - status =3D "disabled"; -}; - -&main_gpio6 { - status =3D "disabled"; +&main_gpio0 { + status =3D "okay"; }; =20 &wkup_gpio0 { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&wkup_gpio_pins_default>; }; =20 -&wkup_gpio1 { - status =3D "disabled"; -}; - &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 5d7542ba41b93..6a776f3bbcb19 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -832,6 +832,7 @@ main_gpio0: gpio@600000 { power-domains =3D <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 105 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio2: gpio@610000 { @@ -849,6 +850,7 @@ main_gpio2: gpio@610000 { power-domains =3D <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 107 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio4: gpio@620000 { @@ -866,6 +868,7 @@ main_gpio4: gpio@620000 { power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 109 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_gpio6: gpio@630000 { @@ -883,6 +886,7 @@ main_gpio6: gpio@630000 { power-domains =3D <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 111 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 main_spi0: spi@2100000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 571eb0e2eac92..5ae7320efad7b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 { power-domains =3D <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 113 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 wkup_gpio1: gpio@42100000 { @@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 { power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks =3D <&k3_clks 114 0>; clock-names =3D "gpio"; + status =3D "disabled"; }; =20 mcu_navss: bus@28380000 { --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D523C001B0 for ; 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Tue, 8 Aug 2023 08:35:12 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:12 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:12 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Q3053163; Tue, 8 Aug 2023 08:35:11 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 11/13] arm64: dts: ti: k3-j721e: Enable TSCADC nodes at the board level Date: Tue, 8 Aug 2023 08:34:55 -0500 Message-ID: <20230808133457.25060-12-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TSCADC nodes defined in the top-level J721e SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 10 ---------- 4 files changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index f06e7bda46f01..9f3a809ddf90b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -747,6 +747,7 @@ &usb1 { }; =20 &tscadc0 { + status =3D "okay"; /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ adc { ti,adc-channels =3D <0 1 2 3 4 5 6>; @@ -754,6 +755,7 @@ adc { }; =20 &tscadc1 { + status =3D "okay"; /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ adc { ti,adc-channels =3D <0>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 824874a7dcb95..fe5207ac7d85d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -619,12 +619,14 @@ partition@3fe0000 { }; =20 &tscadc0 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; }; =20 &tscadc1 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 4d107eee9b341..37a8c80de3bc5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -411,6 +411,7 @@ tscadc0: tscadc@40200000 { dmas =3D <&main_udmap 0x7400>, <&main_udmap 0x7401>; dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; @@ -430,6 +431,7 @@ tscadc1: tscadc@40210000 { dmas =3D <&main_udmap 0x7402>, <&main_udmap 0x7403>; dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index ed4994d264f26..4032601fd53fa 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -828,16 +828,6 @@ &usb1 { phy-names =3D "cdns3,usb3-phy"; }; =20 -&tscadc0 { - /* Unused */ - status =3D "disabled"; -}; - -&tscadc1 { - /* Unused */ - status =3D "disabled"; -}; - &mcu_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D00EC04A6A for ; Tue, 8 Aug 2023 17:04:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231959AbjHHRER (ORCPT ); Tue, 8 Aug 2023 13:04:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230437AbjHHRDg (ORCPT ); Tue, 8 Aug 2023 13:03:36 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8523519BC3; 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Tue, 8 Aug 2023 08:35:13 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Q4053163; Tue, 8 Aug 2023 08:35:12 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 12/13] arm64: dts: ti: k3-am65: Enable TSCADC nodes at the board level Date: Tue, 8 Aug 2023 08:34:56 -0500 Message-ID: <20230808133457.25060-13-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TSCADC nodes defined in the top-level AM65 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the top-level dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 5 +---- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 ++ 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6041862d5aa75..ba1c14a54acf4 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -582,11 +582,8 @@ &mcu_spi0 { ti,pindir-d0-out-d1-in; }; =20 -&tscadc0 { - status =3D "disabled"; -}; - &tscadc1 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 2c9c20a9d9179..4defde540fe0b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -112,6 +112,7 @@ tscadc0: tscadc@40200000 { dmas =3D <&mcu_udmap 0x7100>, <&mcu_udmap 0x7101 >; dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; @@ -130,6 +131,7 @@ tscadc1: tscadc@40210000 { dmas =3D <&mcu_udmap 0x7102>, <&mcu_udmap 0x7103>; dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index aac243bacfeea..f5c26e9fba987 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -478,12 +478,14 @@ &usb0_phy { }; =20 &tscadc0 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; }; =20 &tscadc1 { + status =3D "okay"; adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; --=20 2.39.2 From nobody Tue Dec 16 03:22:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6BEEC001B0 for ; Tue, 8 Aug 2023 17:02:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233556AbjHHRC3 (ORCPT ); Tue, 8 Aug 2023 13:02:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233670AbjHHRBe (ORCPT ); Tue, 8 Aug 2023 13:01:34 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64393AAF8; Tue, 8 Aug 2023 09:01:05 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378DZEq7025855; Tue, 8 Aug 2023 08:35:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691501714; bh=aGljPDdDeXcDz2W28UkV3gl/mQekjNY+A4wIc1EUsM0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CiRXCpBZjQKKY0Rc/eZeDfoAlkFtreMaUMwucyO1dCvRJehYVCiPRyJ8aPrlWZjhY nzE11g+oyYwbdeVC5wFLKxv3Bb0dYmTp2uCT/wzbARor0rbE7xImh/n21S3gTzjZtF sNSk98/Yp4MTHIoiYQTSlnlosi58nqfyZog4Xn38= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 378DZESY004725 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Aug 2023 08:35:14 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 08:35:13 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 08:35:13 -0500 Received: from fllv0039.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378DZ4Q5053163; Tue, 8 Aug 2023 08:35:13 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dhruva Gole CC: , , , Andrew Davis Subject: [PATCH v2 13/13] arm64: dts: ti: k3-am64: Enable TSCADC nodes at the board level Date: Tue, 8 Aug 2023 08:34:57 -0500 Message-ID: <20230808133457.25060-14-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230808133457.25060-1-afd@ti.com> References: <20230808133457.25060-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TSCADC nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and/or device information. Disable the TSCADC nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Reviewed-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am642-sk.dts | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index ed1b63b9c1c5f..0df54a7418247 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -765,6 +765,7 @@ tscadc0: tscadc@28001000 { assigned-clock-parents =3D <&k3_clks 0 3>; assigned-clock-rates =3D <60000000>; clock-names =3D "fck"; + status =3D "disabled"; =20 adc { #io-channel-cells =3D <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index af06ccd466802..722fd285a34ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -513,10 +513,6 @@ cpsw3g_phy1: ethernet-phy@1 { }; }; =20 -&tscadc0 { - status =3D "disabled"; -}; - &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.39.2